msm: camera: cre: Add batch support in CRE

This change adds the batch mode support in CRE

CRs-Fixed: 2893978
Change-Id: I9a8f9f1f2f555bc875b3d48485b4458a825dbdbd
Signed-off-by: Vikram Sharma <[email protected]>

drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.c

@@ -77,12 +77,12 @@ end:
 }
 
 static int cam_cre_mgr_update_reg_set(struct cam_cre_hw_mgr *hw_mgr,
-	struct cam_cre_request *cre_req)
+	struct cam_cre_request *cre_req, int batch_index)
 {
 	struct cam_cre_dev_reg_set_update reg_set_upd_cmd;
 	int i;
 
-	reg_set_upd_cmd.cre_reg_buf = cre_req->cre_reg_buf;
+	reg_set_upd_cmd.cre_reg_buf = cre_req->cre_reg_buf[batch_index];
 
 	for (i = 0; i < cre_hw_mgr->num_cre; i++) {
 		hw_mgr->cre_dev_intf[i]->hw_ops.process_cmd(
@@ -160,15 +160,15 @@ static int cam_cre_mgr_process_cmd_io_buf_req(struct cam_cre_hw_mgr *hw_mgr,
 
 			for (k = 0; k < io_buf->num_planes; k++) {
 				is_secure = cam_mem_is_secure_buf(
-					io_cfg_ptr[i].mem_handle[k]);
+					io_cfg_ptr[j].mem_handle[k]);
 				if (is_secure)
 					rc = cam_mem_get_io_buf(
-						io_cfg_ptr[i].mem_handle[k],
+						io_cfg_ptr[j].mem_handle[k],
 						hw_mgr->iommu_sec_hdl,
 						&iova_addr, &len);
 				else
 					rc = cam_mem_get_io_buf(
-						io_cfg_ptr[i].mem_handle[k],
+						io_cfg_ptr[j].mem_handle[k],
 						hw_mgr->iommu_hdl,
 						&iova_addr, &len);
 
@@ -177,18 +177,24 @@ static int cam_cre_mgr_process_cmd_io_buf_req(struct cam_cre_hw_mgr *hw_mgr,
 						rc);
 					return -EINVAL;
 				}
-				iova_addr += io_cfg_ptr[i].offsets[k];
+				iova_addr += io_cfg_ptr[j].offsets[k];
 				plane_info = &io_buf->p_info[k];
 
-				plane_info->offset    = io_cfg_ptr[i].offsets[k];
+				plane_info->offset    = io_cfg_ptr[j].offsets[k];
 				plane_info->format    = io_buf->format;
-				plane_info->iova_addr = iova_addr;
+				/*
+				 * TODO: Confirm if the calculation for batch frame offset
+				 * is correct with some experiment in TFE.
+				 */
+				plane_info->iova_addr = iova_addr +
+					((io_cfg_ptr[j].planes[k].plane_stride *
+					  io_cfg_ptr[j].planes[k].slice_height) * i);
 				plane_info->width     =
-					io_cfg_ptr[i].planes[k].width;
+					io_cfg_ptr[j].planes[k].width;
 				plane_info->height    =
-					io_cfg_ptr[i].planes[k].height;
+					io_cfg_ptr[j].planes[k].height;
 				plane_info->stride    =
-					io_cfg_ptr[i].planes[k].plane_stride;
+					io_cfg_ptr[j].planes[k].plane_stride;
 				plane_info->len       = len;
 				plane_info->alignment = alignment;
 			}
@@ -796,9 +802,11 @@ static int cam_cre_mgr_process_cmd(void *priv, void *data)
 
 	hw_mgr = task_data->data;
 	ctx_data->active_req = cre_req;
-	cam_cre_mgr_update_reg_set(hw_mgr, cre_req);
-	cam_cre_ctx_wait_for_idle_irq(ctx_data, cre_req,
+	for (i = 0; i < cre_req->num_batch; i++) {
+		cam_cre_mgr_update_reg_set(hw_mgr, cre_req);
+		cam_cre_ctx_wait_for_idle_irq(ctx_data, cre_req,
 			active_req_idx);
+	}
 
 	mutex_unlock(&hw_mgr->hw_mgr_mutex);
 
@@ -865,10 +873,13 @@ static int32_t cam_cre_mgr_process_msg(void *priv, void *data)
 	} else if ((irq_data.top_irq_status & CAM_CRE_WE_IRQ)
 		&& (irq_data.wr_buf_done)) {
 		/* Signal Buf done */
-		evt_id = CAM_CTX_EVT_ID_SUCCESS;
-		buf_data.evt_param = CAM_SYNC_COMMON_EVENT_SUCCESS;
-		buf_data.request_id = ctx->active_req->request_id;
-		ctx->ctxt_event_cb(ctx->context_priv, evt_id, &buf_data);
+		ctx->active_req->frames_done++;
+		if (ctx->active_req->frames_done == ctx->active_req->num_batch) {
+			evt_id = CAM_CTX_EVT_ID_SUCCESS;
+			buf_data.evt_param = CAM_SYNC_COMMON_EVENT_SUCCESS;
+			buf_data.request_id = ctx->active_req->request_id;
+			ctx->ctxt_event_cb(ctx->context_priv, evt_id, &buf_data);
+		}
 	}
 	mutex_unlock(&ctx->ctx_mutex);
 	return rc;

drivers/cam_cre/cam_cre_hw_mgr/cam_cre_hw_mgr.h

@@ -304,11 +304,12 @@ struct cam_cre_request {
 	uint32_t  req_idx;
 	uint32_t  state;
 	uint32_t  num_batch;
+	uint32_t  frames_done;
 	uint32_t  num_frame_bufs;
 	uint32_t  num_pass_bufs;
 	uint32_t  num_io_bufs[CRE_MAX_BATCH_SIZE];
 	uint32_t  in_resource;
-	struct    cre_reg_buffer cre_reg_buf;
+	struct    cre_reg_buffer cre_reg_buf[CRE_MAX_BATCH_SIZE];
 	struct    cre_debug_buffer cre_debug_buf;
 	struct    cre_io_buf *io_buf[CRE_MAX_BATCH_SIZE][CRE_MAX_IO_BUFS];
 	struct    cam_cre_clk_bw_request clk_info;

drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_rd/cre_bus_rd.c

@@ -57,7 +57,7 @@ static int cam_cre_bus_rd_update(struct cam_cre_hw *cam_cre_hw_info,
 	uint32_t req_idx, temp;
 	uint32_t rm_id;
 	uint32_t rsc_type;
-	uint32_t iova_base, iova_offset;
+	uint32_t iova_base;
 	struct cam_hw_prepare_update_args *prepare_args;
 	struct cam_cre_ctx *ctx_data;
 	struct cam_cre_request *cre_request;
@@ -131,19 +131,11 @@ static int cam_cre_bus_rd_update(struct cam_cre_hw *cam_cre_hw_info,
 			(rd_reg->offset + rd_reg_client->ccif_meta_data),
 			temp);
 
-		/*
-		 * As CRE have 36 Bit addressing support Image Address
-		 * register will have 32 bit MSB of 36 bit iova.
-		 * and addr_config will have 8 bit byte offset.
-		 */
-		iova_base = (io_buf->p_info[k].iova_addr & 0xffffff00) >> 8;
+		/* Image Address */
+		iova_base = io_buf->p_info[k].iova_addr;
 		update_cre_reg_set(cre_reg_buf,
 			rd_reg->offset + rd_reg_client->img_addr,
 			iova_base);
-		iova_offset = io_buf->p_info[k].iova_addr & 0xff;
-		update_cre_reg_set(cre_reg_buf,
-			rd_reg->offset + rd_reg_client->addr_cfg,
-			iova_offset);
 
 		/* Buffer size */
 		update_cre_reg_set(cre_reg_buf,
@@ -211,7 +203,6 @@ static int cam_cre_bus_rd_prepare(struct cam_cre_hw *cam_cre_hw_info,
 	req_idx = prepare->req_idx;
 
 	cre_request = ctx_data->req_list[req_idx];
-	cre_reg_buf = &cre_request->cre_reg_buf;
 
 	CAM_DBG(CAM_CRE, "req_idx = %d req_id = %lld",
 		req_idx, cre_request->request_id);
@@ -220,6 +211,7 @@ static int cam_cre_bus_rd_prepare(struct cam_cre_hw *cam_cre_hw_info,
 	rd_reg_val = cam_cre_hw_info->bus_rd_reg_val;
 
 	for (i = 0; i < cre_request->num_batch; i++) {
+		cre_reg_buf = &cre_request->cre_reg_buf[i];
 		for (j = 0; j < cre_request->num_io_bufs[i]; j++) {
 			io_buf = cre_request->io_buf[i][j];
 			if (io_buf->direction != CAM_BUF_INPUT)
@@ -233,15 +225,15 @@ static int cam_cre_bus_rd_prepare(struct cam_cre_hw *cam_cre_hw_info,
 			if (rc)
 				goto end;
 		}
-	}
 
-	/* Go command */
-	temp = 0;
-	temp |= rd_reg_val->go_cmd;
-	temp |= rd_reg_val->static_prg & rd_reg_val->static_prg_mask;
-	update_cre_reg_set(cre_reg_buf,
-		rd_reg->offset + rd_reg->input_if_cmd,
-		temp);
+		/* Go command */
+		temp = 0;
+		temp |= rd_reg_val->go_cmd;
+		temp |= rd_reg_val->static_prg & rd_reg_val->static_prg_mask;
+		update_cre_reg_set(cre_reg_buf,
+			rd_reg->offset + rd_reg->input_if_cmd,
+			temp);
+	}
 end:
 	return 0;
 }

drivers/cam_cre/cam_cre_hw_mgr/cre_hw/bus_wr/cre_bus_wr.c

@@ -89,7 +89,7 @@ static int cam_cre_bus_wr_update(struct cam_cre_hw *cam_cre_hw_info,
 	uint32_t req_idx;
 	uint32_t temp = 0;
 	uint32_t wm_port_id;
-	uint32_t iova_base, iova_offset;
+	uint32_t iova_base;
 	struct cam_hw_prepare_update_args *prepare_args;
 	struct cam_cre_ctx *ctx_data;
 	struct cam_cre_request *cre_request;
@@ -159,19 +159,11 @@ static int cam_cre_bus_wr_update(struct cam_cre_hw *cam_cre_hw_info,
 			wr_reg->offset + wr_reg_client->client_cfg,
 			temp);
 
-		/*
-		 * As CRE have 36 Bit addressing support Image Address
-		 * register will have 32 bit MSB of 36 bit iova.
-		 * and addr_config will have 8 bit byte offset.
-		 */
-		iova_base = (io_buf->p_info[k].iova_addr & 0xffffff00) >> 8;
+		/* Image Address */
+		iova_base = io_buf->p_info[k].iova_addr;
 		update_cre_reg_set(cre_reg_buf,
 			wr_reg->offset + wr_reg_client->img_addr,
 			iova_base);
-		iova_offset = io_buf->p_info[k].iova_addr & 0xff;
-		update_cre_reg_set(cre_reg_buf,
-			wr_reg->offset + wr_reg_client->addr_cfg,
-			iova_offset);
 
 		/* Buffer size */
 		temp = 0;
@@ -236,12 +228,12 @@ static int cam_cre_bus_wr_prepare(struct cam_cre_hw *cam_cre_hw_info,
 	bus_wr_ctx = wr_info->bus_wr_ctx[ctx_id];
 
 	cre_request = ctx_data->req_list[req_idx];
-	cre_reg_buf = &cre_request->cre_reg_buf;
 
 	CAM_DBG(CAM_CRE, "req_idx = %d req_id = %lld num_io_bufs = %d",
 		req_idx, cre_request->request_id, cre_request->num_io_bufs[0]);
 
 	for (i = 0; i < cre_request->num_batch; i++) {
+		cre_reg_buf = &cre_request->cre_reg_buf[i];
 		for (j = 0; j < cre_request->num_io_bufs[i]; j++) {
 			io_buf = cre_request->io_buf[i][j];
 			CAM_DBG(CAM_CRE, "batch = %d io buf num = %d dir = %d",

drivers/cam_cre/cam_cre_hw_mgr/cre_hw/cre_core.c

@@ -100,20 +100,20 @@ static int cam_cre_dev_process_init(struct cam_cre_hw *cre_hw,
 	if (rc)
 		goto top_init_fail;
 
-	rc = cam_cre_bus_rd_process(cre_hw, 0, CRE_HW_INIT, cmd_args);
-		if (rc)
-			goto bus_rd_init_fail;
-
 	rc = cam_cre_bus_wr_process(cre_hw, 0, CRE_HW_INIT, cmd_args);
 		if (rc)
 			goto bus_wr_init_fail;
 
+	rc = cam_cre_bus_rd_process(cre_hw, 0, CRE_HW_INIT, cmd_args);
+		if (rc)
+			goto bus_rd_init_fail;
+
 	return rc;
 
-bus_wr_init_fail:
-	rc = cam_cre_bus_rd_process(cre_hw, 0,
-		CRE_HW_DEINIT, NULL);
 bus_rd_init_fail:
+	rc = cam_cre_bus_wr_process(cre_hw, 0,
+		CRE_HW_DEINIT, NULL);
+bus_wr_init_fail:
 	rc = cam_cre_top_process(cre_hw, 0,
 		CRE_HW_DEINIT, NULL);
 top_init_fail:
@@ -274,10 +274,10 @@ static int cam_cre_dev_process_release(struct cam_cre_hw *cre_hw, void *cmd_args
 	rc = cam_cre_top_process(cre_hw, cre_dev_release->ctx_id,
 		CRE_HW_RELEASE, NULL);
 
-	rc |= cam_cre_bus_rd_process(cre_hw, cre_dev_release->ctx_id,
+	rc |= cam_cre_bus_wr_process(cre_hw, cre_dev_release->ctx_id,
 		CRE_HW_RELEASE, NULL);
 
-	rc |= cam_cre_bus_wr_process(cre_hw, cre_dev_release->ctx_id,
+	rc |= cam_cre_bus_rd_process(cre_hw, cre_dev_release->ctx_id,
 		CRE_HW_RELEASE, NULL);
 
 	return rc;
@@ -300,22 +300,22 @@ static int cam_cre_dev_process_acquire(struct cam_cre_hw *cre_hw, void *cmd_args
 	if (rc)
 		goto top_acquire_fail;
 
-	rc = cam_cre_bus_rd_process(cre_hw, cre_dev_acquire->ctx_id,
+	rc = cam_cre_bus_wr_process(cre_hw, cre_dev_acquire->ctx_id,
 		CRE_HW_ACQUIRE, cre_dev_acquire->cre_acquire);
 	if (rc)
-		goto bus_rd_acquire_fail;
+		goto bus_wr_acquire_fail;
 
-	rc = cam_cre_bus_wr_process(cre_hw, cre_dev_acquire->ctx_id,
+	rc = cam_cre_bus_rd_process(cre_hw, cre_dev_acquire->ctx_id,
 		CRE_HW_ACQUIRE, cre_dev_acquire->cre_acquire);
 	if (rc)
-		goto bus_wr_acquire_fail;
+		goto bus_rd_acquire_fail;
 
 	return 0;
 
-bus_wr_acquire_fail:
-	cam_cre_bus_rd_process(cre_hw, cre_dev_acquire->ctx_id,
-		CRE_HW_RELEASE, cre_dev_acquire->cre_acquire);
 bus_rd_acquire_fail:
+	cam_cre_bus_wr_process(cre_hw, cre_dev_acquire->ctx_id,
+		CRE_HW_RELEASE, cre_dev_acquire->cre_acquire);
+bus_wr_acquire_fail:
 	cam_cre_top_process(cre_hw, cre_dev_acquire->ctx_id,
 		CRE_HW_RELEASE, cre_dev_acquire->cre_acquire);
 top_acquire_fail:
@@ -334,12 +334,12 @@ static int cam_cre_dev_process_reg_set_update(struct cam_cre_hw *cre_hw, void *c
 	if (rc)
 		goto end;
 
-	rc = cam_cre_bus_rd_process(cre_hw, 0,
+	rc = cam_cre_bus_wr_process(cre_hw, 0,
 		CRE_HW_REG_SET_UPDATE, reg_set_update);
 	if (rc)
 		goto end;
 
-	rc = cam_cre_bus_wr_process(cre_hw, 0,
+	rc = cam_cre_bus_rd_process(cre_hw, 0,
 		CRE_HW_REG_SET_UPDATE, reg_set_update);
 	if (rc)
 		goto end;
@@ -360,13 +360,13 @@ static int cam_cre_dev_process_prepare(struct cam_cre_hw *cre_hw, void *cmd_args
 	if (rc)
 		goto end;
 
-	rc = cam_cre_bus_rd_process(cre_hw,
+	rc = cam_cre_bus_wr_process(cre_hw,
 		cre_dev_prepare_req->ctx_data->ctx_id,
 		CRE_HW_PREPARE, cre_dev_prepare_req);
 	if (rc)
 		goto end;
 
-	rc = cam_cre_bus_wr_process(cre_hw,
+	rc = cam_cre_bus_rd_process(cre_hw,
 		cre_dev_prepare_req->ctx_data->ctx_id,
 		CRE_HW_PREPARE, cre_dev_prepare_req);
 	if (rc)
@@ -380,8 +380,8 @@ static int cam_cre_dev_process_probe(struct cam_cre_hw *cre_hw,
 	void *cmd_args)
 {
 	cam_cre_top_process(cre_hw, -1, CRE_HW_PROBE, NULL);
-	cam_cre_bus_rd_process(cre_hw, -1, CRE_HW_PROBE, NULL);
 	cam_cre_bus_wr_process(cre_hw, -1, CRE_HW_PROBE, NULL);
+	cam_cre_bus_rd_process(cre_hw, -1, CRE_HW_PROBE, NULL);
 
 	return 0;
 }
@@ -561,10 +561,10 @@ irqreturn_t cam_cre_irq(int irq_num, void *data)
 
 	cam_cre_top_process(cre_hw, 0, CRE_HW_ISR, &irq_data);
 
-	if (irq_data.top_irq_status & CAM_CRE_FE_IRQ)
-		cam_cre_bus_rd_process(cre_hw, 0, CRE_HW_ISR, &irq_data);
 	if (irq_data.top_irq_status & CAM_CRE_WE_IRQ)
 		cam_cre_bus_wr_process(cre_hw, 0, CRE_HW_ISR, &irq_data);
+	if (irq_data.top_irq_status & CAM_CRE_FE_IRQ)
+		cam_cre_bus_rd_process(cre_hw, 0, CRE_HW_ISR, &irq_data);
 
 	spin_lock(&cre_dev->hw_lock);
 	if (core_info->irq_cb.cre_hw_mgr_cb && core_info->irq_cb.data)