Merge "msm: camera: icp: Add WD clear logic for lx7" into camera-kernel.lnx.5.0
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@@ -857,8 +857,15 @@ irqreturn_t cam_lx7_handle_irq(int irq_num, void *data)
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cam_io_w_mb(status, cirq_base + ICP_LX7_CIRQ_OB_CLEAR);
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cam_io_w_mb(status, cirq_base + ICP_LX7_CIRQ_OB_CLEAR);
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cam_io_w_mb(LX7_IRQ_CLEAR_CMD, cirq_base + ICP_LX7_CIRQ_OB_IRQ_CMD);
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cam_io_w_mb(LX7_IRQ_CLEAR_CMD, cirq_base + ICP_LX7_CIRQ_OB_IRQ_CMD);
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if (status & (LX7_WDT_BITE_WS0 | LX7_WDT_BITE_WS1)) {
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if (status & LX7_WDT_BITE_WS0) {
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CAM_ERR_RATE_LIMIT(CAM_ICP, "got watchdog interrupt from LX7");
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/* WD clear sequence - SW listens only to WD0 */
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cam_io_w_mb(0x0,
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lx7_info->soc_info.reg_map[LX7_WD0_BASE].mem_base +
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ICP_LX7_WD_CTRL);
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cam_io_w_mb(0x1,
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lx7_info->soc_info.reg_map[LX7_WD0_BASE].mem_base +
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ICP_LX7_WD_INTCLR);
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CAM_ERR_RATE_LIMIT(CAM_ICP, "Fatal: Watchdog Bite from LX7");
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recover = true;
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recover = true;
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}
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}
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@@ -15,6 +15,7 @@
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enum cam_lx7_reg_base {
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enum cam_lx7_reg_base {
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LX7_CSR_BASE,
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LX7_CSR_BASE,
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LX7_CIRQ_BASE,
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LX7_CIRQ_BASE,
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LX7_WD0_BASE,
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LX7_SYS_BASE,
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LX7_SYS_BASE,
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LX7_BASE_MAX,
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LX7_BASE_MAX,
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};
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};
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@@ -20,6 +20,10 @@
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#define ICP_LX7_CIRQ_OB_CLEAR 0x4
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#define ICP_LX7_CIRQ_OB_CLEAR 0x4
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#define ICP_LX7_CIRQ_OB_STATUS 0xc
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#define ICP_LX7_CIRQ_OB_STATUS 0xc
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/* ICP WD reg space */
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#define ICP_LX7_WD_CTRL 0x8
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#define ICP_LX7_WD_INTCLR 0xC
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/* These bitfields are shared by OB_MASK, OB_CLEAR, OB_STATUS */
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/* These bitfields are shared by OB_MASK, OB_CLEAR, OB_STATUS */
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#define LX7_WDT_BITE_WS1 (1 << 6)
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#define LX7_WDT_BITE_WS1 (1 << 6)
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#define LX7_WDT_BARK_WS1 (1 << 5)
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#define LX7_WDT_BARK_WS1 (1 << 5)
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