msm: camera: csiphy: Secure cam usecase not working

Secure CP control register always assume that it contains 7 bit
mask for each PHY. But this register format is different based on
target. Update secure CP control bitmask generation logic for each
PHY index based on phy_version.
So we have below 3 combinations to handle at SW.
1.Old Titan Targets : 7 bits for each PHY.
2.PHY 1_2_1 : for 4 pHYS 7 bits and for
remaining 2 PHYs 8 bits are reserved.
3.Mimas (PHY 2_0_1): 8 bits for each PHY.

CRs-Fixed: 2624698
Change-Id: Iac4c3c718fc96a51592e07b45458fb045c52366d
Signed-off-by: Anil Kumar Kanakanti <akanakan@codeaurora.org>

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/module.h>
@@ -19,6 +19,9 @@
 #define LANE_MASK_2PH 0x1F
 #define LANE_MASK_3PH 0x7
 
+#define SEC_LANE_CP_REG_LEN 32
+#define MAX_PHY_MSK_PER_REG 4
+
 static int csiphy_dump;
 module_param(csiphy_dump, int, 0644);
 
@@ -80,7 +83,7 @@ int32_t cam_csiphy_update_secure_info(
 	struct cam_csiphy_info  *cam_cmd_csiphy_info,
 	struct cam_config_dev_cmd *cfg_dev)
 {
-	uint32_t clock_lane, adj_lane_mask, temp;
+	uint32_t clock_lane, adj_lane_mask, temp, phy_mask_len;
 	int32_t offset;
 
 	if (csiphy_dev->acquire_count >=
@@ -114,12 +117,37 @@ int32_t cam_csiphy_update_secure_info(
 
 	csiphy_dev->csiphy_info.secure_mode[offset] = 1;
 
-	csiphy_dev->csiphy_cpas_cp_reg_mask[offset] =
-		adj_lane_mask << (csiphy_dev->soc_info.index *
-		(CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES) +
-		(!cam_cmd_csiphy_info->csiphy_3phase) *
-		(CAM_CSIPHY_MAX_CPHY_LANES));
+	if (csiphy_dev->hw_version == CSIPHY_VERSION_V201) {
+		phy_mask_len = CAM_CSIPHY_MAX_DPHY_LANES +
+			CAM_CSIPHY_MAX_CPHY_LANES + 1;
+	} else if (csiphy_dev->hw_version == CSIPHY_VERSION_V121) {
+		phy_mask_len =
+			(csiphy_dev->soc_info.index < MAX_PHY_MSK_PER_REG) ?
+			CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES :
+			CAM_CSIPHY_MAX_DPHY_LANES +
+			CAM_CSIPHY_MAX_CPHY_LANES + 1;
+	} else {
+		phy_mask_len = CAM_CSIPHY_MAX_DPHY_LANES +
+			CAM_CSIPHY_MAX_CPHY_LANES;
+	}
 
+	if (csiphy_dev->soc_info.index < MAX_PHY_MSK_PER_REG) {
+		csiphy_dev->csiphy_cpas_cp_reg_mask[offset] =
+			((uint64_t)adj_lane_mask) <<
+			(csiphy_dev->soc_info.index * phy_mask_len +
+			(!cam_cmd_csiphy_info->csiphy_3phase) *
+			(CAM_CSIPHY_MAX_CPHY_LANES));
+	} else {
+		csiphy_dev->csiphy_cpas_cp_reg_mask[offset] =
+			((uint64_t)adj_lane_mask) <<
+			((csiphy_dev->soc_info.index - MAX_PHY_MSK_PER_REG) *
+			phy_mask_len + SEC_LANE_CP_REG_LEN +
+			(!cam_cmd_csiphy_info->csiphy_3phase) *
+			(CAM_CSIPHY_MAX_CPHY_LANES));
+	}
+	CAM_DBG(CAM_CSIPHY, "csi phy idx:%d, cp_reg_mask:0x%lx",
+		csiphy_dev->soc_info.index,
+		csiphy_dev->csiphy_cpas_cp_reg_mask[offset]);
 	return 0;
 }
 
@@ -216,6 +244,24 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev,
 		cam_csiphy_update_secure_info(csiphy_dev,
 			cam_cmd_csiphy_info, cfg_dev);
 
+	CAM_DBG(CAM_CSIPHY,
+		"phy version_%d, lane count:%d, mask:0x%x",
+		csiphy_dev->hw_version,
+		csiphy_dev->csiphy_info.lane_cnt,
+		csiphy_dev->csiphy_info.lane_mask
+	);
+	CAM_DBG(CAM_CSIPHY,
+		"3phase:%d, combo mode:%d, secure mode:%d",
+		csiphy_dev->csiphy_info.csiphy_3phase,
+		csiphy_dev->csiphy_info.combo_mode,
+		cam_cmd_csiphy_info->secure_mode
+	);
+	CAM_DBG(CAM_CSIPHY,
+		"phy idx:%d, settle time:%d, datarate:%d",
+		csiphy_dev->soc_info.index,
+		csiphy_dev->csiphy_info.settle_time,
+		csiphy_dev->csiphy_info.data_rate);
+
 	return rc;
 }
 

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c

@@ -370,6 +370,23 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
 		csiphy_dev->is_divisor_32_comp = false;
 		csiphy_dev->clk_lane = 0;
 		csiphy_dev->ctrl_reg->data_rates_settings_table = NULL;
+	} else if (of_device_is_compatible(soc_info->dev->of_node,
+		"qcom,csiphy-v2.0.1")) {
+		csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_0_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg =
+			csiphy_2ph_v2_0_combo_mode_reg;
+		csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v2_0_reg;
+		csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
+		csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_2_0;
+		csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_2_0;
+		csiphy_dev->ctrl_reg->csiphy_reset_reg = csiphy_reset_reg_2_0;
+		csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v2_0;
+		csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default;
+		csiphy_dev->hw_version = CSIPHY_VERSION_V201;
+		csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW;
+		csiphy_dev->is_divisor_32_comp = false;
+		csiphy_dev->clk_lane = 0;
+		csiphy_dev->ctrl_reg->data_rates_settings_table = NULL;
 	} else {
 		CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x",
 			csiphy_dev->hw_version);

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h

@@ -32,6 +32,7 @@
 #define CSIPHY_VERSION_V121                       0x121
 #define CSIPHY_VERSION_V123                       0x123
 #define CSIPHY_VERSION_V20                        0x20
+#define CSIPHY_VERSION_V201                       0x201
 
 /**
  * @csiphy_dev: CSIPhy device structure