From ea7b6b2312b37d6eae998ed35f877cb106198e3c Mon Sep 17 00:00:00 2001 From: Jigar Agrawal Date: Fri, 24 Jul 2020 17:55:27 -0700 Subject: [PATCH] msm: camera: csiphy: Add Skew calibration in DPHY Programming Sequence Update register pragramming sequence to account for signal skew calibration for DPHY single and combo mode for per lane data rates higher than 1.5 Gbps for CSIPHY1.2.3 and CSIPHY 2.1.0. Also, move settle time register update in data specific table, as settle time is pre calculated based on datarate and need to configure accordingly. CRs-fixed: 2697576 Change-Id: I428d8d14887aa54ff22d727f80ee4a395be76baf Signed-off-by: Jigar Agrawal --- .../include/cam_csiphy_1_2_3_hwreg.h | 90 +++++++++++++++---- .../include/cam_csiphy_2_1_0_hwreg.h | 42 ++++++++- 2 files changed, 116 insertions(+), 16 deletions(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_3_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_3_hwreg.h index 2c66175742..e626c13a70 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_3_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_3_hwreg.h @@ -15,8 +15,8 @@ struct csiphy_reg_parms_t csiphy_v1_2_3 = { .csiphy_interrupt_status_size = 11, .csiphy_common_array_size = 8, .csiphy_reset_array_size = 5, - .csiphy_2ph_config_array_size = 16, - .csiphy_3ph_config_array_size = 28, + .csiphy_2ph_config_array_size = 19, + .csiphy_3ph_config_array_size = 26, .csiphy_2ph_3ph_config_array_size = 0, .csiphy_2ph_clock_lane = 0x1, .csiphy_2ph_combo_ck_ln = 0x10, @@ -73,6 +73,9 @@ csiphy_reg_t csiphy_2ph_v1_2_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x005C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0060, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { @@ -91,6 +94,9 @@ csiphy_reg_t csiphy_2ph_v1_2_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x075C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0760, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0764, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { @@ -109,6 +115,9 @@ csiphy_reg_t csiphy_2ph_v1_2_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x025C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0260, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0264, 0x7F, 0x00, CSIPHY_SKEW_CAL}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { @@ -127,6 +136,9 @@ csiphy_reg_t csiphy_2ph_v1_2_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x045C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0460, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { @@ -145,6 +157,9 @@ csiphy_reg_t csiphy_2ph_v1_2_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x065C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0660, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0664, 0x7F, 0x00, CSIPHY_SKEW_CAL}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, }, }; @@ -167,6 +182,9 @@ struct csiphy_reg_t {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x005C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0060, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { @@ -185,6 +203,9 @@ struct csiphy_reg_t {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x075C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0760, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0764, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { @@ -203,6 +224,9 @@ struct csiphy_reg_t {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x025C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0260, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0264, 0x7F, 0x00, CSIPHY_SKEW_CAL}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { @@ -221,6 +245,9 @@ struct csiphy_reg_t {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x045C, 0xC0, 0x00, CSIPHY_SKEW_CAL}, + {0x0460, 0x0D, 0x00, CSIPHY_SKEW_CAL}, + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { @@ -239,6 +266,9 @@ struct csiphy_reg_t {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x065C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0660, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0664, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }, }; @@ -254,8 +284,6 @@ csiphy_reg_t csiphy_3ph_v1_2_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x016C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x015C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0188, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -284,8 +312,6 @@ csiphy_reg_t csiphy_3ph_v1_2_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x036C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x035C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0388, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -314,8 +340,6 @@ csiphy_reg_t csiphy_3ph_v1_2_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x056C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x055C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0588, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -343,29 +367,41 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = { { /* (2.5 * 10**3 * 2.28) rounded value*/ .bandwidth = 5700000000, - .data_rate_reg_array_size = 2, + .data_rate_reg_array_size = 4, .per_lane_info = { { .lane_identifier = CPHY_LANE_0, .csiphy_data_rate_regs = { + {0x010C, 0x12, 0x00, + CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, + CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x144, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x9B4, 0x03, 0x00, + {0x9B4, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, }, }, { .lane_identifier = CPHY_LANE_1, .csiphy_data_rate_regs = { + {0x030C, 0x12, 0x00, + CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, + CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x344, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0xAB4, 0x03, 0x00, + {0xAB4, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS}, }, }, { .lane_identifier = CPHY_LANE_2, .csiphy_data_rate_regs = { + {0x050C, 0x12, 0x00, + CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, + CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, {0xBB4, 0x03, 0x0A, @@ -377,11 +413,15 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = { { /* (3.5 * 10**3 * 2.28) rounded value */ .bandwidth = 7980000000, - .data_rate_reg_array_size = 4, + .data_rate_reg_array_size = 6, .per_lane_info = { { .lane_identifier = CPHY_LANE_0, .csiphy_data_rate_regs = { + {0x010C, 0x08, 0x00, + CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, + CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x988, 0x05, 0x00, @@ -395,6 +435,10 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = { { .lane_identifier = CPHY_LANE_1, .csiphy_data_rate_regs = { + {0x030C, 0x08, 0x00, + CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, + CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, {0xA88, 0x05, 0x00, @@ -408,7 +452,11 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = { { .lane_identifier = CPHY_LANE_2, .csiphy_data_rate_regs = { - {0x344, 0xB2, 0x00, + {0x050C, 0x08, 0x00, + CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, + CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, {0xB88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -423,11 +471,15 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = { { /* (4.5 * 10**3 * 2.28) rounded value */ .bandwidth = 10260000000, - .data_rate_reg_array_size = 4, + .data_rate_reg_array_size = 6, .per_lane_info = { { .lane_identifier = CPHY_LANE_0, .csiphy_data_rate_regs = { + {0x010C, 0x08, 0x00, + CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0108, 0x00, 0x00, + CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x988, 0x05, 0x00, @@ -441,6 +493,10 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = { { .lane_identifier = CPHY_LANE_1, .csiphy_data_rate_regs = { + {0x030C, 0x08, 0x00, + CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0308, 0x00, 0x00, + CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, {0xA88, 0x05, 0x00, @@ -454,7 +510,11 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = { { .lane_identifier = CPHY_LANE_2, .csiphy_data_rate_regs = { - {0x344, 0xB2, 0x00, + {0x050C, 0x08, 0x00, + CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0508, 0x00, 0x00, + CSIPHY_SETTLE_CNT_HIGHER_BYTE}, + {0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, {0xB88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h index 9cd115be22..841b91c5ff 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h @@ -14,7 +14,7 @@ struct csiphy_reg_parms_t csiphy_v2_1_0 = { .mipi_csiphy_glbl_irq_cmd_addr = 0x1028, .csiphy_common_array_size = 6, .csiphy_reset_array_size = 5, - .csiphy_2ph_config_array_size = 19, + .csiphy_2ph_config_array_size = 23, .csiphy_3ph_config_array_size = 29, .csiphy_2ph_clock_lane = 0x1, .csiphy_2ph_combo_ck_ln = 0x10, @@ -72,6 +72,10 @@ struct csiphy_reg_t csiphy_2ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x005C, 0x00, 0x00, CSIPHY_SKEW_CAL}, + {0x0060, 0xF1, 0x00, CSIPHY_SKEW_CAL}, + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + {0x1000, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -93,6 +97,10 @@ struct csiphy_reg_t csiphy_2ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0E08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E5C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0E60, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0E64, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x1000, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -114,6 +122,10 @@ struct csiphy_reg_t csiphy_2ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x045C, 0x00, 0x00, CSIPHY_SKEW_CAL}, + {0x0460, 0xF1, 0x00, CSIPHY_SKEW_CAL}, + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + {0x1000, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -135,6 +147,10 @@ struct csiphy_reg_t csiphy_2ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0808, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x085C, 0x00, 0x00, CSIPHY_SKEW_CAL}, + {0x0860, 0xF1, 0x00, CSIPHY_SKEW_CAL}, + {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + {0x1000, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -156,6 +172,10 @@ struct csiphy_reg_t csiphy_2ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C5C, 0x00, 0x00, CSIPHY_SKEW_CAL}, + {0x0C60, 0xF1, 0x00, CSIPHY_SKEW_CAL}, + {0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + {0x1000, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, }, }; @@ -182,6 +202,10 @@ struct csiphy_reg_t {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x005C, 0x00, 0x00, CSIPHY_SKEW_CAL}, + {0x0060, 0xF1, 0x00, CSIPHY_SKEW_CAL}, + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + {0x1000, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -204,6 +228,10 @@ struct csiphy_reg_t {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0E08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0E5C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0E60, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0E64, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x1000, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -226,6 +254,10 @@ struct csiphy_reg_t {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x045C, 0x00, 0x00, CSIPHY_SKEW_CAL}, + {0x0460, 0xF1, 0x00, CSIPHY_SKEW_CAL}, + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + {0x1000, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -248,6 +280,10 @@ struct csiphy_reg_t {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0808, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x085C, 0x00, 0x00, CSIPHY_SKEW_CAL}, + {0x0860, 0xF1, 0x00, CSIPHY_SKEW_CAL}, + {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL}, + {0x1000, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -270,6 +306,10 @@ struct csiphy_reg_t {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C5C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0C60, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0C64, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x1000, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }, };