disp: msm: sde: update autorefresh disable seq-2
Update autorefresh disable sequence-2 by avoiding tearcheck enable configuration. Updated sequence will trigger the frame by resetting the write line count with tearcheck start position. Change-Id: I984251c0cb23475f20cd5ea62122a167324d6670 Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
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@@ -1783,8 +1783,11 @@ static void _sde_encoder_autorefresh_disable_seq2(
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u32 autorefresh_status = 0;
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struct sde_encoder_phys_cmd *cmd_enc =
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to_sde_encoder_phys_cmd(phys_enc);
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struct intf_tear_status tear_status;
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struct sde_hw_intf *hw_intf = phys_enc->hw_intf;
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if (!hw_mdp->ops.get_autorefresh_status) {
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if (!hw_mdp->ops.get_autorefresh_status ||
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!hw_intf->ops.check_and_reset_tearcheck) {
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SDE_DEBUG_CMDENC(cmd_enc,
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"autofresh disable seq2 not supported\n");
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return;
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@@ -1793,10 +1796,11 @@ static void _sde_encoder_autorefresh_disable_seq2(
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/*
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* If autorefresh is still enabled after sequence-1, proceed with
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* below sequence-2.
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* 1. Disable TEAR CHECK
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* 2. Disable autorefresh config
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* 4. Poll for autorefresh to be disabled
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* 5. Enable TEAR CHECK
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* 1. Disable autorefresh config
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* 2. Run in loop:
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* 2.1 Poll for autorefresh to be disabled
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* 2.2 Log read and write count status
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* 2.3 Replace te write count with start_pos to meet trigger window
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*/
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autorefresh_status = hw_mdp->ops.get_autorefresh_status(hw_mdp,
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phys_enc->intf_idx);
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@@ -1813,52 +1817,36 @@ static void _sde_encoder_autorefresh_disable_seq2(
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autorefresh_status, SDE_EVTLOG_FUNC_CASE2);
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}
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if (autorefresh_status & BIT(7)) {
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SDE_ERROR_CMDENC(cmd_enc, "autofresh status:0x%x intf:%d\n",
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autorefresh_status, phys_enc->intf_idx - INTF_0);
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if (phys_enc->has_intf_te &&
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phys_enc->hw_intf->ops.enable_tearcheck)
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phys_enc->hw_intf->ops.enable_tearcheck(
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phys_enc->hw_intf, false);
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else if (phys_enc->hw_pp->ops.enable_tearcheck)
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phys_enc->hw_pp->ops.enable_tearcheck(
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phys_enc->hw_pp, false);
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_sde_encoder_phys_cmd_config_autorefresh(phys_enc, 0);
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do {
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usleep_range(AUTOREFRESH_SEQ2_POLL_TIME,
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AUTOREFRESH_SEQ2_POLL_TIME + 1);
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if ((trial * AUTOREFRESH_SEQ2_POLL_TIME)
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> AUTOREFRESH_SEQ2_POLL_TIMEOUT) {
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SDE_ERROR_CMDENC(cmd_enc,
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"disable autorefresh failed\n");
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SDE_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus",
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"panic");
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break;
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}
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trial++;
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autorefresh_status =
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hw_mdp->ops.get_autorefresh_status(hw_mdp,
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phys_enc->intf_idx);
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while (autorefresh_status & BIT(7)) {
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if (!trial) {
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SDE_ERROR_CMDENC(cmd_enc,
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"autofresh status:0x%x intf:%d\n",
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autorefresh_status,
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phys_enc->intf_idx - INTF_0);
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SDE_EVT32(DRMID(phys_enc->parent),
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phys_enc->intf_idx - INTF_0,
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autorefresh_status);
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} while (autorefresh_status & BIT(7));
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"autofresh status:0x%x intf:%d\n", autorefresh_status,
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phys_enc->intf_idx - INTF_0);
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if (phys_enc->has_intf_te &&
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phys_enc->hw_intf->ops.enable_tearcheck)
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phys_enc->hw_intf->ops.enable_tearcheck(
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phys_enc->hw_intf, true);
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else if (phys_enc->hw_pp->ops.enable_tearcheck)
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phys_enc->hw_pp->ops.enable_tearcheck(
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phys_enc->hw_pp, true);
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_sde_encoder_phys_cmd_config_autorefresh(phys_enc, 0);
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}
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usleep_range(AUTOREFRESH_SEQ2_POLL_TIME,
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AUTOREFRESH_SEQ2_POLL_TIME + 1);
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if ((trial * AUTOREFRESH_SEQ2_POLL_TIME)
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> AUTOREFRESH_SEQ2_POLL_TIMEOUT) {
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SDE_ERROR_CMDENC(cmd_enc,
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"disable autorefresh failed\n");
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SDE_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic");
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break;
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}
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trial++;
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autorefresh_status = hw_mdp->ops.get_autorefresh_status(hw_mdp,
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phys_enc->intf_idx);
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hw_intf->ops.check_and_reset_tearcheck(hw_intf, &tear_status);
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SDE_ERROR_CMDENC(cmd_enc,
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"autofresh status:0x%x intf:%d tear_read:0x%x tear_write:0x%x\n",
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autorefresh_status, phys_enc->intf_idx - INTF_0,
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tear_status.read_count, tear_status.write_count);
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SDE_EVT32(DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0,
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autorefresh_status, tear_status.read_count,
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tear_status.write_count);
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}
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}
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@@ -672,6 +672,27 @@ static int sde_hw_intf_get_vsync_info(struct sde_hw_intf *intf,
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return 0;
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}
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static int sde_hw_intf_v1_check_and_reset_tearcheck(struct sde_hw_intf *intf,
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struct intf_tear_status *status)
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{
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struct sde_hw_blk_reg_map *c = &intf->hw;
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u32 start_pos;
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if (!intf || !status)
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return -EINVAL;
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c = &intf->hw;
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status->read_count = SDE_REG_READ(c, INTF_TEAR_INT_COUNT_VAL);
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start_pos = SDE_REG_READ(c, INTF_TEAR_START_POS);
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status->write_count = SDE_REG_READ(c, INTF_TEAR_SYNC_WRCOUNT);
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status->write_count &= 0xffff0000;
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status->write_count |= start_pos;
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SDE_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT, status->write_count);
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return 0;
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}
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static void sde_hw_intf_vsync_sel(struct sde_hw_intf *intf,
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u32 vsync_source)
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{
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@@ -739,6 +760,8 @@ static void _setup_intf_ops(struct sde_hw_intf_ops *ops,
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ops->poll_timeout_wr_ptr = sde_hw_intf_poll_timeout_wr_ptr;
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ops->vsync_sel = sde_hw_intf_vsync_sel;
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ops->get_status = sde_hw_intf_v1_get_status;
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ops->check_and_reset_tearcheck =
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sde_hw_intf_v1_check_and_reset_tearcheck;
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}
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}
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@@ -52,6 +52,11 @@ struct intf_status {
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u32 line_count; /* current line count including blanking */
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};
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struct intf_tear_status {
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u32 read_count; /* frame & line count for tear init value */
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u32 write_count; /* frame & line count for tear write */
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};
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struct intf_avr_params {
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u32 default_fps;
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u32 min_fps;
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@@ -188,6 +193,12 @@ struct sde_hw_intf_ops {
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*/
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void (*enable_compressed_input)(struct sde_hw_intf *intf,
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bool compression_en, bool dsc_4hs_merge);
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/**
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* Check the intf tear check status and reset it to start_pos
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*/
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int (*check_and_reset_tearcheck)(struct sde_hw_intf *intf,
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struct intf_tear_status *status);
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};
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struct sde_hw_intf {
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