msm: camera: cdm: Add support for CDM 2.2

Added support for new cdm status register for SM8650.

CRs-Fixed: 3147223
Change-Id: I35392cfb35613a777664e1fae2c24b0150c5b8ef
Signed-off-by: Li Sha Lim <[email protected]>

drivers/cam_cdm/cam_cdm.h

@@ -26,6 +26,7 @@
 #define CAM_SW_CDM_INDEX                  0
 #define CAM_CDM_INFLIGHT_WORKS            5
 #define CAM_CDM_HW_RESET_TIMEOUT          300
+#define CAM_CDM_PAUSE_CORE_US_TIMEOUT     10000
 
 /*
  * Macros to get prepare and get information
@@ -313,6 +314,9 @@ struct cam_cdm_common_reg_data {
  *                       wait, etc.
  * @core_en:             offset to pause/enable CDM
  * @fe_cfg:              offset to configure CDM fetch engine
+ * @cdm_status:          offset to read CDM status register, this register
+ *                       indicates if CDM is idle, and if a pause operation
+ *                       is successfully completed or not
  * @irq_context_status   offset to read back irq context status
  * @bl_fifo_rb:          offset to set BL_FIFO read back
  * @bl_fifo_base_rb:     offset to read back base address on offset set by
@@ -358,6 +362,7 @@ struct cam_cdm_common_regs {
 	uint32_t core_cfg;
 	uint32_t core_en;
 	uint32_t fe_cfg;
+	uint32_t cdm_status;
 	uint32_t irq_context_status;
 	uint32_t bl_fifo_rb;
 	uint32_t bl_fifo_base_rb;
@@ -458,6 +463,7 @@ enum cam_cdm_hw_version {
 	CAM_CDM_VERSION_1_2 = 0x10020000,
 	CAM_CDM_VERSION_2_0 = 0x20000000,
 	CAM_CDM_VERSION_2_1 = 0x20010000,
+	CAM_CDM_VERSION_2_2 = 0x20020000,
 	CAM_CDM_VERSION_MAX,
 };
 

drivers/cam_cdm/cam_cdm_core_common.c

@@ -83,6 +83,7 @@ bool cam_cdm_set_cam_hw_version(
 	case CAM_CDM120_VERSION:
 	case CAM_CDM200_VERSION:
 	case CAM_CDM210_VERSION:
+	case CAM_CDM220_VERSION:
 		cam_version->major    = (ver & 0xF0000000);
 		cam_version->minor    = (ver & 0xFFF0000);
 		cam_version->incr     = (ver & 0xFFFF);
@@ -116,6 +117,7 @@ struct cam_cdm_utils_ops *cam_cdm_get_ops(
 		case CAM_CDM120_VERSION:
 		case CAM_CDM200_VERSION:
 		case CAM_CDM210_VERSION:
+		case CAM_CDM220_VERSION:
 			return &CDM170_ops;
 		default:
 			CAM_ERR(CAM_CDM, "CDM Version=%x not supported in util",

drivers/cam_cdm/cam_cdm_core_common.h

@@ -14,6 +14,7 @@
 #define CAM_CDM120_VERSION 0x10020000
 #define CAM_CDM200_VERSION 0x20000000
 #define CAM_CDM210_VERSION 0x20010000
+#define CAM_CDM220_VERSION 0x20020000
 
 #define CAM_CDM_AHB_BURST_LEN_1  (BIT(1) - 1)
 #define CAM_CDM_AHB_BURST_LEN_4  (BIT(2) - 1)
@@ -23,6 +24,7 @@
 #define CAM_CDM_AHB_STOP_ON_ERROR BIT(8)
 #define CAM_CDM_ARB_SEL_RR        BIT(16)
 #define CAM_CDM_IMPLICIT_WAIT_EN  BIT(17)
+#define CAM_CDM_PAUSE_CORE_ENABLE_MASK  (0x1 << 1)
 
 extern struct cam_cdm_utils_ops CDM170_ops;
 

drivers/cam_cdm/cam_cdm_hw_core.c

@@ -24,6 +24,7 @@
 #include "cam_cdm_hw_reg_1_2.h"
 #include "cam_cdm_hw_reg_2_0.h"
 #include "cam_cdm_hw_reg_2_1.h"
+#include "cam_cdm_hw_reg_2_2.h"
 #include "camera_main.h"
 #include "cam_trace.h"
 #include "cam_req_mgr_workq.h"
@@ -81,6 +82,10 @@ static const struct of_device_id msm_cam_hw_cdm_dt_match[] = {
 		.compatible = CAM_HW_CDM_OPE_NAME_2_1,
 		.data = &cam_cdm_2_1_reg_offset,
 	},
+	{
+		.compatible  = CAM_HW_CDM_RT_NAME_2_2,
+		.data = &cam_cdm_2_2_reg_offset,
+	},
 	{},
 };
 
@@ -116,7 +121,9 @@ static enum cam_cdm_id cam_hw_cdm_get_id_by_name(char *name)
 	if (strnstr(name, CAM_HW_CDM_OPE_NAME_2_1,
 			strlen(CAM_HW_CDM_OPE_NAME_2_1)))
 		return CAM_CDM_OPE;
-
+	if (strnstr(name, CAM_HW_CDM_RT_NAME_2_2,
+			strlen(CAM_HW_CDM_RT_NAME_2_2)))
+		return CAM_CDM_RT;
 	return CAM_CDM_MAX;
 }
 
@@ -164,11 +171,26 @@ static int cam_hw_cdm_pause_core(struct cam_hw_info *cdm_hw, bool pause)
 {
 	int rc = 0;
 	struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info;
-	uint32_t val = 0x1;
+	uint32_t val = 0x1, core_en_reg, cdm_status_reg;
 
 	if (pause)
 		val |= 0x2;
 
+	if (core->offsets->cmn_reg->cdm_status) {
+		cam_cdm_read_hw_reg(cdm_hw,
+			core->offsets->cmn_reg->core_en, &core_en_reg);
+		cam_cdm_read_hw_reg(cdm_hw,
+			core->offsets->cmn_reg->cdm_status, &cdm_status_reg);
+
+		/* In both pause or resume, further action need not/cannot be taken */
+		if ((core_en_reg & CAM_CDM_PAUSE_CORE_ENABLE_MASK) &&
+			!(cdm_status_reg & CAM_CDM_PAUSE_CORE_DONE_MASK)) {
+			if (!pause)
+				CAM_ERR(CAM_CDM, "Pause core not done yet, can't resume core");
+			return -EAGAIN;
+		}
+	}
+
 	if (cam_cdm_write_hw_reg(cdm_hw,
 			core->offsets->cmn_reg->core_en, val)) {
 		CAM_ERR(CAM_CDM, "Failed to Write core_en for %s%u",
@@ -176,6 +198,23 @@ static int cam_hw_cdm_pause_core(struct cam_hw_info *cdm_hw, bool pause)
 			cdm_hw->soc_info.index);
 		rc = -EIO;
 	}
+	if (pause && core->offsets->cmn_reg->cdm_status) {
+		uint32_t us_wait_time = 0;
+
+		while (us_wait_time < CAM_CDM_PAUSE_CORE_US_TIMEOUT) {
+			cam_cdm_read_hw_reg(cdm_hw,
+				core->offsets->cmn_reg->cdm_status,
+				&cdm_status_reg);
+			if (cdm_status_reg & CAM_CDM_PAUSE_CORE_DONE_MASK) {
+				CAM_DBG(CAM_CDM, "Pause core time (us): %lu",
+					us_wait_time);
+				break;
+			}
+			us_wait_time += 100;
+			usleep_range(100, 110);
+		}
+		CAM_WARN(CAM_CDM, "Pause core operation not successful");
+	}
 
 	return rc;
 }
@@ -324,10 +363,8 @@ void cam_hw_cdm_dump_core_debug_registers(struct cam_hw_info *cdm_hw,
 		cdm_hw->soc_info.label_name, cdm_hw->soc_info.index);
 
 
-	if (pause_core) {
+	if (pause_core)
 		cam_hw_cdm_pause_core(cdm_hw, true);
-		usleep_range(1000, 1010);
-	}
 
 	cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->cdm_hw_version,
 		&cdm_version);
@@ -464,10 +501,8 @@ void cam_hw_cdm_dump_core_debug_registers(struct cam_hw_info *cdm_hw,
 		cam_cdm_read_hw_reg(cdm_hw,
 			core->offsets->cmn_reg->core_en, &dump_reg[0]);
 		is_core_paused_already = (bool)(dump_reg[0] & 0x20);
-		if (!is_core_paused_already) {
+		if (!is_core_paused_already)
 			cam_hw_cdm_pause_core(cdm_hw, true);
-			usleep_range(1000, 1010);
-		}
 
 		cam_hw_cdm_dump_bl_fifo_data(cdm_hw);
 
@@ -1630,9 +1665,7 @@ int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle)
 
 	reinit_completion(&cdm_core->reset_complete);
 
-	/* First pause CDM, If it fails still proceed to reset CDM HW */
 	cam_hw_cdm_pause_core(cdm_hw, true);
-	usleep_range(1000, 1010);
 
 	for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) {
 		if (!cdm_core->bl_fifo[i].bl_depth)
@@ -1726,7 +1759,6 @@ int cam_hw_cdm_handle_error_info(
 		goto end;
 	}
 
-	/* First pause CDM, If it fails still proceed to dump debug info */
 	cam_hw_cdm_pause_core(cdm_hw, true);
 
 	rc = cam_cdm_read_hw_reg(cdm_hw,
@@ -2126,9 +2158,7 @@ int cam_hw_cdm_deinit(void *hw_priv,
 	set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status);
 	reinit_completion(&cdm_core->reset_complete);
 
-	/* First pause CDM, If it fails still proceed to reset CDM HW */
 	cam_hw_cdm_pause_core(cdm_hw, true);
-	usleep_range(1000, 1010);
 
 	for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) {
 		if (!cdm_core->bl_fifo[i].bl_depth)

drivers/cam_cdm/cam_cdm_hw_reg_1_0.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include "cam_cdm.h"
@@ -87,6 +88,8 @@ static struct cam_cdm_common_regs cdm_hw_1_0_cmn_reg_offset = {
 	.core_cfg = 0x18,
 	.core_en = 0x1c,
 	.fe_cfg = 0x20,
+	.cdm_status = 0x0,
+	.irq_context_status = 0x0,
 	.bl_fifo_rb = 0x60,
 	.bl_fifo_base_rb = 0x64,
 	.bl_fifo_len_rb = 0x68,

drivers/cam_cdm/cam_cdm_hw_reg_1_1.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include "cam_cdm.h"
@@ -87,6 +88,8 @@ static struct cam_cdm_common_regs cdm_hw_1_1_cmn_reg_offset = {
 	.core_cfg = 0x18,
 	.core_en = 0x1c,
 	.fe_cfg = 0x20,
+	.cdm_status = 0x0,
+	.irq_context_status = 0x0,
 	.bl_fifo_rb = 0x60,
 	.bl_fifo_base_rb = 0x64,
 	.bl_fifo_len_rb = 0x68,

drivers/cam_cdm/cam_cdm_hw_reg_1_2.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include "cam_cdm.h"
@@ -107,6 +108,8 @@ static struct cam_cdm_common_regs cdm_hw_1_2_cmn_reg_offset = {
 	.core_cfg = 0x18,
 	.core_en = 0x1c,
 	.fe_cfg = 0x20,
+	.cdm_status = 0x0,
+	.irq_context_status = 0x0,
 	.bl_fifo_rb = 0x60,
 	.bl_fifo_base_rb = 0x64,
 	.bl_fifo_len_rb = 0x68,

drivers/cam_cdm/cam_cdm_hw_reg_2_0.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include "cam_cdm.h"
@@ -178,6 +179,8 @@ static struct cam_cdm_common_regs cdm_hw_2_0_cmn_reg_offset = {
 	.core_cfg = 0x18,
 	.core_en = 0x1c,
 	.fe_cfg = 0x20,
+	.cdm_status = 0x0,
+	.irq_context_status = 0x0,
 	.bl_fifo_rb = 0x60,
 	.bl_fifo_base_rb = 0x64,
 	.bl_fifo_len_rb = 0x68,

drivers/cam_cdm/cam_cdm_hw_reg_2_1.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include "cam_cdm.h"
@@ -178,6 +179,7 @@ static struct cam_cdm_common_regs cdm_hw_2_1_cmn_reg_offset = {
 	.core_cfg = 0x18,
 	.core_en = 0x1c,
 	.fe_cfg = 0x20,
+	.cdm_status = 0x0,
 	.irq_context_status = 0x2c,
 	.bl_fifo_rb = 0x60,
 	.bl_fifo_base_rb = 0x64,

drivers/cam_cdm/cam_cdm_hw_reg_2_2.h

@@ -0,0 +1,257 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "cam_cdm.h"
+
+#define CAM_CDM_PAUSE_CORE_DONE_MASK    (0x1 << 1)
+
+struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_2_bl_pending_req0 = {
+	.rb_offset = 0x6c,
+	.rb_mask = 0x1ff,
+	.rb_num_fifo = 0x2,
+	.rb_next_fifo_shift = 0x10,
+};
+
+struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_2_bl_pending_req1 = {
+	.rb_offset = 0x70,
+	.rb_mask = 0x1ff,
+	.rb_num_fifo = 0x2,
+	.rb_next_fifo_shift = 0x10,
+};
+
+static struct cam_cdm_irq_regs cdm_hw_2_2_irq0 = {
+	.irq_mask = 0x30,
+	.irq_clear = 0x34,
+	.irq_clear_cmd = 0x38,
+	.irq_set = 0x3c,
+	.irq_set_cmd = 0x40,
+	.irq_status = 0x44,
+};
+
+static struct cam_cdm_irq_regs cdm_hw_2_2_irq1 = {
+	.irq_mask = 0x130,
+	.irq_clear = 0x134,
+	.irq_clear_cmd = 0x138,
+	.irq_set = 0x13c,
+	.irq_set_cmd = 0x140,
+	.irq_status = 0x144,
+};
+
+static struct cam_cdm_irq_regs cdm_hw_2_2_irq2 = {
+	.irq_mask = 0x230,
+	.irq_clear = 0x234,
+	.irq_clear_cmd = 0x238,
+	.irq_set = 0x23c,
+	.irq_set_cmd = 0x240,
+	.irq_status = 0x244,
+};
+
+static struct cam_cdm_irq_regs cdm_hw_2_2_irq3 = {
+	.irq_mask = 0x330,
+	.irq_clear = 0x334,
+	.irq_clear_cmd = 0x338,
+	.irq_set = 0x33c,
+	.irq_set_cmd = 0x340,
+	.irq_status = 0x344,
+};
+
+static struct cam_cdm_bl_fifo_regs cdm_hw_2_2_bl_fifo0 = {
+	.bl_fifo_base = 0x50,
+	.bl_fifo_len = 0x54,
+	.bl_fifo_store = 0x58,
+	.bl_fifo_cfg = 0x5c,
+};
+
+static struct cam_cdm_bl_fifo_regs cdm_hw_2_2_bl_fifo1 = {
+	.bl_fifo_base = 0x150,
+	.bl_fifo_len = 0x154,
+	.bl_fifo_store = 0x158,
+	.bl_fifo_cfg = 0x15c,
+};
+
+static struct cam_cdm_bl_fifo_regs cdm_hw_2_2_bl_fifo2 = {
+	.bl_fifo_base = 0x250,
+	.bl_fifo_len = 0x254,
+	.bl_fifo_store = 0x258,
+	.bl_fifo_cfg = 0x25c,
+};
+
+static struct cam_cdm_bl_fifo_regs cdm_hw_2_2_bl_fifo3 = {
+	.bl_fifo_base = 0x350,
+	.bl_fifo_len = 0x354,
+	.bl_fifo_store = 0x358,
+	.bl_fifo_cfg = 0x35c,
+};
+
+static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg0 = {
+	.scratch_reg = 0x90,
+};
+
+static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg1 = {
+	.scratch_reg = 0x94,
+};
+
+static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg2 = {
+	.scratch_reg = 0x98,
+};
+
+static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg3 = {
+	.scratch_reg = 0x9c,
+};
+
+static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg4 = {
+	.scratch_reg = 0xa0,
+};
+
+static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg5 = {
+	.scratch_reg = 0xa4,
+};
+
+static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg6 = {
+	.scratch_reg = 0xa8,
+};
+
+static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg7 = {
+	.scratch_reg = 0xac,
+};
+
+static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg8 = {
+	.scratch_reg = 0xb0,
+};
+
+static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg9 = {
+	.scratch_reg = 0xb4,
+};
+
+static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg10  = {
+	.scratch_reg = 0xb8,
+};
+
+static struct cam_cdm_scratch_reg cdm_2_2_scratch_reg11  = {
+	.scratch_reg = 0xbc,
+};
+
+static struct cam_cdm_perf_mon_regs cdm_2_2_perf_mon0 = {
+	.perf_mon_ctrl = 0x110,
+	.perf_mon_0 = 0x114,
+	.perf_mon_1 = 0x118,
+	.perf_mon_2 = 0x11c,
+};
+
+static struct cam_cdm_perf_mon_regs cdm_2_2_perf_mon1 = {
+	.perf_mon_ctrl = 0x120,
+	.perf_mon_0 = 0x124,
+	.perf_mon_1 = 0x128,
+	.perf_mon_2 = 0x12c,
+};
+
+static struct cam_cdm_comp_wait_status cdm_2_2_comp_wait_status0 = {
+	.comp_wait_status = 0x88,
+};
+
+static struct cam_cdm_comp_wait_status cdm_2_2_comp_wait_status1 = {
+	.comp_wait_status = 0x8c,
+};
+
+static struct cam_cdm_icl_data_regs cdm_2_2_icl_data = {
+	.icl_last_data_0 = 0x1c0,
+	.icl_last_data_1 = 0x1c4,
+	.icl_last_data_2 = 0x1c8,
+	.icl_inv_data = 0x1cc,
+};
+
+static struct cam_cdm_icl_misc_regs cdm_2_2_icl_misc = {
+	.icl_inv_bl_addr = 0x1d0,
+	.icl_status = 0x1d8,
+};
+
+static struct cam_cdm_icl_regs cdm_2_2_icl = {
+	.data_regs = &cdm_2_2_icl_data,
+	.misc_regs = &cdm_2_2_icl_misc,
+};
+
+static struct cam_cdm_common_regs cdm_hw_2_2_cmn_reg_offset = {
+	.cdm_hw_version = 0x0,
+	.cam_version = NULL,
+	.rst_cmd = 0x10,
+	.cgc_cfg = 0x14,
+	.core_cfg = 0x18,
+	.core_en = 0x1c,
+	.fe_cfg = 0x20,
+	.cdm_status = 0x28,
+	.irq_context_status = 0x2c,
+	.bl_fifo_rb = 0x60,
+	.bl_fifo_base_rb = 0x64,
+	.bl_fifo_len_rb = 0x68,
+	.usr_data = 0x80,
+	.wait_status = 0x84,
+	.last_ahb_addr = 0xd0,
+	.last_ahb_data = 0xd4,
+	.core_debug = 0xd8,
+	.last_ahb_err_addr = 0xe0,
+	.last_ahb_err_data = 0xe4,
+	.current_bl_base = 0xe8,
+	.current_bl_len = 0xec,
+	.current_used_ahb_base = 0xf0,
+	.debug_status = 0xf4,
+	.bus_misr_cfg0 = 0x100,
+	.bus_misr_cfg1 = 0x104,
+	.bus_misr_rd_val = 0x108,
+	.pending_req = {
+			&cdm_hw_2_2_bl_pending_req0,
+			&cdm_hw_2_2_bl_pending_req1,
+		},
+	.comp_wait = {
+			&cdm_2_2_comp_wait_status0,
+			&cdm_2_2_comp_wait_status1,
+		},
+	.perf_mon = {
+			&cdm_2_2_perf_mon0,
+			&cdm_2_2_perf_mon1,
+		},
+	.scratch = {
+			&cdm_2_2_scratch_reg0,
+			&cdm_2_2_scratch_reg1,
+			&cdm_2_2_scratch_reg2,
+			&cdm_2_2_scratch_reg3,
+			&cdm_2_2_scratch_reg4,
+			&cdm_2_2_scratch_reg5,
+			&cdm_2_2_scratch_reg6,
+			&cdm_2_2_scratch_reg7,
+			&cdm_2_2_scratch_reg8,
+			&cdm_2_2_scratch_reg9,
+			&cdm_2_2_scratch_reg10,
+			&cdm_2_2_scratch_reg11,
+		},
+	.perf_reg = NULL,
+	.icl_reg = &cdm_2_2_icl,
+	.spare = 0x3fc,
+	.priority_group_bit_offset = 20,
+};
+
+static struct cam_cdm_common_reg_data cdm_hw_2_2_cmn_reg_data = {
+	.num_bl_fifo = 0x4,
+	.num_bl_fifo_irq = 0x4,
+	.num_bl_pending_req_reg = 0x2,
+	.num_scratch_reg = 0xc,
+};
+
+struct cam_cdm_hw_reg_offset cam_cdm_2_2_reg_offset = {
+	.cmn_reg = &cdm_hw_2_2_cmn_reg_offset,
+	.bl_fifo_reg = {
+			&cdm_hw_2_2_bl_fifo0,
+			&cdm_hw_2_2_bl_fifo1,
+			&cdm_hw_2_2_bl_fifo2,
+			&cdm_hw_2_2_bl_fifo3,
+		},
+	.irq_reg = {
+			&cdm_hw_2_2_irq0,
+			&cdm_hw_2_2_irq1,
+			&cdm_hw_2_2_irq2,
+			&cdm_hw_2_2_irq3,
+		},
+	.reg_data = &cdm_hw_2_2_cmn_reg_data,
+};

drivers/cam_cdm/cam_cdm_soc.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_CDM_SOC_H_
@@ -16,6 +17,7 @@
 #define CAM_HW_CDM_CPAS_NAME_2_1 "qcom,cam-cpas-cdm2_1"
 #define CAM_HW_CDM_RT_NAME_2_1   "qcom,cam-rt-cdm2_1"
 #define CAM_HW_CDM_OPE_NAME_2_1  "qcom,cam-ope-cdm2_1"
+#define CAM_HW_CDM_RT_NAME_2_2   "qcom,cam-rt-cdm2_2"
 
 int cam_hw_cdm_soc_get_dt_properties(struct cam_hw_info *cdm_hw,
 	const struct of_device_id *table);