Merge "msm: camera: csiphy: Add Support for datarate specific settings" into camera-kernel.lnx.5.0

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

@@ -691,9 +691,9 @@ static int cam_csiphy_cphy_data_rate_config(
 	int i = 0;
 	int lane_idx = -1;
 	int data_rate_idx = -1;
-	uint64_t phy_data_rate = 0;
+	uint64_t required_phy_data_rate = 0;
 	void __iomem *csiphybase = NULL;
-	ssize_t num_table_entries = 0;
+	ssize_t num_data_rates = 0;
 	struct data_rate_settings_t *settings_table = NULL;
 	struct csiphy_cphy_per_lane_info *per_lane = NULL;
 	uint32_t lane_enable = 0;
@@ -716,12 +716,12 @@ static int cam_csiphy_cphy_data_rate_config(
 		return 0;
 	}
 
-	phy_data_rate = csiphy_device->csiphy_info[idx].data_rate;
+	required_phy_data_rate = csiphy_device->csiphy_info[idx].data_rate;
 	csiphybase =
 		csiphy_device->soc_info.reg_map[0].mem_base;
 	settings_table =
 		csiphy_device->ctrl_reg->data_rates_settings_table;
-	num_table_entries =
+	num_data_rates =
 		settings_table->num_data_rate_settings;
 	lane_cnt = csiphy_device->csiphy_info[idx].lane_cnt;
 
@@ -730,23 +730,25 @@ static int cam_csiphy_cphy_data_rate_config(
 	settle_cnt = intermediate_var;
 	skew_cal_enable = csiphy_device->csiphy_info[idx].mipi_flags;
 
-	CAM_DBG(CAM_CSIPHY, "required data rate : %llu", phy_data_rate);
-	for (data_rate_idx = 0; data_rate_idx < num_table_entries;
+	CAM_DBG(CAM_CSIPHY, "required data rate : %llu", required_phy_data_rate);
+	for (data_rate_idx = 0; data_rate_idx < num_data_rates;
 			data_rate_idx++) {
 		struct data_rate_reg_info_t *drate_settings =
 			settings_table->data_rate_settings;
-		uint64_t bandwidth = drate_settings[data_rate_idx].bandwidth;
+		uint64_t supported_phy_bw = drate_settings[data_rate_idx].bandwidth;
 		ssize_t  num_reg_entries =
 			drate_settings[data_rate_idx].data_rate_reg_array_size;
-		if (phy_data_rate > bandwidth) {
+
+		if ((required_phy_data_rate > supported_phy_bw) &&
+			(data_rate_idx < (num_data_rates - 1))) {
 			CAM_DBG(CAM_CSIPHY,
 				"Skipping table [%d] with BW: %llu, Required data_rate: %llu",
-				data_rate_idx, bandwidth, phy_data_rate);
+				data_rate_idx, supported_phy_bw, required_phy_data_rate);
 			continue;
 		}
 
 		CAM_DBG(CAM_CSIPHY, "table[%d] BW : %llu Selected",
-			data_rate_idx, bandwidth);
+			data_rate_idx, supported_phy_bw);
 		lane_enable = csiphy_device->csiphy_info[idx].lane_enable;
 		lane_assign = csiphy_device->csiphy_info[idx].lane_assign;
 		lane_idx = -1;

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c

@@ -476,7 +476,8 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
 		csiphy_dev->hw_version = CSIPHY_VERSION_V210;
 		csiphy_dev->is_divisor_32_comp = true;
 		csiphy_dev->clk_lane = 0;
-		csiphy_dev->ctrl_reg->data_rates_settings_table = NULL;
+		csiphy_dev->ctrl_reg->data_rates_settings_table =
+			&data_rate_delta_table_2_1_0;
 		csiphy_dev->ctrl_reg->csiphy_bist_reg = &bist_setting_2_1_0;
 	} else {
 		CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x",

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h

@@ -30,7 +30,7 @@ struct csiphy_reg_parms_t csiphy_v2_1_0 = {
 	.csiphy_common_array_size = 4,
 	.csiphy_reset_array_size = 3,
 	.csiphy_2ph_config_array_size = 24,
-	.csiphy_3ph_config_array_size = 45,
+	.csiphy_3ph_config_array_size = 43,
 	.csiphy_2ph_clock_lane = 0x1,
 	.csiphy_2ph_combo_ck_ln = 0x10,
 	.csiphy_interrupt_status_size = 11,
@@ -39,7 +39,7 @@ struct csiphy_reg_parms_t csiphy_v2_1_0 = {
 };
 
 struct csiphy_reg_t csiphy_common_reg_2_1_0[] = {
-	{0x1014, 0x00, 0x00, CSIPHY_LANE_ENABLE},
+	{0x1014, 0x00, 0xBB8, CSIPHY_LANE_ENABLE},
 	{0x1084, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x1018, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
 	{0x101C, 0x7A, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -334,11 +334,10 @@ struct csiphy_reg_t
 
 struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 	{
-		{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0278, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0288, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x028C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x026C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0288, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x028C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x026C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0268, 0xF1, 0x64, CSIPHY_DEFAULT_PARAMS},
 		{0x0294, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x02F4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -352,7 +351,6 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x020C, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 		{0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
 		{0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x02E4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x02E8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x02EC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -381,11 +379,10 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x1000, 0x0E, 0x00, CSIPHY_DNP_PARAMS},
 	},
 	{
-		{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0678, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0688, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x068C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x066C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0688, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x068C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x066C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0668, 0xF1, 0x64, CSIPHY_DEFAULT_PARAMS},
 		{0x0694, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x06F4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -399,7 +396,6 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x060C, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 		{0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
 		{0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x06E4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x06E8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x06EC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -428,11 +424,10 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x1000, 0x0E, 0x00, CSIPHY_DNP_PARAMS},
 	},
 	{
-		{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0A78, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0A88, 0xAA, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0A8C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0A6C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A88, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A8C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A6C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A68, 0xF1, 0x64, CSIPHY_DEFAULT_PARAMS},
 		{0x0A94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0AF4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -446,7 +441,6 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x0A0C, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
 		{0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
 		{0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0AE4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0AE8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0AEC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -528,4 +522,94 @@ struct bist_reg_settings_t bist_setting_2_1_0 = {
 	.bist_status_err_check_arr = bist_status_err_check_arr_2_1_0,
 };
 
+struct data_rate_settings_t data_rate_delta_table_2_1_0 = {
+	.num_data_rate_settings = 3,
+	.data_rate_settings = {
+		{
+			/* ((1 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
+			.bandwidth = 2280000000,
+			.data_rate_reg_array_size = 2,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0278, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0678, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A78, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((2 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
+			.bandwidth = 4560000000,
+			.data_rate_reg_array_size = 2,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0278, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0678, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A78, 0x30, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+		{
+			/* ((3.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
+			.bandwidth = 7980000000,
+			.data_rate_reg_array_size = 2,
+			.per_lane_info = {
+				{
+					.lane_identifier = CPHY_LANE_0,
+					.csiphy_data_rate_regs = {
+						{0x0278, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0214, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_1,
+					.csiphy_data_rate_regs = {
+						{0x0678, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0614, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+				{
+					.lane_identifier = CPHY_LANE_2,
+					.csiphy_data_rate_regs = {
+						{0x0A78, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
+						{0x0A14, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
+					},
+				},
+			},
+		},
+	},
+};
+
 #endif /* _CAM_CSIPHY_2_1_0_HWREG_H_ */