disp: msm: sde: Split demura config into two blobs

Some of the demura config parameters are single buffered. When demura config is reprogrammed by user-space clients, single buffered updates can cause artifacts on screen. Change splits the double buffered and single buffered configs into different payloads to allow user-space to update double buffered config. Change-Id: I493b86944f7c2d630dcc1b863174e816cf8c82ed Signed-off-by: Gopikrishnaiah Anand <quic_agopik@quicinc.com>
2022-12-06 12:10:59 -08:00
--- a/include/uapi/display/drm/msm_drm_pp.h
+++ b/include/uapi/display/drm/msm_drm_pp.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
 /*
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
 */

@@ -642,6 +642,7 @@ struct drm_msm_spr_udc_cfg {
 #define DEMURA_FLAG_0 (1 << 0)
 #define DEMURA_FLAG_1 (1 << 1)
 #define DEMURA_FLAG_2 (3 << 2)
+#define DEMURA_SKIP_CFG0_PARAM2 (1 << 4)
 #define DEMURA_PRECISION_0 (0 << 2)
 #define DEMURA_PRECISION_1 (1 << 2)
 #define DEMURA_PRECISION_2 (2 << 2)
@@ -692,6 +693,14 @@ struct drm_msm_dem_cfg {
 	__u32 c1_depth;
 	__u32 c2_depth;
 	__u32 src_id;
+	__u32 cfg0_param2_idx;
+};
+
+struct drm_msm_dem_cfg0_param2 {
+	__u32 cfg0_param2_len;
+	__u64 cfg0_param2_c0[CFG0_PARAM2_LEN];
+	__u64 cfg0_param2_c1[CFG0_PARAM2_LEN];
+	__u64 cfg0_param2_c2[CFG0_PARAM2_LEN];
 };

 /**
--- a/msm/sde/sde_color_processing.c
+++ b/msm/sde/sde_color_processing.c
@@ -1025,6 +1025,22 @@ static int _set_demura_feature(struct sde_hw_dspp *hw_dspp,
 	return ret;
 }

+static int _set_demura_cfg0_param2(struct sde_hw_dspp *hw_dspp,
+				   struct sde_hw_cp_cfg *hw_cfg,
+				   struct sde_crtc *sde_crtc)
+{
+	int ret = 0;
+
+	if (!hw_dspp) {
+		ret = -EINVAL;
+	} else {
+		if (hw_dspp->ops.setup_demura_cfg0_param2)
+			hw_dspp->ops.setup_demura_cfg0_param2(hw_dspp, hw_cfg);
+	}
+
+	return ret;
+}
+
 static int _feature_unsupported(struct sde_hw_dspp *hw_dspp,
 				   struct sde_hw_cp_cfg *hw_cfg,
 				   struct sde_crtc *sde_crtc)
@@ -1098,6 +1114,7 @@ do { \
 	wrappers[SDE_CP_CRTC_DSPP_SPR_INIT] = _set_spr_init_feature; \
 	wrappers[SDE_CP_CRTC_DSPP_SPR_UDC] = _set_spr_udc_feature; \
 	wrappers[SDE_CP_CRTC_DSPP_DEMURA_INIT] = _set_demura_feature; \
+	wrappers[SDE_CP_CRTC_DSPP_DEMURA_CFG0_PARAM2] = _set_demura_cfg0_param2; \
 } while (0)

 feature_wrapper set_crtc_pu_feature_wrappers[SDE_CP_CRTC_MAX_PU_FEATURES];
@@ -1921,6 +1938,7 @@ static const int dspp_feature_to_sub_blk_tbl[SDE_CP_CRTC_MAX_FEATURES] = {
 	[SDE_CP_CRTC_DSPP_DEMURA_INIT] = SDE_DSPP_DEMURA,
 	[SDE_CP_CRTC_DSPP_DEMURA_BACKLIGHT] = SDE_DSPP_DEMURA,
 	[SDE_CP_CRTC_DSPP_MAX] = SDE_DSPP_MAX,
+	[SDE_CP_CRTC_DSPP_DEMURA_CFG0_PARAM2] = SDE_DSPP_DEMURA,
 	[SDE_CP_CRTC_LM_GC] = SDE_DSPP_MAX,
 };

@@ -3537,6 +3555,9 @@ static  void _dspp_demura_install_property(struct drm_crtc *crtc)
 				SDE_CP_CRTC_DSPP_DEMURA_BOOT_PLANE, true,
 				sde_demura_fetch_planes,
 				ARRAY_SIZE(sde_demura_fetch_planes), 0xf);
+		_sde_cp_crtc_install_blob_property(crtc, "SDE_DEMURA_CFG0_PARAM2",
+			SDE_CP_CRTC_DSPP_DEMURA_CFG0_PARAM2,
+			sizeof(struct drm_msm_dem_cfg0_param2));
 		break;
 	default:
 		DRM_ERROR("version %d not supported\n", version);
--- a/msm/sde/sde_color_processing.h
+++ b/msm/sde/sde_color_processing.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
 */

@@ -108,6 +108,7 @@ enum sde_cp_crtc_features {
 	SDE_CP_CRTC_DSPP_DEMURA_INIT,
 	SDE_CP_CRTC_DSPP_DEMURA_BACKLIGHT,
 	SDE_CP_CRTC_DSPP_DEMURA_BOOT_PLANE,
+	SDE_CP_CRTC_DSPP_DEMURA_CFG0_PARAM2,
 	SDE_CP_CRTC_DSPP_MAX,
 	/* DSPP features end */

--- a/msm/sde/sde_hw_catalog.h
+++ b/msm/sde/sde_hw_catalog.h
@@ -455,6 +455,7 @@ enum {
 * @SDE_DSPP_DEMURA          Demura block
 * @SDE_DSPP_RC              RC block
 * @SDE_DSPP_SB              SB LUT DMA
+ * @SDE_DSPP_DEMURA_CFG0_PARAM2 Demura block
 * @SDE_DSPP_MAX             maximum value
 */
 enum {
@@ -474,6 +475,7 @@ enum {
 	SDE_DSPP_DEMURA,
 	SDE_DSPP_RC,
 	SDE_DSPP_SB,
+	SDE_DSPP_DEMURA_CFG0_PARAM2,
 	SDE_DSPP_MAX
 };

--- a/msm/sde/sde_hw_dspp.c
+++ b/msm/sde/sde_hw_dspp.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
 */

@@ -373,11 +373,15 @@ static void dspp_spr(struct sde_hw_dspp *c)
 static void dspp_demura(struct sde_hw_dspp *c)
 {
 	int ret;
+	c->ops.setup_demura_cfg = NULL;
+	c->ops.setup_demura_backlight_cfg = NULL;
+	c->ops.setup_demura_cfg0_param2 = NULL;

 	if (c->cap->sblk->demura.version == SDE_COLOR_PROCESS_VER(0x1, 0x0)) {
 		ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_DEMURA, c->idx);
-		c->ops.setup_demura_cfg = NULL;
-		c->ops.setup_demura_backlight_cfg = NULL;
+		if (!ret)
+			ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_DEMURA_CFG0_PARAM2, c->idx);
+
 		if (!ret) {
 			c->ops.setup_demura_cfg = reg_dmav1_setup_demurav1;
 			c->ops.setup_demura_backlight_cfg =
@@ -385,11 +389,12 @@ static void dspp_demura(struct sde_hw_dspp *c)
 			c->ops.demura_read_plane_status =
 					sde_demura_read_plane_status;
 			c->ops.setup_demura_pu_config = sde_demura_pu_cfg;
+			c->ops.setup_demura_cfg0_param2 = reg_dmav1_setup_demura_cfg0_param2;
 		}
 	} else if (c->cap->sblk->demura.version == SDE_COLOR_PROCESS_VER(0x2, 0x0)) {
 		ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_DEMURA, c->idx);
-		c->ops.setup_demura_cfg = NULL;
-		c->ops.setup_demura_backlight_cfg = NULL;
+		if (!ret)
+			ret = reg_dmav1_init_dspp_op_v4(SDE_DSPP_DEMURA_CFG0_PARAM2, c->idx);
 		if (!ret) {
 			c->ops.setup_demura_cfg = reg_dmav1_setup_demurav2;
 			c->ops.setup_demura_backlight_cfg =
@@ -397,6 +402,7 @@ static void dspp_demura(struct sde_hw_dspp *c)
 			c->ops.demura_read_plane_status =
 					sde_demura_read_plane_status;
 			c->ops.setup_demura_pu_config = sde_demura_pu_cfg;
+			c->ops.setup_demura_cfg0_param2 = reg_dmav1_setup_demura_cfg0_param2;
 		} else {
 			SDE_ERROR("Regdma init dspp op failed for DemuraV2");
 		}
--- a/msm/sde/sde_hw_dspp.h
+++ b/msm/sde/sde_hw_dspp.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
 */

@@ -326,6 +326,12 @@ struct sde_hw_dspp_ops {
 	 * @cfg: Pointer to configuration
 	 */
 	void (*setup_demura_pu_config)(struct sde_hw_dspp *ctx, void *cfg);
+	/**
+	 * setup_demura_cfg0_param2 - function to configure demura cfg0_param2 params
+	 * @ctx: Pointer to dspp context
+	 * @cfg: Pointer to configuration
+	 */
+	void (*setup_demura_cfg0_param2)(struct sde_hw_dspp *ctx, void *cfg);
 };

 /**
--- a/msm/sde/sde_hw_reg_dma_v1.c
+++ b/msm/sde/sde_hw_reg_dma_v1.c
@@ -937,6 +937,7 @@ int init_v12(struct sde_hw_reg_dma *cfg)
 	v1_supported[SPR_PU_CFG] = (GRP_DSPP_HW_BLK_SELECT |
 			GRP_MDSS_HW_BLK_SELECT);
 	v1_supported[DEMURA_CFG] = MDSS | DSPP0 | DSPP1;
+	v1_supported[DEMURA_CFG0_PARAM2] = MDSS | DSPP0 | DSPP1;

 	return 0;
 }
@@ -1083,6 +1084,7 @@ int init_v3(struct sde_hw_reg_dma *cfg)
 	}

 	v1_supported[DEMURA_CFG] = v1_supported[DEMURA_CFG] | DSPP2 | DSPP3;
+	v1_supported[DEMURA_CFG0_PARAM2] = v1_supported[DEMURA_CFG0_PARAM2] | DSPP2 | DSPP3;
 	return 0;
 }

--- a/msm/sde/sde_hw_reg_dma_v1_color_proc.c
+++ b/msm/sde/sde_hw_reg_dma_v1_color_proc.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
 */

@@ -87,6 +87,8 @@
 		REG_DMA_HEADERS_BUFFER_SZ)
 #define DEMURA_MEM_SIZE ((sizeof(struct drm_msm_dem_cfg)) + \
 		REG_DMA_HEADERS_BUFFER_SZ)
+#define DEMURA_CFG0_PARAM2_MEM_SIZE ((sizeof(struct drm_msm_dem_cfg0_param2)) + \
+		REG_DMA_HEADERS_BUFFER_SZ)

 #define APPLY_MASK_AND_SHIFT(x, n, shift) ((x & (REG_MASK(n))) << (shift))
 #define REG_DMA_VIG_GAMUT_OP_MASK 0x300
@@ -158,6 +160,7 @@ static u32 feature_map[SDE_DSPP_MAX] = {
 	[SDE_DSPP_AD] = REG_DMA_FEATURES_MAX,
 	[SDE_DSPP_RC] = RC_DATA,
 	[SDE_DSPP_DEMURA] = DEMURA_CFG,
+	[SDE_DSPP_DEMURA_CFG0_PARAM2] = DEMURA_CFG0_PARAM2,
 };

 static u32 sspp_feature_map[SDE_SSPP_MAX] = {
@@ -187,6 +190,7 @@ static u32 feature_reg_dma_sz[SDE_DSPP_MAX] = {
 	[SDE_DSPP_RC] = RC_MEM_SIZE,
 	[SDE_DSPP_SPR] = SPR_INIT_MEM_SIZE,
 	[SDE_DSPP_DEMURA] = DEMURA_MEM_SIZE,
+	[SDE_DSPP_DEMURA_CFG0_PARAM2] = DEMURA_CFG0_PARAM2_MEM_SIZE,
 };

 static u32 sspp_feature_reg_dma_sz[SDE_SSPP_MAX] = {
@@ -5670,41 +5674,15 @@ static void reg_dma_demura_off(struct sde_hw_dspp *ctx,
 		DRM_ERROR("failed to kick off ret %d\n", rc);
 }

-static int __reg_dmav1_setup_demurav1_cfg0_c_params(
-		struct sde_reg_dma_setup_ops_cfg *dma_write_cfg,
-		struct drm_msm_dem_cfg *dcfg,
-		struct sde_hw_reg_dma_ops *dma_ops,
-		u32 *temp, u32 temp_sz, u32 comp_index,
-		u32 demura_base)
+static int __reg_dmav1_setup_demurav1_cfg0_c_params_cmn(
+						struct sde_reg_dma_setup_ops_cfg *dma_write_cfg,
+						struct sde_hw_reg_dma_ops *dma_ops,
+						u64 *p, u32 len, u32 *temp, u32 comp_index,
+						u32 demura_base)
 {
-	u32 i, len;
-	u64 *p;
+	u32 i;
 	int rc;

-	if (temp_sz < ARRAY_SIZE(dcfg->cfg0_param2_c0) * 8 || comp_index > 2) {
-		DRM_ERROR("exp sz %zd act sz %d comp index %d\n",
-			ARRAY_SIZE(dcfg->cfg0_param2_c0) * 8,
-			temp_sz, comp_index);
-		return -EINVAL;
-	}
-
-	memset(temp, 0x0, ARRAY_SIZE(dcfg->cfg0_param2_c0) * 8);
-	if (comp_index == 0) {
-		len = 1 << dcfg->c0_depth;
-		p = dcfg->cfg0_param2_c0;
-	} else if (comp_index == 1) {
-		len = 1 << dcfg->c1_depth;
-		p = dcfg->cfg0_param2_c1;
-	} else {
-		len = 1 << dcfg->c2_depth;
-		p = dcfg->cfg0_param2_c2;
-	}
-
-	if (!len || len > 256) {
-		DRM_ERROR("invalid len %d Max 256\n", len);
-		return -EINVAL;
-	}
-
 	i = ((comp_index & 0x3) << 28) | BIT(31);
 	REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x68,
 		&i, sizeof(i), REG_SINGLE_WRITE, 0, 0, 0);
@@ -5732,13 +5710,72 @@ static int __reg_dmav1_setup_demurav1_cfg0_c_params(
 	return rc;
 }

+static int __reg_dmav1_setup_demurav1_cfg0_c_params(
+		struct sde_reg_dma_setup_ops_cfg *dma_write_cfg,
+		struct drm_msm_dem_cfg *dcfg,
+		struct sde_hw_reg_dma_ops *dma_ops,
+		u32 *temp, u32 temp_sz, u32 comp_index,
+		u32 demura_base)
+{
+	u32 len;
+	u64 *p;
+	int rc;
+
+	if (temp_sz < ARRAY_SIZE(dcfg->cfg0_param2_c0) * 8 || comp_index > 2) {
+		DRM_ERROR("exp sz %zd act sz %d comp index %d\n",
+			ARRAY_SIZE(dcfg->cfg0_param2_c0) * 8,
+			temp_sz, comp_index);
+		return -EINVAL;
+	}
+
+	memset(temp, 0x0, ARRAY_SIZE(dcfg->cfg0_param2_c0) * 8);
+	if (comp_index == 0) {
+		len = 1 << dcfg->c0_depth;
+		p = dcfg->cfg0_param2_c0;
+	} else if (comp_index == 1) {
+		len = 1 << dcfg->c1_depth;
+		p = dcfg->cfg0_param2_c1;
+	} else {
+		len = 1 << dcfg->c2_depth;
+		p = dcfg->cfg0_param2_c2;
+	}
+
+	if (!len || len > 256) {
+		DRM_ERROR("invalid len %d Max 256\n", len);
+		return -EINVAL;
+	}
+
+	rc = __reg_dmav1_setup_demurav1_cfg0_c_params_cmn(dma_write_cfg, dma_ops, p, len,
+					temp, comp_index, demura_base);
+	return rc;
+}
+
+static u32 __get_offset_idx(u32 idx, u32 depth)
+{
+	u32 offset;
+
+	if (depth > 8 || idx > 3 || (depth == 8 && idx > 0) || (depth == 7 && idx > 1)) {
+		DRM_ERROR("invalid depth %d index %d\n", depth, idx);
+		return 0;
+	}
+
+	offset = (1 << depth) * idx;
+	if ((offset + (1 << depth)) > 256) {
+		DRM_ERROR("invalid offset %d end %d > 256\n", offset, (offset + (1 << depth)));
+		return 0;
+	}
+
+	offset = (offset << 16) | (offset << 8) | offset;
+	return offset;
+}
+
 static int __reg_dmav1_setup_demurav1_cfg0(struct sde_hw_dspp *ctx,
 		struct drm_msm_dem_cfg *dcfg,
 		struct sde_reg_dma_setup_ops_cfg *dma_write_cfg,
 		struct sde_hw_reg_dma_ops *dma_ops,
 		struct sde_hw_cp_cfg *hw_cfg)
 {
-	u32 *temp = NULL, i, *p = NULL, shift, width;
+	u32 *temp = NULL, i, *p = NULL, shift, width, codebook_offset;
 	int rc;
 	u32 demura_base = ctx->cap->sblk->demura.base + ctx->hw.blk_off;

@@ -5831,7 +5868,7 @@ static int __reg_dmav1_setup_demurav1_cfg0(struct sde_hw_dspp *ctx,
 		goto quit;
 	}

-	for (i = 0; i < 3; i++) {
+	for (i = 0; i < 3 && !(dcfg->flags & DEMURA_SKIP_CFG0_PARAM2); i++) {
 		rc = __reg_dmav1_setup_demurav1_cfg0_c_params(dma_write_cfg,
 				dcfg, dma_ops, temp,
 				sizeof(struct drm_msm_dem_cfg), i,
@@ -5840,6 +5877,20 @@ static int __reg_dmav1_setup_demurav1_cfg0(struct sde_hw_dspp *ctx,
 			goto quit;
 	}

+	if (!(dcfg->flags & DEMURA_SKIP_CFG0_PARAM2))
+		dcfg->cfg0_param2_idx = 0;
+
+	codebook_offset = __get_offset_idx(dcfg->cfg0_param2_idx, dcfg->c0_depth);
+
+	REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x70,
+		&codebook_offset, sizeof(codebook_offset), REG_SINGLE_WRITE, 0, 0, 0);
+	rc = dma_ops->setup_payload(dma_write_cfg);
+	if (rc) {
+		DRM_ERROR("0x70: REG_SINGLE_WRITE err %d len %zd buf idx %d\n",
+			rc, sizeof(codebook_offset), dma_write_cfg->dma_buf->index);
+		goto quit;
+	}
+
 	width = hw_cfg->panel_width >> ((dcfg->flags & DEMURA_FLAG_1) ? 2 : 1);
 	DRM_DEBUG_DRIVER("0x80: value %x\n", width);
 	REG_DMA_SETUP_OPS(*dma_write_cfg, demura_base + 0x80,
@@ -6439,3 +6490,68 @@ void reg_dmav1_setup_demurav2(struct sde_hw_dspp *ctx, void *cfx)
 	if (rc)
 		DRM_ERROR("failed to kick off demurav2 ret %d\n", rc);
 }
+
+void reg_dmav1_setup_demura_cfg0_param2(struct sde_hw_dspp *ctx, void *cfg)
+{
+	struct drm_msm_dem_cfg0_param2 *dcfg;
+	struct sde_hw_cp_cfg *hw_cfg = cfg;
+	int rc = 0;
+	struct sde_hw_reg_dma_ops *dma_ops;
+	struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
+	struct sde_reg_dma_kickoff_cfg kick_off;
+	u32 *temp, i, len;
+	u64 *p;
+	u32 demura_base = ctx->cap->sblk->demura.base + ctx->hw.blk_off;
+
+	rc = reg_dma_dspp_check(ctx, cfg, DEMURA_CFG0_PARAM2);
+	if (rc)
+		return;
+
+	if (!hw_cfg->payload) {
+		LOG_FEATURE_OFF;
+		return;
+	}
+
+	if (hw_cfg->len != sizeof(struct drm_msm_dem_cfg0_param2)) {
+		DRM_ERROR("invalid sz of payload len %d exp %zd\n",
+				hw_cfg->len, sizeof(struct drm_msm_dem_cfg0_param2));
+	}
+	dcfg = hw_cfg->payload;
+	dma_ops = sde_reg_dma_get_ops();
+	dma_ops->reset_reg_dma_buf(dspp_buf[DEMURA_CFG0_PARAM2][ctx->idx]);
+
+	REG_DMA_INIT_OPS(dma_write_cfg, MDSS, DEMURA_CFG0_PARAM2,
+			dspp_buf[DEMURA_CFG0_PARAM2][ctx->idx]);
+
+	REG_DMA_SETUP_OPS(dma_write_cfg, 0, NULL, 0, HW_BLK_SELECT, 0, 0, 0);
+	rc = dma_ops->setup_payload(&dma_write_cfg);
+	if (rc) {
+		DRM_ERROR("write decode select failed ret %d\n", rc);
+		return;
+	}
+	temp = kvzalloc(sizeof(struct drm_msm_dem_cfg0_param2), GFP_KERNEL);
+	if (!temp)
+		return;
+	len = dcfg->cfg0_param2_len;
+	for (i = 0; i < 3; i++) {
+		if (!i)
+			p = dcfg->cfg0_param2_c0;
+		else if (i == 1)
+			p = dcfg->cfg0_param2_c1;
+		else if (i == 2)
+			p = dcfg->cfg0_param2_c2;
+		__reg_dmav1_setup_demurav1_cfg0_c_params_cmn(&dma_write_cfg, dma_ops,
+						p, len, temp, i, demura_base);
+	}
+	REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,
+			dspp_buf[DEMURA_CFG0_PARAM2][ctx->idx],
+			REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE,
+			DEMURA_CFG0_PARAM2);
+
+	rc = dma_ops->kick_off(&kick_off);
+	if (rc)
+		DRM_ERROR("failed to kick off ret %d\n", rc);
+
+	LOG_FEATURE_ON;
+	kvfree(temp);
+}
--- a/msm/sde/sde_hw_reg_dma_v1_color_proc.h
+++ b/msm/sde/sde_hw_reg_dma_v1_color_proc.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
 */

@@ -367,5 +367,11 @@ void reg_dmav1_setup_demurav1(struct sde_hw_dspp *ctx, void *cfg);
 */
 void reg_dmav1_setup_demurav2(struct sde_hw_dspp *ctx, void *cfg);

+/**
+ * reg_dmav1_setup_demura_cfg0_param2() - function to set up the demura cfg0 param2 configuration.
+ * @ctx: dspp ctx info
+ * @cfg: pointer to struct sde_hw_cp_cfg
+ */
+void reg_dmav1_setup_demura_cfg0_param2(struct sde_hw_dspp *ctx, void *cfg);

 #endif /* _SDE_HW_REG_DMA_V1_COLOR_PROC_H */
--- a/msm/sde/sde_reg_dma.h
+++ b/msm/sde/sde_reg_dma.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
 */

@@ -85,6 +85,7 @@ enum sde_reg_dma_features {
 	LTM_VLUT,
 	RC_DATA,
 	DEMURA_CFG,
+	DEMURA_CFG0_PARAM2,
 	REG_DMA_FEATURES_MAX,
 };