qcacmn: Register ppe2tcl and reo2ppe ring interrupts

Enable and register PPE2TCL and REO2PPE ring interrupts
for direct switch
Set interrupt timer threshold for ppe2tcl ring as 30 us.

Change-Id: Ida1ff6c3c2000f16f07960f7eae0d10edc337dc0
CRs-Fixed: 3341790

dp/wifi3.0/be/dp_be.c

@@ -946,6 +946,9 @@ void dp_free_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
 		if (ring_type == WBM2SW_RELEASE &&
 		    ring_num == WBM2_SW_PPE_REL_RING_ID)
 			pld_pfrm_free_irq(soc->osdev->dev, srng->irq, soc);
+		else if (ring_type == REO2PPE || ring_type == PPE2TCL)
+			pld_pfrm_free_irq(soc->osdev->dev, srng->irq,
+					  dp_get_ppe_ds_ctxt(soc));
 	}
 }
 
@@ -953,14 +956,15 @@ static
 int dp_register_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
 				 int vector, int ring_type, int ring_num)
 {
-	int irq, ret = 0;
+	int irq = -1, ret = 0;
 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
 	int pci_slot = pld_get_pci_slot(soc->osdev->dev);
-	void *ctxt;
+
+	srng->irq = -1;
+	irq = pld_get_msi_irq(soc->osdev->dev, vector);
 
 	if (ring_type == WBM2SW_RELEASE &&
 	    ring_num == WBM2_SW_PPE_REL_RING_ID) {
-		irq = pld_get_msi_irq(soc->osdev->dev, vector);
 		snprintf(be_soc->irq_name[2], DP_PPE_INTR_STRNG_LEN,
 			 "pci%d_ppe_wbm_rel", pci_slot);
 
@@ -971,6 +975,29 @@ int dp_register_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
 
 		if (ret)
 			goto fail;
+	} else if (ring_type == REO2PPE && be_soc->ppeds_int_mode_enabled) {
+		snprintf(be_soc->irq_name[0], DP_PPE_INTR_STRNG_LEN,
+			 "pci%d_reo2ppe", pci_slot);
+		ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
+					   dp_ppe_ds_reo2ppe_irq_handler,
+					   IRQF_SHARED | IRQF_NO_SUSPEND,
+					   be_soc->irq_name[0],
+					   dp_get_ppe_ds_ctxt(soc));
+
+		if (ret)
+			goto fail;
+	} else if (ring_type == PPE2TCL && be_soc->ppeds_int_mode_enabled) {
+		snprintf(be_soc->irq_name[1], DP_PPE_INTR_STRNG_LEN,
+			 "pci%d_ppe2tcl", pci_slot);
+		ret = pld_pfrm_request_irq(soc->osdev->dev, irq,
+					   dp_ppe_ds_ppe2tcl_irq_handler,
+					   IRQF_SHARED | IRQF_NO_SUSPEND,
+					   be_soc->irq_name[1],
+					   dp_get_ppe_ds_ctxt(soc));
+		if (ret)
+			goto fail;
+
+		pld_pfrm_disable_irq_nosync(soc->osdev->dev, irq);
 	} else {
 		return 0;
 	}
@@ -982,8 +1009,8 @@ int dp_register_ppeds_interrupts(struct dp_soc *soc, struct dp_srng *srng,
 
 	return 0;
 fail:
-	dp_err("Unable to config irq : ring type %d irq %d vector %d ctxt %pK",
-	       ring_type, irq, vector, ctxt);
+	dp_err("Unable to config irq : ring type %d irq %d vector %d",
+	       ring_type, irq, vector);
 
 	return ret;
 }

dp/wifi3.0/be/dp_be.h

@@ -283,6 +283,7 @@ struct dp_ppeds_napi {
  * @mld_peer_hash: peer hash table for ML peers
  *           Associated peer with this MAC address)
  * @mld_peer_hash_lock: lock to protect mld_peer_hash
+ * @ppe_ds_int_mode_enabled: PPE DS interrupt mode enabled
  * @reo2ppe_ring: REO2PPE ring
  * @ppe2tcl_ring: PPE2TCL ring
  * @ppe_release_ring: PPE release ring
@@ -308,6 +309,7 @@ struct dp_soc_be {
 	struct dp_hw_cookie_conversion_t tx_cc_ctx[MAX_TXDESC_POOLS];
 	struct dp_hw_cookie_conversion_t rx_cc_ctx[MAX_RXDESC_POOLS];
 #ifdef WLAN_SUPPORT_PPEDS
+	bool ppeds_int_mode_enabled;
 	struct dp_srng reo2ppe_ring;
 	struct dp_srng ppe2tcl_ring;
 	struct dp_srng ppe_release_ring;

dp/wifi3.0/dp_main.c

@@ -1556,6 +1556,14 @@ static int dp_srng_calculate_msi_group(struct dp_soc *soc,
 		grp_mask = &soc->wlan_cfg_ctx->int_host2txmon_ring_mask[0];
 	break;
 
+	case REO2PPE:
+		grp_mask = &soc->wlan_cfg_ctx->int_reo2ppe_ring_mask[0];
+	break;
+
+	case PPE2TCL:
+		grp_mask = &soc->wlan_cfg_ctx->int_ppe2tcl_ring_mask[0];
+	break;
+
 	case TCL_DATA:
 	/* CMD_CREDIT_RING is used as command in 8074 and credit in 9000 */
 	case TCL_CMD_CREDIT:
@@ -1922,7 +1930,7 @@ dp_srng_configure_interrupt_thresholds(struct dp_soc *soc,
 
 	wbm2_sw_rx_rel_ring_id = wlan_cfg_get_rx_rel_ring_id(soc->wlan_cfg_ctx);
 
-	if (ring_type == REO_DST) {
+	if (ring_type == REO_DST || ring_type == REO2PPE) {
 		ring_params->intr_timer_thres_us =
 			wlan_cfg_get_int_timer_threshold_rx(soc->wlan_cfg_ctx);
 		ring_params->intr_batch_cntr_thres_entries =
@@ -1963,11 +1971,16 @@ dp_srng_configure_interrupt_thresholds(struct dp_soc *soc,
 	case TCL_STATUS:
 	case WBM_IDLE_LINK:
 	case SW2WBM_RELEASE:
-	case PPE2TCL:
 	case SW2RXDMA_NEW:
 		ring_params->intr_timer_thres_us = 0;
 		ring_params->intr_batch_cntr_thres_entries = 0;
 		break;
+	case PPE2TCL:
+		ring_params->intr_timer_thres_us =
+			wlan_cfg_get_int_timer_threshold_other(soc->wlan_cfg_ctx);
+		ring_params->intr_batch_cntr_thres_entries =
+			wlan_cfg_get_int_batch_threshold_ppe2tcl(soc->wlan_cfg_ctx);
+		break;
 	}
 
 	/* Enable low threshold interrupts for rx buffer rings (regular and

dp/wifi3.0/dp_stats.c

@@ -5618,6 +5618,11 @@ void dp_print_soc_cfg_params(struct dp_soc *soc)
 		       soc_cfg_ctx->int_batch_threshold_other);
 	DP_PRINT_STATS("Int timer threshold other: %u ",
 		       soc_cfg_ctx->int_timer_threshold_other);
+	DP_PRINT_STATS("Int batch threshold ppe2tcl: %u ",
+		       soc_cfg_ctx->int_batch_threshold_ppe2tcl);
+	DP_PRINT_STATS("Int timer threshold ppe2tcl: %u ",
+		       soc_cfg_ctx->int_timer_threshold_ppe2tcl);
+
 	DP_PRINT_STATS("DP NAPI scale factor: %u ",
 		       soc_cfg_ctx->napi_scale_factor);