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@@ -12,9 +12,263 @@
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#include "cam_ife_csid_common.h"
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#include "cam_ife_csid_common.h"
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#include "cam_ife_csid_hw_ver2.h"
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#include "cam_ife_csid_hw_ver2.h"
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#include "cam_irq_controller.h"
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#include "cam_irq_controller.h"
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+#include "cam_isp_hw_mgr_intf.h"
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#define CAM_CSID_VERSION_V780 0x70080000
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#define CAM_CSID_VERSION_V780 0x70080000
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+static const struct cam_ife_csid_irq_desc cam_ife_csid_780_rx_irq_desc[] = {
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+ {
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+ .bitmask = BIT(0),
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+ .desc = "DL0_EOT",
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+ },
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+ {
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+ .bitmask = BIT(1),
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+ .desc = "DL1_EOT",
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+ },
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+ {
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+ .bitmask = BIT(2),
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+ .desc = "DL2_EOT",
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+ },
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+ {
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+ .bitmask = BIT(3),
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+ .desc = "DL3_EOT",
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+ },
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+ {
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+ .bitmask = BIT(4),
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+ .desc = "DL0_SOT",
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+ },
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+ {
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+ .bitmask = BIT(5),
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+ .desc = "DL1_SOT",
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+ },
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+ {
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+ .bitmask = BIT(6),
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+ .desc = "DL2_SOT",
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+ },
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+ {
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+ .bitmask = BIT(7),
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+ .desc = "DL3_SOT",
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+ },
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+ {
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+ .bitmask = BIT(8),
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+ .desc = "LONG_PKT",
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+ },
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+ {
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+ .bitmask = BIT(9),
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+ .desc = "SHORT_PKT",
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+ },
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+ {
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+ .bitmask = BIT(10),
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+ .desc = "CPHY_PKT_HDR",
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+ },
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+ {
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+ .bitmask = BIT(11),
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+ .desc = "ERROR_CPHY_EOT_RECEPTION",
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+ },
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+ {
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+ .bitmask = BIT(12),
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+ .desc = "ERROR_CPHY_SOT_RECEPTION",
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+ },
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+ {
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+ .bitmask = BIT(13),
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+ .desc = "ERROR_CPHY_PH_CRC",
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+ },
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+ {
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+ .bitmask = BIT(14),
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+ .desc = "WARNING_ECC",
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+ },
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+ {
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+ .bitmask = BIT(15),
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+ .desc = "ERROR_LANE0_FIFO_OVERFLOW",
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+ },
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+ {
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+ .bitmask = BIT(16),
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+ .desc = "ERROR_LANE1_FIFO_OVERFLOW",
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+ },
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+ {
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+ .bitmask = BIT(17),
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+ .desc = "ERROR_LANE2_FIFO_OVERFLOW",
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+ },
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+ {
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+ .bitmask = BIT(18),
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+ .desc = "ERROR_LANE3_FIFO_OVERFLOW",
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+ },
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+ {
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+ .bitmask = BIT(19),
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+ .desc = "ERROR_CRC",
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+ },
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+ {
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+ .bitmask = BIT(20),
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+ .desc = "ERROR_ECC",
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+ },
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+ {
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+ .bitmask = BIT(21),
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+ .desc = "ERROR_MMAPPED_VC_DT",
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+ },
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+ {
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+ .bitmask = BIT(22),
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+ .desc = "ERROR_UNMAPPED_VC_DT",
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+ },
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+ {
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+ .bitmask = BIT(23),
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+ .desc = "ERROR_STREAM_UNDERFLOW",
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+ },
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+ {
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+ .bitmask = BIT(24),
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+ .desc = "ERROR_UNBOUNDED_FRAME",
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+ },
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+};
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+
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+static const struct cam_ife_csid_irq_desc cam_ife_csid_780_path_irq_desc[] = {
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+ {
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+ .bitmask = BIT(0),
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+ .desc = "ILLEGAL_PROGRAMMING",
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+ },
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+ {
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+ .bitmask = BIT(1),
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+ .desc = "EROOR_MSG_FIFO_OVERFLOW",
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+ },
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+ {
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+ .bitmask = BIT(2),
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+ .desc = "ERROR_FIFO_OVERFLOW",
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+ },
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+ {
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+ .bitmask = BIT(3),
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+ .desc = "CAMIF_EOF",
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+ },
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+ {
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+ .bitmask = BIT(4),
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+ .desc = "CAMIF_SOF",
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+ },
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+ {
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+ .bitmask = BIT(5),
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+ .desc = "FRAME_DROP_EOF",
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+ },
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+ {
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+ .bitmask = BIT(6),
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+ .desc = "FRAME_DROP_EOL",
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+ },
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+ {
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+ .bitmask = BIT(7),
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+ .desc = "FRAME_DROP_SOL",
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+ },
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+ {
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+ .bitmask = BIT(8),
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+ .desc = "FRAME_DROP_SOF",
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+ },
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+ {
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+ .bitmask = BIT(9),
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+ .desc = "INFO_INPUT_EOF",
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+ },
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+ {
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+ .bitmask = BIT(10),
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+ .desc = "INFO_INPUT_EOL",
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+ },
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+ {
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+ .bitmask = BIT(11),
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+ .desc = "INFO_INPUT_SOL",
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+ },
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+ {
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+ .bitmask = BIT(12),
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+ .desc = "INFO_INPUT_SOF",
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+ },
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+ {
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+ .bitmask = BIT(13),
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+ .desc = "ERROR_PIX_COUNT",
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+ },
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+ {
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+ .bitmask = BIT(14),
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+ .desc = "ERROR_LINE_COUNT",
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+ },
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+ {
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+ .bitmask = BIT(15),
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+ .desc = "VCDT_GRP0_SEL",
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+ },
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+ {
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+ .bitmask = BIT(16),
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+ .desc = "VCDT_GRP1_SEL",
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+ },
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+ {
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+ .bitmask = BIT(17),
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+ .desc = "VCDT_GRP_CHANGE",
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+ },
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+ {
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+ .bitmask = BIT(18),
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+ .desc = "FRAME_DROP",
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+ },
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+ {
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+ .bitmask = BIT(19),
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+ .desc = "OVERFLOW_RECOVERY: Back pressure/output fifo ovrfl",
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+ },
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+ {
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+ .bitmask = BIT(20),
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+ .desc = "ERROR_REC_CCIF_VIOLATION From Camif",
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+ },
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+ {
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+ .bitmask = BIT(21),
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+ .desc = "CAMIF_EPOCH0",
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+ },
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+ {
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+ .bitmask = BIT(22),
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+ .desc = "CAMIF_EPOCH1",
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+ },
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+ {
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+ .bitmask = BIT(23),
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+ .desc = "RUP_DONE",
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+ },
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+ {
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+ .bitmask = BIT(24),
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+ .desc = "ILLEGAL_BATCH_ID",
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+ },
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+ {
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+ .bitmask = BIT(25),
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+ .desc = "BATCH_END_MISSING_VIOLATION",
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+ },
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+ {
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+ .bitmask = BIT(26),
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+ .desc = "HEIGHT_VIOLATION",
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+ },
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+ {
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+ .bitmask = BIT(27),
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+ .desc = "WIDTH_VIOLATION",
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+ },
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+ {
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+ .bitmask = BIT(28),
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+ .desc = "SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP",
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+ },
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+ {
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+ .bitmask = BIT(29),
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+ .desc = "CCIF_VIOLATION: Bad frame timings",
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+ },
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+};
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+
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+static const struct cam_ife_csid_top_irq_desc cam_ife_csid_780_top_irq_desc[] = {
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+ {
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+ .bitmask = BIT(1),
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+ .err_type = CAM_ISP_HW_ERROR_CSID_FATAL,
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+ .err_name = "FATAL_SENSOR_SWITCHING_IRQ",
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+ .desc = "Fatal Error duirng dynamically switching between 2 sensors",
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+ },
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+ {
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+ .bitmask = BIT(18),
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+ .err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
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+ .err_name = "ERROR_NO_VOTE_DN",
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+ .desc = "vote_up is asserted before IDLE is encountered in a frame",
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+ },
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+ {
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+ .bitmask = BIT(19),
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+ .err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
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+ .err_name = "ERROR_VOTE_UP_LATE",
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+ .desc = "vote_up is asserted at the same time as an SOF",
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+ },
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+ {
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+ .bitmask = BIT(20),
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+ .err_type = CAM_ISP_HW_ERROR_CSID_FIFO_OVERFLOW,
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+ .err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
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+ .desc = "Two or more RDIs programmed to access the shared line buffer",
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+ },
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+};
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+
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static struct cam_irq_register_set cam_ife_csid_780_irq_reg_set[9] = {
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static struct cam_irq_register_set cam_ife_csid_780_irq_reg_set[9] = {
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/* Top */
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/* Top */
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{
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{
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@@ -200,7 +454,7 @@ static struct cam_ife_csid_ver2_pxl_reg_info
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.stripe_loc_shift_val = 20,
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.stripe_loc_shift_val = 20,
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.lut_bank_0_sel_val = 0,
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.lut_bank_0_sel_val = 0,
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.lut_bank_1_sel_val = 1,
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.lut_bank_1_sel_val = 1,
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- .fatal_err_mask = 0x186005,
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+ .fatal_err_mask = 0x186007,
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.non_fatal_err_mask = 0x10000000,
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.non_fatal_err_mask = 0x10000000,
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.camif_irq_mask = 0x800000,
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.camif_irq_mask = 0x800000,
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.rup_aup_mask = 0x10001,
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.rup_aup_mask = 0x10001,
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@@ -296,7 +550,7 @@ static struct cam_ife_csid_ver2_pxl_reg_info
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.start_master_sel_shift_val = 4,
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.start_master_sel_shift_val = 4,
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.lut_bank_0_sel_val = 0,
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.lut_bank_0_sel_val = 0,
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.lut_bank_1_sel_val = 1,
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.lut_bank_1_sel_val = 1,
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- .fatal_err_mask = 0x186005,
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+ .fatal_err_mask = 0x186007,
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.non_fatal_err_mask = 0x10000000,
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.non_fatal_err_mask = 0x10000000,
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.rup_aup_mask = 0x40004,
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.rup_aup_mask = 0x40004,
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.top_irq_mask = 0x10,
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.top_irq_mask = 0x10,
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@@ -391,7 +645,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.pix_pattern_shift_val = 24,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.ccif_violation_en = 1,
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- .fatal_err_mask = 0x186005,
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+ .fatal_err_mask = 0x186007,
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.non_fatal_err_mask = 0x10000000,
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.non_fatal_err_mask = 0x10000000,
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.camif_irq_mask = 0x800000,
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.camif_irq_mask = 0x800000,
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.rup_aup_mask = 0x100010,
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.rup_aup_mask = 0x100010,
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@@ -487,7 +741,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.pix_pattern_shift_val = 24,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.ccif_violation_en = 1,
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- .fatal_err_mask = 0x186005,
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+ .fatal_err_mask = 0x186007,
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.non_fatal_err_mask = 0x10000000,
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.non_fatal_err_mask = 0x10000000,
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.camif_irq_mask = 0x800000,
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.camif_irq_mask = 0x800000,
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.rup_aup_mask = 0x200020,
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.rup_aup_mask = 0x200020,
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@@ -583,7 +837,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.pix_pattern_shift_val = 24,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.ccif_violation_en = 1,
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- .fatal_err_mask = 0x186005,
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+ .fatal_err_mask = 0x186007,
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.non_fatal_err_mask = 0x10000000,
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.non_fatal_err_mask = 0x10000000,
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.camif_irq_mask = 0x800000,
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.camif_irq_mask = 0x800000,
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.rup_aup_mask = 0x400040,
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.rup_aup_mask = 0x400040,
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@@ -679,7 +933,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.pix_pattern_shift_val = 24,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.ccif_violation_en = 1,
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- .fatal_err_mask = 0x186005,
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+ .fatal_err_mask = 0x186007,
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.non_fatal_err_mask = 0x10000000,
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.non_fatal_err_mask = 0x10000000,
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.camif_irq_mask = 0x800000,
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.camif_irq_mask = 0x800000,
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.rup_aup_mask = 0x800080,
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.rup_aup_mask = 0x800080,
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@@ -775,7 +1029,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
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.pix_pattern_shift_val = 24,
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.pix_pattern_shift_val = 24,
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.stripe_loc_shift_val = 20,
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.stripe_loc_shift_val = 20,
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.ccif_violation_en = 1,
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.ccif_violation_en = 1,
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- .fatal_err_mask = 0x186005,
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+ .fatal_err_mask = 0x186007,
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.non_fatal_err_mask = 0x10000000,
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.non_fatal_err_mask = 0x10000000,
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.camif_irq_mask = 0x800000,
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.camif_irq_mask = 0x800000,
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.rup_aup_mask = 0x1000100,
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.rup_aup_mask = 0x1000100,
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@@ -913,7 +1167,7 @@ static struct cam_ife_csid_ver2_common_reg_info
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.ipp_irq_mask_all = 0x7FFF,
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.ipp_irq_mask_all = 0x7FFF,
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.rdi_irq_mask_all = 0x7FFF,
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.rdi_irq_mask_all = 0x7FFF,
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.ppp_irq_mask_all = 0xFFFF,
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.ppp_irq_mask_all = 0xFFFF,
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- .top_err_irq_mask = 0x2,
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+ .top_err_irq_mask = 0x1C0002,
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.rst_loc_path_only_val = 0x0,
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.rst_loc_path_only_val = 0x0,
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.rst_loc_complete_csid_val = 0x1,
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.rst_loc_complete_csid_val = 0x1,
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.rst_mode_frame_boundary_val = 0x0,
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.rst_mode_frame_boundary_val = 0x0,
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@@ -1004,5 +1258,9 @@ static struct cam_ife_csid_ver2_reg_info cam_ife_csid_780_reg_info = {
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},
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},
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.need_top_cfg = 0x1,
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.need_top_cfg = 0x1,
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.csid_cust_node_map = {0x1, 0x0, 0x2},
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.csid_cust_node_map = {0x1, 0x0, 0x2},
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+ .rx_irq_desc = cam_ife_csid_780_rx_irq_desc,
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+ .path_irq_desc = cam_ife_csid_780_path_irq_desc,
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+ .top_irq_desc = cam_ife_csid_780_top_irq_desc,
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+ .num_top_err_irqs = ARRAY_SIZE(cam_ife_csid_780_top_irq_desc),
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};
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};
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#endif /*_CAM_IFE_CSID_780_H_ */
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#endif /*_CAM_IFE_CSID_780_H_ */
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