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@@ -29,7 +29,7 @@
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#include "cam_context.h"
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#define MAX_CSIPHY 6
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-#define MAX_DPHY_DATA_LN 4
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+
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#define MAX_LRME_V4l2_EVENTS 30
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#define CSIPHY_NUM_CLK_MAX 16
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#define MAX_CSIPHY_REG_ARRAY 70
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@@ -41,6 +41,7 @@
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#define MAX_DATA_RATE_REGS 30
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#define CAMX_CSIPHY_DEV_NAME "cam-csiphy-driver"
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+#define CAM_CSIPHY_RX_CLK_SRC "cphy_rx_src_clk"
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#define CSIPHY_POWER_UP 0
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#define CSIPHY_POWER_DOWN 1
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@@ -53,19 +54,24 @@
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#define CSIPHY_2PH_REGS 5
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#define CSIPHY_3PH_REGS 6
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-#define CSIPHY_MAX_INSTANCES 2
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+#define CSIPHY_MAX_INSTANCES_PER_PHY 3
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#define CAM_CSIPHY_MAX_DPHY_LANES 4
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#define CAM_CSIPHY_MAX_CPHY_LANES 3
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+#define CAM_CSIPHY_MAX_CPHY_DPHY_COMBO_LN 3
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+#define CAM_CSIPHY_MAX_CPHY_COMBO_LN 3
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-#define ENABLE_IRQ false
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-#undef CDBG
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-#ifdef CAM_CSIPHY_CORE_DEBUG
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-#define CDBG(fmt, args...) pr_err(fmt, ##args)
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-#else
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-#define CDBG(fmt, args...) pr_debug(fmt, ##args)
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-#endif
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+#define DPHY_LANE_0 BIT(0)
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+#define CPHY_LANE_0 BIT(1)
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+#define DPHY_LANE_1 BIT(2)
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+#define CPHY_LANE_1 BIT(3)
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+#define DPHY_LANE_2 BIT(4)
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+#define CPHY_LANE_2 BIT(5)
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+#define DPHY_LANE_3 BIT(6)
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+#define DPHY_CLK_LN BIT(7)
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+
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+#define ENABLE_IRQ false
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enum cam_csiphy_state {
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CAM_CSIPHY_INIT,
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@@ -111,6 +117,7 @@ struct csiphy_reg_parms_t {
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uint32_t csiphy_reset_array_size;
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uint32_t csiphy_2ph_config_array_size;
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uint32_t csiphy_3ph_config_array_size;
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+ uint32_t csiphy_2ph_3ph_config_array_size;
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uint32_t csiphy_cpas_cp_bits_per_phy;
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uint32_t csiphy_cpas_cp_is_interleaved;
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uint32_t csiphy_cpas_cp_2ph_offset;
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@@ -123,22 +130,17 @@ struct csiphy_reg_parms_t {
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* struct csiphy_intf_params
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* @device_hdl: Device Handle
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* @session_hdl: Session Handle
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- * @ops: KMD operations
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- * @crm_cb: Callback API pointers
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*/
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-struct csiphy_intf_params {
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- int32_t device_hdl[CSIPHY_MAX_INSTANCES];
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- int32_t session_hdl[CSIPHY_MAX_INSTANCES];
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- int32_t link_hdl[CSIPHY_MAX_INSTANCES];
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- struct cam_req_mgr_kmd_ops ops;
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- struct cam_req_mgr_crm_cb *crm_cb;
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+struct csiphy_hdl_tbl {
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+ int32_t device_hdl;
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+ int32_t session_hdl;
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};
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/**
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* struct csiphy_reg_t
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- * @reg_addr: Register address
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- * @reg_data: Register data
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- * @delay: Delay in us
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+ * @reg_addr: Register address
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+ * @reg_data: Register data
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+ * @delay: Delay in us
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* @csiphy_param_type: CSIPhy parameter type
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*/
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struct csiphy_reg_t {
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@@ -200,38 +202,35 @@ struct csiphy_ctrl_t {
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struct csiphy_reg_t (*csiphy_2ph_reg)[MAX_SETTINGS_PER_LANE];
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struct csiphy_reg_t (*csiphy_2ph_combo_mode_reg)[MAX_SETTINGS_PER_LANE];
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struct csiphy_reg_t (*csiphy_3ph_reg)[MAX_SETTINGS_PER_LANE];
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+ struct csiphy_reg_t (*csiphy_3ph_combo_reg)[MAX_SETTINGS_PER_LANE];
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struct csiphy_reg_t (*csiphy_2ph_3ph_mode_reg)[MAX_SETTINGS_PER_LANE];
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- enum cam_vote_level (*getclockvoting)(struct csiphy_device *phy_dev);
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+ enum cam_vote_level (*getclockvoting)(struct csiphy_device *phy_dev,
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+ int32_t index);
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struct data_rate_settings_t *data_rates_settings_table;
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};
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/**
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- * cam_csiphy_param: Provides cmdbuffer structre
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- * @lane_mask : Lane mask details
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- * @lane_assign : Lane sensor will be using
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- * @csiphy_3phase : Mentions DPHY or CPHY
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- * @combo_mode : Info regarding combo_mode is enable / disable
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- * @lane_cnt : Total number of lanes
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- * @reserved
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- * @3phase : Details whether 3Phase / 2Phase operation
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- * @settle_time : Settling time in ms
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- * @settle_time_combo_sensor : Settling time in ms
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- * @data_rate : Data rate in mbps
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- * @data_rate_combo_sensor: data rate of combo sensor
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- * in the the same phy
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- *
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+ * cam_csiphy_param : Provides cmdbuffer structure
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+ * @lane_assign : Lane sensor will be using
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+ * @lane_cnt : Total number of lanes
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+ * @secure_mode : To identify whether stream is secure/nonsecure
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+ * @lane_enable : Data Lane selection
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+ * @settle_time : Settling time in ms
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+ * @data_rate : Data rate in mbps
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+ * @csiphy_3phase : To identify DPHY or CPHY
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+ * @csiphy_cpas_cp_reg_mask : CP reg mask for phy instance
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+ * @hdl_data : CSIPHY handle table
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*/
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struct cam_csiphy_param {
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- uint16_t lane_mask;
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- uint16_t lane_assign;
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- uint8_t csiphy_3phase;
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- uint8_t combo_mode;
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- uint8_t lane_cnt;
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- uint8_t secure_mode[CSIPHY_MAX_INSTANCES];
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- uint64_t settle_time;
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- uint64_t settle_time_combo_sensor;
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- uint64_t data_rate;
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- uint64_t data_rate_combo_sensor;
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+ uint16_t lane_assign;
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+ uint8_t lane_cnt;
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+ uint8_t secure_mode;
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+ uint32_t lane_enable;
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+ uint64_t settle_time;
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+ uint64_t data_rate;
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+ int csiphy_3phase;
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+ uint64_t csiphy_cpas_cp_reg_mask;
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+ struct csiphy_hdl_tbl hdl_data;
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};
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/**
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@@ -255,41 +254,50 @@ struct cam_csiphy_param {
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* @csi_3phase: Is it a 3Phase mode
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* @ref_count: Reference count
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* @clk_lane: Clock lane
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+ * @rx_clk_src_idx: Phy src clk index
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* @acquire_count: Acquire device count
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* @start_dev_count: Start count
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- * @is_acquired_dev_combo_mode: Flag that mentions whether already acquired
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- * device is for combo mode
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* @soc_info: SOC information
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* @cpas_handle: CPAS handle
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* @config_count: Config reg count
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- * @csiphy_cpas_cp_reg_mask: CP reg mask for phy instance
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+ * @current_data_rate: Data rate in mbps
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+ * @csiphy_3phase: To identify DPHY or CPHY at top level
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+ * @combo_mode: Info regarding combo_mode is enable / disable
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+ * @ops: KMD operations
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+ * @crm_cb: Callback API pointers
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*/
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struct csiphy_device {
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- char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH];
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- struct mutex mutex;
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- uint32_t hw_version;
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- enum cam_csiphy_state csiphy_state;
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- struct csiphy_ctrl_t *ctrl_reg;
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- uint32_t csiphy_max_clk;
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- struct msm_cam_clk_info csiphy_3p_clk_info[2];
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- struct clk *csiphy_3p_clk[2];
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- unsigned char csi_3phase;
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- int32_t ref_count;
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- uint16_t lane_mask[MAX_CSIPHY];
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- uint8_t is_csiphy_3phase_hw;
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- uint8_t is_divisor_32_comp;
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- uint8_t num_irq_registers;
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- struct cam_subdev v4l2_dev_str;
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- struct cam_csiphy_param csiphy_info;
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- struct csiphy_intf_params bridge_intf;
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- uint32_t clk_lane;
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- uint32_t acquire_count;
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- uint32_t start_dev_count;
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- uint32_t is_acquired_dev_combo_mode;
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- struct cam_hw_soc_info soc_info;
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- uint32_t cpas_handle;
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- uint32_t config_count;
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- uint64_t csiphy_cpas_cp_reg_mask[CSIPHY_MAX_INSTANCES];
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+ char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH];
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+ struct mutex mutex;
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+ uint32_t hw_version;
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+ enum cam_csiphy_state csiphy_state;
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+ struct csiphy_ctrl_t *ctrl_reg;
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+ uint32_t csiphy_max_clk;
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+ struct msm_cam_clk_info csiphy_3p_clk_info[2];
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+ struct clk *csiphy_3p_clk[2];
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+ int32_t ref_count;
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+ uint16_t lane_mask[MAX_CSIPHY];
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+ uint8_t is_csiphy_3phase_hw;
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+ uint8_t is_divisor_32_comp;
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+ uint8_t num_irq_registers;
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+ struct cam_subdev v4l2_dev_str;
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+ struct cam_csiphy_param csiphy_info[
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+ CSIPHY_MAX_INSTANCES_PER_PHY];
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+ uint32_t clk_lane;
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+ uint8_t rx_clk_src_idx;
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+ uint32_t acquire_count;
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+ uint32_t start_dev_count;
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+ struct cam_hw_soc_info soc_info;
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+ uint32_t cpas_handle;
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+ uint32_t config_count;
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+ uint64_t current_data_rate;
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+ uint64_t csiphy_cpas_cp_reg_mask[
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+ CSIPHY_MAX_INSTANCES_PER_PHY];
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+ uint8_t session_max_device_support;
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+ uint8_t combo_mode;
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+ uint8_t cphy_dphy_combo_mode;
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+ struct cam_req_mgr_kmd_ops ops;
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+ struct cam_req_mgr_crm_cb *crm_cb;
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};
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/**
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Camera Software Integration