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@@ -5928,6 +5928,7 @@ static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
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if (mi2s_intf_conf[index].msm_is_ext_mclk) {
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pr_debug("%s: Enabling mclk, clk_freq_in_hz = %u\n",
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__func__, mi2s_mclk[index].clk_freq_in_hz);
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+ mi2s_mclk[index].enable = 1;
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ret = afe_set_lpass_clock_v2(port_id,
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&mi2s_mclk[index]);
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if (ret < 0) {
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@@ -5935,7 +5936,6 @@ static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
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__func__, ret);
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goto clk_off;
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}
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- mi2s_mclk[index].enable = 1;
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}
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if (pdata->mi2s_gpio_p[index])
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msm_cdc_pinctrl_select_active_state(
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@@ -5988,12 +5988,12 @@ static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
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if (mi2s_intf_conf[index].msm_is_ext_mclk) {
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pr_debug("%s: Disabling mclk, clk_freq_in_hz = %u\n",
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__func__, mi2s_mclk[index].clk_freq_in_hz);
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+ mi2s_mclk[index].enable = 0;
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ret = afe_set_lpass_clock_v2(port_id,
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&mi2s_mclk[index]);
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if (ret < 0)
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pr_err("%s: mclk disable failed for MCLK (%d); ret=%d\n",
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__func__, index, ret);
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- mi2s_mclk[index].enable = 0;
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}
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}
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mutex_unlock(&mi2s_intf_conf[index].lock);
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qctecmdr