msm: camera: cpas: Disable ICP QoS registers for kalama

Disable cpas writing to ICP QoS registers, since they are in
ICP clock domain, which has not been enabled by the time cpas
probes to configure the registers.

CRs-Fixed: 3048249
Change-Id: Iaada5194a06408ecee69cb724eb94c6ffb7bfb95
Signed-off-by: Karthik Jayakumar <[email protected]>

drivers/cam_cpas/cam_cpas_hw.c

@@ -130,8 +130,8 @@ int cam_cpas_util_reg_update(struct cam_hw_info *cpas_hw,
 		value = reg_info->value;
 	}
 
-	CAM_DBG(CAM_CPAS, "Base[%d] Offset[0x%08x] Value[0x%08x]",
-		reg_base, reg_info->offset, value);
+	CAM_DBG(CAM_CPAS, "Base[%d]:[0x%08x] Offset[0x%08x] Value[0x%08x]",
+		reg_base, soc_info->reg_map[reg_base_index].mem_base, reg_info->offset, value);
 
 	cam_io_w_mb(value, soc_info->reg_map[reg_base_index].mem_base +
 		reg_info->offset);

drivers/cam_cpas/cam_cpas_soc.c

@@ -229,6 +229,8 @@ static int cam_cpas_parse_node_tree(struct cam_cpas *cpas_core,
 		if (!level_node)
 			continue;
 
+		CAM_DBG(CAM_CPAS, "Parsing level %d nodes", level_idx);
+
 		camnoc_max_needed = of_property_read_bool(level_node,
 			"camnoc-max-needed");
 		for_each_available_child_of_node(level_node, curr_node) {
@@ -246,6 +248,9 @@ static int cam_cpas_parse_node_tree(struct cam_cpas *cpas_core,
 				return rc;
 			}
 
+			CAM_DBG(CAM_CPAS, "Parsing Node with cell index %d",
+					curr_node_ptr->cell_idx);
+
 			if (curr_node_ptr->cell_idx >=
 				CAM_CPAS_MAX_TREE_NODES) {
 				CAM_ERR(CAM_CPAS, "Invalid cell idx: %d",

drivers/cam_cpas/cpas_top/cam_cpastop_hw.c

@@ -737,6 +737,8 @@ static int cam_cpastop_print_poweron_settings(struct cam_hw_info *cpas_hw)
 				&camnoc_info->specific[i].ubwc_ctl);
 			cam_cpas_util_reg_read(cpas_hw, CAM_CPAS_REG_CAMNOC,
 				&camnoc_info->specific[i].flag_out_set0_low);
+			cam_cpas_util_reg_read(cpas_hw, CAM_CPAS_REG_CAMNOC,
+				&camnoc_info->specific[i].dynattr_mainctl);
 			cam_cpas_util_reg_read(cpas_hw, CAM_CPAS_REG_CAMNOC,
 				&camnoc_info->specific[i].qosgen_mainctl);
 			cam_cpas_util_reg_read(cpas_hw, CAM_CPAS_REG_CAMNOC,
@@ -776,6 +778,8 @@ static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw)
 				&camnoc_info->specific[i].ubwc_ctl);
 			cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC,
 				&camnoc_info->specific[i].flag_out_set0_low);
+			cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC,
+				&camnoc_info->specific[i].dynattr_mainctl);
 			cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC,
 				&camnoc_info->specific[i].qosgen_mainctl);
 			cam_cpas_util_reg_update(cpas_hw, CAM_CPAS_REG_CAMNOC,

drivers/cam_cpas/cpas_top/cpastop_v780_100.h

@@ -1141,7 +1141,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_name = "ICP_RD_WR",
-		.enable = true,
+		.enable = false,
 		.dynattr_mainctl = {
 			.enable = true,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
@@ -1150,7 +1150,7 @@ static struct cam_camnoc_specific
 			.value = 0x10,
 		},
 		.qosgen_mainctl = {
-			.enable = true,
+			.enable = false,
 			.access_type = CAM_REG_TYPE_READ_WRITE,
 			.masked_value = 0,
 			.offset = 0x5608, /* ICP_RD_WR : NOC_XM_ICP_QOSGEN_MAINCTL */
@@ -1213,4 +1213,3 @@ static struct cam_cpas_camnoc_qchannel cam780_cpas100_qchannel_info = {
 	.qchannel_status = 0x60,
 };
 #endif /* _CPASTOP_V780_100_H_ */
-