ASoC: Add driver support for lpass digital codec
Add driver support to enable lpass digital codec for audio playback and capture usecases. Change-Id: I3d31d31f340db79334700e8fd495f40479e0ec6c Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
This commit is contained in:
Sudheer Papothi
committed by
Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
parent
b3cfeef661
commit
e3ab630202
@@ -256,6 +256,7 @@ ifeq ($(KERNEL_BUILD), 1)
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obj-y += wcd937x/
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obj-y += wcd938x/
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obj-y += bolero/
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obj-y += lpass-cdc/
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obj-y += wsa883x/
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obj-y += rouleur/
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endif
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159
asoc/codecs/lpass-cdc/Kbuild
Normal file
159
asoc/codecs/lpass-cdc/Kbuild
Normal file
@@ -0,0 +1,159 @@
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# We can build either as part of a standalone Kernel build or as
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# an external module. Determine which mechanism is being used
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ifeq ($(MODNAME),)
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KERNEL_BUILD := 1
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else
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KERNEL_BUILD := 0
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endif
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ifeq ($(KERNEL_BUILD), 1)
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# These are configurable via Kconfig for kernel-based builds
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# Need to explicitly configure for Android-based builds
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AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
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AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
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endif
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ifeq ($(KERNEL_BUILD), 0)
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ifeq ($(CONFIG_ARCH_SM6150), y)
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include $(AUDIO_ROOT)/config/sm6150auto.conf
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export
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INCS += -include $(AUDIO_ROOT)/config/sm6150autoconf.h
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endif
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ifeq ($(CONFIG_ARCH_TRINKET), y)
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include $(AUDIO_ROOT)/config/sm6150auto.conf
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export
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INCS += -include $(AUDIO_ROOT)/config/sm6150autoconf.h
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endif
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ifeq ($(CONFIG_ARCH_KONA), y)
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include $(AUDIO_ROOT)/config/konaauto.conf
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INCS += -include $(AUDIO_ROOT)/config/konaautoconf.h
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endif
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ifeq ($(CONFIG_ARCH_LITO), y)
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include $(AUDIO_ROOT)/config/litoauto.conf
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export
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INCS += -include $(AUDIO_ROOT)/config/litoautoconf.h
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endif
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ifeq ($(CONFIG_ARCH_BENGAL), y)
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include $(AUDIO_ROOT)/config/bengalauto.conf
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export
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INCS += -include $(AUDIO_ROOT)/config/bengalautoconf.h
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endif
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ifeq ($(CONFIG_ARCH_QCS405), y)
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include $(AUDIO_ROOT)/config/qcs405auto.conf
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export
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INCS += -include $(AUDIO_ROOT)/config/qcs405autoconf.h
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endif
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endif
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# As per target team, build is done as follows:
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# Defconfig : build with default flags
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# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
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# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
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# Perf : Using appropriate msmXXXX-perf_defconfig
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#
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# Shipment builds (user variants) should not have any debug feature
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# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
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# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
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# there is no other way to identify defconfig builds, QTI internal
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# representation of perf builds (identified using the string 'perf'),
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# is used to identify if the build is a slub or defconfig one. This
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# way no critical debug feature will be enabled for perf and shipment
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# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
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# config.
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############ UAPI ############
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UAPI_DIR := uapi/audio
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UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
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############ COMMON ############
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COMMON_DIR := include
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COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
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############ LPASS_CDC ############
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# for LPASS_CDC Codec
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ifdef CONFIG_SND_SOC_LPASS_CDC
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LPASS_CDC_OBJS += lpass-cdc.o
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LPASS_CDC_OBJS += lpass-cdc-utils.o
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LPASS_CDC_OBJS += lpass-cdc-regmap.o
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LPASS_CDC_OBJS += lpass-cdc-tables.o
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LPASS_CDC_OBJS += lpass-cdc-clk-rsc.o
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endif
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ifdef CONFIG_WSA_MACRO
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WSA_OBJS += lpass-cdc-wsa-macro.o
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endif
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ifdef CONFIG_VA_MACRO
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VA_OBJS += lpass-cdc-va-macro.o
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endif
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ifdef CONFIG_TX_MACRO
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TX_OBJS += lpass-cdc-tx-macro.o
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endif
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ifdef CONFIG_RX_MACRO
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RX_OBJS += lpass-cdc-rx-macro.o
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endif
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LINUX_INC += -Iinclude/linux
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INCS += $(COMMON_INC) \
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$(UAPI_INC)
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EXTRA_CFLAGS += $(INCS)
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CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
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-DANI_LITTLE_BIT_ENDIAN \
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-DDOT11F_LITTLE_ENDIAN_HOST \
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-DANI_COMPILER_TYPE_GCC \
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-DANI_OS_TYPE_ANDROID=6 \
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-DPTT_SOCK_SVC_ENABLE \
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-Wall\
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-Werror\
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-D__linux__
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KBUILD_CPPFLAGS += $(CDEFINES)
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# Currently, for versions of gcc which support it, the kernel Makefile
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# is disabling the maybe-uninitialized warning. Re-enable it for the
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# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
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# will override the kernel settings.
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ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
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EXTRA_CFLAGS += -Wmaybe-uninitialized
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endif
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#EXTRA_CFLAGS += -Wmissing-prototypes
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ifeq ($(call cc-option-yn, -Wheader-guard),y)
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EXTRA_CFLAGS += -Wheader-guard
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endif
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ifeq ($(KERNEL_BUILD), 0)
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KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
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KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
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KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
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KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
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KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
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endif
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# Module information used by KBuild framework
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obj-$(CONFIG_SND_SOC_LPASS_CDC) += lpass_cdc_dlkm.o
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lpass_cdc_dlkm-y := $(LPASS_CDC_OBJS)
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obj-$(CONFIG_WSA_MACRO) += wsa_macro_dlkm.o
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wsa_macro_dlkm-y := $(WSA_OBJS)
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obj-$(CONFIG_VA_MACRO) += va_macro_dlkm.o
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va_macro_dlkm-y := $(VA_OBJS)
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obj-$(CONFIG_TX_MACRO) += tx_macro_dlkm.o
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tx_macro_dlkm-y := $(TX_OBJS)
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obj-$(CONFIG_RX_MACRO) += rx_macro_dlkm.o
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rx_macro_dlkm-y := $(RX_OBJS)
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# inject some build related information
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DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"
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111
asoc/codecs/lpass-cdc/internal.h
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111
asoc/codecs/lpass-cdc/internal.h
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@@ -0,0 +1,111 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _LPASS_CDC_INTERNAL_H
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#define _LPASS_CDC_INTERNAL_H
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#include "lpass-cdc-registers.h"
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#define LPASS_CDC_CHILD_DEVICES_MAX 6
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/* from lpass_cdc to WCD events */
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enum {
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LPASS_CDC_WCD_EVT_TX_CH_HOLD_CLEAR = 1,
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LPASS_CDC_WCD_EVT_PA_OFF_PRE_SSR,
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LPASS_CDC_WCD_EVT_SSR_DOWN,
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LPASS_CDC_WCD_EVT_SSR_UP,
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LPASS_CDC_WCD_EVT_PA_ON_POST_FSCLK,
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LPASS_CDC_WCD_EVT_PA_ON_POST_FSCLK_ADIE_LB,
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};
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enum {
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REG_NO_ACCESS,
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RD_REG,
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WR_REG,
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RD_WR_REG
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};
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/* from WCD to lpass_cdc events */
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enum {
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WCD_LPASS_CDC_EVT_RX_MUTE = 1, /* for RX mute/unmute */
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WCD_LPASS_CDC_EVT_IMPED_TRUE, /* for imped true */
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WCD_LPASS_CDC_EVT_IMPED_FALSE, /* for imped false */
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WCD_LPASS_CDC_EVT_RX_COMPANDER_SOFT_RST,
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WCD_LPASS_CDC_EVT_BCS_CLK_OFF,
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WCD_LPASS_CDC_EVT_RX_PA_GAIN_UPDATE,
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WCD_LPASS_CDC_EVT_HPHL_HD2_ENABLE, /* to enable hd2 config for hphl */
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WCD_LPASS_CDC_EVT_HPHR_HD2_ENABLE, /* to enable hd2 config for hphr */
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};
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struct wcd_ctrl_platform_data {
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void *handle;
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int (*update_wcd_event)(void *handle, u16 event, u32 data);
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int (*register_notifier)(void *handle,
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struct notifier_block *nblock,
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bool enable);
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};
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struct lpass_cdc_priv {
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struct device *dev;
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struct snd_soc_component *component;
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struct regmap *regmap;
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struct mutex io_lock;
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struct mutex clk_lock;
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struct mutex vote_lock;
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bool va_without_decimation;
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bool macros_supported[MAX_MACRO];
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bool dev_up;
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bool initial_boot;
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struct macro_ops macro_params[MAX_MACRO];
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struct snd_soc_dai_driver *lpass_cdc_dais;
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u16 num_dais;
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u16 num_macros_registered;
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u16 num_macros;
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u16 current_mclk_mux_macro[MAX_MACRO];
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struct work_struct lpass_cdc_add_child_devices_work;
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u32 version;
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struct clk *lpass_core_hw_vote;
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struct clk *lpass_audio_hw_vote;
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int core_hw_vote_count;
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int core_audio_vote_count;
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/* Entry for version info */
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struct snd_info_entry *entry;
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struct snd_info_entry *version_entry;
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int (*read_dev)(struct lpass_cdc_priv *priv,
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u16 macro_id, u16 reg, u8 *val);
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int (*write_dev)(struct lpass_cdc_priv *priv,
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u16 macro_id, u16 reg, u8 val);
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struct platform_device *pdev_child_devices
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[LPASS_CDC_CHILD_DEVICES_MAX];
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u16 child_count;
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struct wcd_ctrl_platform_data plat_data;
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struct device *wcd_dev;
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struct blocking_notifier_head notifier;
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struct device *clk_dev;
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rsc_clk_cb_t rsc_clk_cb;
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s32 dmic_0_1_clk_cnt;
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s32 dmic_2_3_clk_cnt;
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s32 dmic_4_5_clk_cnt;
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s32 dmic_6_7_clk_cnt;
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u8 dmic_0_1_clk_div;
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u8 dmic_2_3_clk_div;
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u8 dmic_4_5_clk_div;
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u8 dmic_6_7_clk_div;
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};
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struct regmap *lpass_cdc_regmap_init(struct device *dev,
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const struct regmap_config *config);
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int lpass_cdc_get_macro_id(bool va_no_dec_flag, u16 reg);
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extern const struct regmap_config lpass_cdc_regmap_config;
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extern u8 *lpass_cdc_reg_access[MAX_MACRO];
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extern u8 lpass_cdc_va_top_reg_access[LPASS_CDC_VA_MACRO_TOP_MAX];
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extern u8 lpass_cdc_va_reg_access_v2[LPASS_CDC_VA_MACRO_MAX];
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extern u8 lpass_cdc_va_reg_access_v3[LPASS_CDC_VA_MACRO_MAX];
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extern u8 lpass_cdc_tx_reg_access_v2[LPASS_CDC_TX_MACRO_MAX];
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extern const u16 macro_id_base_offset[MAX_MACRO];
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#endif
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768
asoc/codecs/lpass-cdc/lpass-cdc-clk-rsc.c
Normal file
768
asoc/codecs/lpass-cdc/lpass-cdc-clk-rsc.c
Normal file
@@ -0,0 +1,768 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/of_platform.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include "lpass-cdc.h"
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#include "lpass-cdc-clk-rsc.h"
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#define DRV_NAME "lpass-cdc-clk-rsc"
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#define LPASS_CDC_CLK_NAME_LENGTH 30
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#define NPL_CLK_OFFSET (TX_NPL_CLK - TX_CORE_CLK)
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static char clk_src_name[MAX_CLK][LPASS_CDC_CLK_NAME_LENGTH] = {
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"tx_core_clk",
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"rx_core_clk",
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"wsa_core_clk",
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"va_core_clk",
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"tx_npl_clk",
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"rx_npl_clk",
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"wsa_npl_clk",
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"va_npl_clk",
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};
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struct lpass_cdc_clk_rsc {
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struct device *dev;
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struct mutex rsc_clk_lock;
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struct mutex fs_gen_lock;
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struct clk *clk[MAX_CLK];
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int clk_cnt[MAX_CLK];
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int reg_seq_en_cnt;
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int va_tx_clk_cnt;
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bool dev_up;
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bool dev_up_gfmux;
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u32 num_fs_reg;
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u32 *fs_gen_seq;
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int default_clk_id[MAX_CLK];
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struct regmap *regmap;
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char __iomem *rx_clk_muxsel;
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char __iomem *wsa_clk_muxsel;
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char __iomem *va_clk_muxsel;
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};
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static int lpass_cdc_clk_rsc_cb(struct device *dev, u16 event)
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{
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struct lpass_cdc_clk_rsc *priv;
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if (!dev) {
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pr_err("%s: Invalid device pointer\n",
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__func__);
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return -EINVAL;
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}
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priv = dev_get_drvdata(dev);
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if (!priv) {
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pr_err("%s: Invalid clk rsc priviate data\n",
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__func__);
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return -EINVAL;
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}
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mutex_lock(&priv->rsc_clk_lock);
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if (event == LPASS_CDC_MACRO_EVT_SSR_UP) {
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priv->dev_up = true;
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} else if (event == LPASS_CDC_MACRO_EVT_SSR_DOWN) {
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priv->dev_up = false;
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priv->dev_up_gfmux = false;
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} else if (event == LPASS_CDC_MACRO_EVT_SSR_GFMUX_UP) {
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priv->dev_up_gfmux = true;
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}
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mutex_unlock(&priv->rsc_clk_lock);
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return 0;
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}
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static char __iomem *lpass_cdc_clk_rsc_get_clk_muxsel(struct lpass_cdc_clk_rsc *priv,
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int clk_id)
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{
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switch (clk_id) {
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case RX_CORE_CLK:
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return priv->rx_clk_muxsel;
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case WSA_CORE_CLK:
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return priv->wsa_clk_muxsel;
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case VA_CORE_CLK:
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return priv->va_clk_muxsel;
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case TX_CORE_CLK:
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default:
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dev_err_ratelimited(priv->dev, "%s: Invalid case\n", __func__);
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break;
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}
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return NULL;
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}
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int lpass_cdc_rsc_clk_reset(struct device *dev, int clk_id)
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{
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struct device *clk_dev = NULL;
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struct lpass_cdc_clk_rsc *priv = NULL;
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int count = 0;
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if (!dev) {
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pr_err("%s: dev is null %d\n", __func__);
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return -EINVAL;
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}
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if (clk_id < 0 || clk_id >= MAX_CLK - NPL_CLK_OFFSET) {
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pr_err("%s: Invalid clk_id: %d\n",
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__func__, clk_id);
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return -EINVAL;
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}
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clk_dev = lpass_cdc_get_rsc_clk_device_ptr(dev->parent);
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if (!clk_dev) {
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pr_err("%s: Invalid rsc clk device\n", __func__);
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return -EINVAL;
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}
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priv = dev_get_drvdata(clk_dev);
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if (!priv) {
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pr_err("%s: Invalid rsc clk priviate data\n", __func__);
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return -EINVAL;
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}
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mutex_lock(&priv->rsc_clk_lock);
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while (__clk_is_enabled(priv->clk[clk_id])) {
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clk_disable_unprepare(priv->clk[clk_id + NPL_CLK_OFFSET]);
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clk_disable_unprepare(priv->clk[clk_id]);
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count++;
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}
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dev_dbg(priv->dev,
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"%s: clock reset after ssr, count %d\n", __func__, count);
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trace_printk("%s: clock reset after ssr, count %d\n", __func__, count);
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while (count--) {
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clk_prepare_enable(priv->clk[clk_id]);
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clk_prepare_enable(priv->clk[clk_id + NPL_CLK_OFFSET]);
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}
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mutex_unlock(&priv->rsc_clk_lock);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(lpass_cdc_rsc_clk_reset);
|
||||
|
||||
void lpass_cdc_clk_rsc_enable_all_clocks(struct device *dev, bool enable)
|
||||
{
|
||||
struct device *clk_dev = NULL;
|
||||
struct lpass_cdc_clk_rsc *priv = NULL;
|
||||
int i = 0;
|
||||
|
||||
if (!dev) {
|
||||
pr_err("%s: dev is null %d\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
clk_dev = lpass_cdc_get_rsc_clk_device_ptr(dev->parent);
|
||||
if (!clk_dev) {
|
||||
pr_err("%s: Invalid rsc clk device\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
priv = dev_get_drvdata(clk_dev);
|
||||
if (!priv) {
|
||||
pr_err("%s: Invalid rsc clk private data\n", __func__);
|
||||
return;
|
||||
}
|
||||
mutex_lock(&priv->rsc_clk_lock);
|
||||
for (i = 0; i < MAX_CLK - NPL_CLK_OFFSET; i++) {
|
||||
if (enable) {
|
||||
if (priv->clk[i])
|
||||
clk_prepare_enable(priv->clk[i]);
|
||||
if (priv->clk[i + NPL_CLK_OFFSET])
|
||||
clk_prepare_enable(
|
||||
priv->clk[i + NPL_CLK_OFFSET]);
|
||||
} else {
|
||||
if (priv->clk[i + NPL_CLK_OFFSET])
|
||||
clk_disable_unprepare(
|
||||
priv->clk[i + NPL_CLK_OFFSET]);
|
||||
if (priv->clk[i])
|
||||
clk_disable_unprepare(priv->clk[i]);
|
||||
}
|
||||
}
|
||||
mutex_unlock(&priv->rsc_clk_lock);
|
||||
return;
|
||||
}
|
||||
EXPORT_SYMBOL(lpass_cdc_clk_rsc_enable_all_clocks);
|
||||
|
||||
static int lpass_cdc_clk_rsc_mux0_clk_request(struct lpass_cdc_clk_rsc *priv,
|
||||
int clk_id,
|
||||
bool enable)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (enable) {
|
||||
/* Enable Requested Core clk */
|
||||
if (priv->clk_cnt[clk_id] == 0) {
|
||||
ret = clk_prepare_enable(priv->clk[clk_id]);
|
||||
if (ret < 0) {
|
||||
dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
|
||||
__func__, clk_id);
|
||||
goto done;
|
||||
}
|
||||
if (priv->clk[clk_id + NPL_CLK_OFFSET]) {
|
||||
ret = clk_prepare_enable(
|
||||
priv->clk[clk_id + NPL_CLK_OFFSET]);
|
||||
if (ret < 0) {
|
||||
dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
|
||||
__func__,
|
||||
clk_id + NPL_CLK_OFFSET);
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
}
|
||||
priv->clk_cnt[clk_id]++;
|
||||
} else {
|
||||
if (priv->clk_cnt[clk_id] <= 0) {
|
||||
dev_err_ratelimited(priv->dev, "%s: clk_id: %d is already disabled\n",
|
||||
__func__, clk_id);
|
||||
priv->clk_cnt[clk_id] = 0;
|
||||
goto done;
|
||||
}
|
||||
priv->clk_cnt[clk_id]--;
|
||||
if (priv->clk_cnt[clk_id] == 0) {
|
||||
if (priv->clk[clk_id + NPL_CLK_OFFSET])
|
||||
clk_disable_unprepare(
|
||||
priv->clk[clk_id + NPL_CLK_OFFSET]);
|
||||
clk_disable_unprepare(priv->clk[clk_id]);
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
|
||||
err:
|
||||
clk_disable_unprepare(priv->clk[clk_id]);
|
||||
done:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
|
||||
int clk_id,
|
||||
bool enable)
|
||||
{
|
||||
char __iomem *clk_muxsel = NULL;
|
||||
int ret = 0;
|
||||
int default_clk_id = priv->default_clk_id[clk_id];
|
||||
u32 muxsel = 0;
|
||||
|
||||
clk_muxsel = lpass_cdc_clk_rsc_get_clk_muxsel(priv, clk_id);
|
||||
if (!clk_muxsel) {
|
||||
ret = -EINVAL;
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (enable) {
|
||||
if (priv->clk_cnt[clk_id] == 0) {
|
||||
if (clk_id != VA_CORE_CLK) {
|
||||
ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
|
||||
default_clk_id,
|
||||
true);
|
||||
if (ret < 0)
|
||||
goto done;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(priv->clk[clk_id]);
|
||||
if (ret < 0) {
|
||||
dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
|
||||
__func__, clk_id);
|
||||
goto err_clk;
|
||||
}
|
||||
if (priv->clk[clk_id + NPL_CLK_OFFSET]) {
|
||||
ret = clk_prepare_enable(
|
||||
priv->clk[clk_id + NPL_CLK_OFFSET]);
|
||||
if (ret < 0) {
|
||||
dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
|
||||
__func__,
|
||||
clk_id + NPL_CLK_OFFSET);
|
||||
goto err_npl_clk;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Temp SW workaround to address a glitch issue of
|
||||
* VA GFMux instance responsible for switching from
|
||||
* TX MCLK to VA MCLK. This configuration would be taken
|
||||
* care in DSP itself
|
||||
*/
|
||||
if (clk_id != VA_CORE_CLK) {
|
||||
if (priv->dev_up_gfmux) {
|
||||
iowrite32(0x1, clk_muxsel);
|
||||
muxsel = ioread32(clk_muxsel);
|
||||
trace_printk("%s: muxsel value after enable: %d\n",
|
||||
__func__, muxsel);
|
||||
}
|
||||
lpass_cdc_clk_rsc_mux0_clk_request(priv,
|
||||
default_clk_id,
|
||||
false);
|
||||
}
|
||||
}
|
||||
priv->clk_cnt[clk_id]++;
|
||||
} else {
|
||||
if (priv->clk_cnt[clk_id] <= 0) {
|
||||
dev_err_ratelimited(priv->dev, "%s: clk_id: %d is already disabled\n",
|
||||
__func__, clk_id);
|
||||
priv->clk_cnt[clk_id] = 0;
|
||||
goto done;
|
||||
}
|
||||
priv->clk_cnt[clk_id]--;
|
||||
if (priv->clk_cnt[clk_id] == 0) {
|
||||
if (clk_id != VA_CORE_CLK) {
|
||||
ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
|
||||
default_clk_id, true);
|
||||
|
||||
if (!ret) {
|
||||
/*
|
||||
* Temp SW workaround to address a glitch issue
|
||||
* of VA GFMux instance responsible for
|
||||
* switching from TX MCLK to VA MCLK.
|
||||
* This configuration would be taken
|
||||
* care in DSP itself.
|
||||
*/
|
||||
if (priv->dev_up_gfmux) {
|
||||
iowrite32(0x0, clk_muxsel);
|
||||
muxsel = ioread32(clk_muxsel);
|
||||
trace_printk("%s: muxsel value after disable: %d\n",
|
||||
__func__, muxsel);
|
||||
}
|
||||
}
|
||||
}
|
||||
if (priv->clk[clk_id + NPL_CLK_OFFSET])
|
||||
clk_disable_unprepare(
|
||||
priv->clk[clk_id + NPL_CLK_OFFSET]);
|
||||
clk_disable_unprepare(priv->clk[clk_id]);
|
||||
|
||||
if (clk_id != VA_CORE_CLK) {
|
||||
if (!ret)
|
||||
lpass_cdc_clk_rsc_mux0_clk_request(priv,
|
||||
default_clk_id, false);
|
||||
}
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
|
||||
err_npl_clk:
|
||||
clk_disable_unprepare(priv->clk[clk_id]);
|
||||
|
||||
err_clk:
|
||||
if (clk_id != VA_CORE_CLK)
|
||||
lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
|
||||
done:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int lpass_cdc_clk_rsc_check_and_update_va_clk(struct lpass_cdc_clk_rsc *priv,
|
||||
bool mux_switch,
|
||||
int clk_id,
|
||||
bool enable)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (enable) {
|
||||
if (clk_id == VA_CORE_CLK && mux_switch) {
|
||||
/*
|
||||
* Handle the following usecase scenarios during enable
|
||||
* 1. VA only, Active clk is VA_CORE_CLK
|
||||
* 2. record -> record + VA, Active clk is TX_CORE_CLK
|
||||
*/
|
||||
if (priv->clk_cnt[TX_CORE_CLK] == 0) {
|
||||
ret = lpass_cdc_clk_rsc_mux1_clk_request(priv,
|
||||
VA_CORE_CLK, enable);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
} else {
|
||||
ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
|
||||
TX_CORE_CLK, enable);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
priv->va_tx_clk_cnt++;
|
||||
}
|
||||
} else if ((priv->clk_cnt[TX_CORE_CLK] > 0) &&
|
||||
(priv->clk_cnt[VA_CORE_CLK] > 0)) {
|
||||
/*
|
||||
* Handle following concurrency scenario during enable
|
||||
* 1. VA-> Record+VA, Increment TX CLK and Disable VA
|
||||
* 2. VA-> Playback+VA, Increment TX CLK and Disable VA
|
||||
*/
|
||||
while (priv->clk_cnt[VA_CORE_CLK] > 0) {
|
||||
ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
|
||||
TX_CORE_CLK, true);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
|
||||
lpass_cdc_clk_rsc_mux1_clk_request(priv,
|
||||
VA_CORE_CLK, false);
|
||||
priv->va_tx_clk_cnt++;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (clk_id == VA_CORE_CLK && mux_switch) {
|
||||
/*
|
||||
* Handle the following usecase scenarios during disable
|
||||
* 1. VA only, disable VA_CORE_CLK
|
||||
* 2. Record + VA -> Record, decrement TX CLK count
|
||||
*/
|
||||
if (priv->clk_cnt[VA_CORE_CLK]) {
|
||||
lpass_cdc_clk_rsc_mux1_clk_request(priv,
|
||||
VA_CORE_CLK, enable);
|
||||
} else if (priv->va_tx_clk_cnt) {
|
||||
lpass_cdc_clk_rsc_mux0_clk_request(priv,
|
||||
TX_CORE_CLK, enable);
|
||||
priv->va_tx_clk_cnt--;
|
||||
}
|
||||
} else if (priv->va_tx_clk_cnt == priv->clk_cnt[TX_CORE_CLK]) {
|
||||
/*
|
||||
* Handle the following usecase scenarios during disable
|
||||
* Record+VA-> VA: enable VA CLK, decrement TX CLK count
|
||||
*/
|
||||
while (priv->va_tx_clk_cnt) {
|
||||
ret = lpass_cdc_clk_rsc_mux1_clk_request(priv,
|
||||
VA_CORE_CLK, true);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
|
||||
lpass_cdc_clk_rsc_mux0_clk_request(priv,
|
||||
TX_CORE_CLK, false);
|
||||
priv->va_tx_clk_cnt--;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* lpass_cdc_clk_rsc_fs_gen_request - request to enable/disable fs generation
|
||||
* sequence
|
||||
*
|
||||
* @dev: Macro device pointer
|
||||
* @enable: enable or disable flag
|
||||
*/
|
||||
void lpass_cdc_clk_rsc_fs_gen_request(struct device *dev, bool enable)
|
||||
{
|
||||
int i;
|
||||
struct regmap *regmap;
|
||||
struct device *clk_dev = NULL;
|
||||
struct lpass_cdc_clk_rsc *priv = NULL;
|
||||
|
||||
if (!dev) {
|
||||
pr_err("%s: dev is null %d\n", __func__);
|
||||
return;
|
||||
}
|
||||
clk_dev = lpass_cdc_get_rsc_clk_device_ptr(dev->parent);
|
||||
if (!clk_dev) {
|
||||
pr_err("%s: Invalid rsc clk device\n", __func__);
|
||||
return;
|
||||
}
|
||||
priv = dev_get_drvdata(clk_dev);
|
||||
if (!priv) {
|
||||
pr_err("%s: Invalid rsc clk priviate data\n", __func__);
|
||||
return;
|
||||
}
|
||||
regmap = dev_get_regmap(priv->dev->parent, NULL);
|
||||
if (!regmap) {
|
||||
pr_err("%s: regmap is null\n", __func__);
|
||||
return;
|
||||
}
|
||||
mutex_lock(&priv->fs_gen_lock);
|
||||
if (enable) {
|
||||
if (priv->reg_seq_en_cnt++ == 0) {
|
||||
for (i = 0; i < (priv->num_fs_reg * 2); i += 2) {
|
||||
dev_dbg(priv->dev, "%s: Register: %d, value: %d\n",
|
||||
__func__, priv->fs_gen_seq[i],
|
||||
priv->fs_gen_seq[i + 1]);
|
||||
regmap_update_bits(regmap,
|
||||
priv->fs_gen_seq[i],
|
||||
priv->fs_gen_seq[i + 1],
|
||||
priv->fs_gen_seq[i + 1]);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (priv->reg_seq_en_cnt <= 0) {
|
||||
dev_err_ratelimited(priv->dev, "%s: req_seq_cnt: %d is already disabled\n",
|
||||
__func__, priv->reg_seq_en_cnt);
|
||||
priv->reg_seq_en_cnt = 0;
|
||||
mutex_unlock(&priv->fs_gen_lock);
|
||||
return;
|
||||
}
|
||||
if (--priv->reg_seq_en_cnt == 0) {
|
||||
for (i = ((priv->num_fs_reg - 1) * 2); i >= 0; i -= 2) {
|
||||
dev_dbg(priv->dev, "%s: Register: %d, value: %d\n",
|
||||
__func__, priv->fs_gen_seq[i],
|
||||
priv->fs_gen_seq[i + 1]);
|
||||
regmap_update_bits(regmap, priv->fs_gen_seq[i],
|
||||
priv->fs_gen_seq[i + 1], 0x0);
|
||||
}
|
||||
}
|
||||
}
|
||||
mutex_unlock(&priv->fs_gen_lock);
|
||||
}
|
||||
EXPORT_SYMBOL(lpass_cdc_clk_rsc_fs_gen_request);
|
||||
|
||||
/**
|
||||
* lpass_cdc_clk_rsc_request_clock - request for clock to
|
||||
* enable/disable
|
||||
*
|
||||
* @dev: Macro device pointer.
|
||||
* @default_clk_id: mux0 Core clock ID input.
|
||||
* @clk_id_req: Core clock ID requested to enable/disable
|
||||
* @enable: enable or disable clock flag
|
||||
*
|
||||
* Returns 0 on success or -EINVAL on error.
|
||||
*/
|
||||
int lpass_cdc_clk_rsc_request_clock(struct device *dev,
|
||||
int default_clk_id,
|
||||
int clk_id_req,
|
||||
bool enable)
|
||||
{
|
||||
int ret = 0;
|
||||
struct device *clk_dev = NULL;
|
||||
struct lpass_cdc_clk_rsc *priv = NULL;
|
||||
bool mux_switch = false;
|
||||
|
||||
if (!dev) {
|
||||
pr_err("%s: dev is null %d\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
if ((clk_id_req < 0 || clk_id_req >= MAX_CLK) &&
|
||||
(default_clk_id < 0 || default_clk_id >= MAX_CLK)) {
|
||||
pr_err("%s: Invalid clk_id_req: %d or default_clk_id: %d\n",
|
||||
__func__, clk_id_req, default_clk_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
clk_dev = lpass_cdc_get_rsc_clk_device_ptr(dev->parent);
|
||||
if (!clk_dev) {
|
||||
pr_err("%s: Invalid rsc clk device\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
priv = dev_get_drvdata(clk_dev);
|
||||
if (!priv) {
|
||||
pr_err("%s: Invalid rsc clk priviate data\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
mutex_lock(&priv->rsc_clk_lock);
|
||||
if (!priv->dev_up && enable) {
|
||||
dev_err_ratelimited(priv->dev, "%s: SSR is in progress..\n",
|
||||
__func__);
|
||||
trace_printk("%s: SSR is in progress..\n", __func__);
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
priv->default_clk_id[clk_id_req] = default_clk_id;
|
||||
if (default_clk_id != clk_id_req)
|
||||
mux_switch = true;
|
||||
|
||||
if (mux_switch) {
|
||||
if (clk_id_req != VA_CORE_CLK) {
|
||||
ret = lpass_cdc_clk_rsc_mux1_clk_request(priv, clk_id_req,
|
||||
enable);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
}
|
||||
} else {
|
||||
ret = lpass_cdc_clk_rsc_mux0_clk_request(priv, clk_id_req, enable);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = lpass_cdc_clk_rsc_check_and_update_va_clk(priv, mux_switch,
|
||||
clk_id_req,
|
||||
enable);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
|
||||
dev_dbg(priv->dev, "%s: clk_cnt: %d for requested clk: %d, enable: %d\n",
|
||||
__func__, priv->clk_cnt[clk_id_req], clk_id_req,
|
||||
enable);
|
||||
trace_printk("%s: clk_cnt: %d for requested clk: %d, enable: %d\n",
|
||||
__func__, priv->clk_cnt[clk_id_req], clk_id_req,
|
||||
enable);
|
||||
|
||||
mutex_unlock(&priv->rsc_clk_lock);
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
mutex_unlock(&priv->rsc_clk_lock);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(lpass_cdc_clk_rsc_request_clock);
|
||||
|
||||
|
||||
static int lpass_cdc_clk_rsc_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret = 0, fs_gen_size, i, j;
|
||||
const char **clk_name_array;
|
||||
int clk_cnt;
|
||||
struct clk *clk;
|
||||
struct lpass_cdc_clk_rsc *priv = NULL;
|
||||
u32 muxsel = 0;
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev, sizeof(struct lpass_cdc_clk_rsc),
|
||||
GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Get clk fs gen sequence from device tree */
|
||||
if (!of_find_property(pdev->dev.of_node, "qcom,fs-gen-sequence",
|
||||
&fs_gen_size)) {
|
||||
dev_err(&pdev->dev, "%s: unable to find qcom,fs-gen-sequence property\n",
|
||||
__func__);
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
priv->num_fs_reg = fs_gen_size/(2 * sizeof(u32));
|
||||
priv->fs_gen_seq = devm_kzalloc(&pdev->dev, fs_gen_size, GFP_KERNEL);
|
||||
if (!priv->fs_gen_seq) {
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
dev_dbg(&pdev->dev, "%s: num_fs_reg %d\n", __func__, priv->num_fs_reg);
|
||||
/* Parse fs-gen-sequence */
|
||||
ret = of_property_read_u32_array(pdev->dev.of_node,
|
||||
"qcom,fs-gen-sequence",
|
||||
priv->fs_gen_seq,
|
||||
priv->num_fs_reg * 2);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "%s: unable to parse fs-gen-sequence, ret = %d\n",
|
||||
__func__, ret);
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* Get clk details from device tree */
|
||||
clk_cnt = of_property_count_strings(pdev->dev.of_node, "clock-names");
|
||||
if (clk_cnt <= 0 || clk_cnt > MAX_CLK) {
|
||||
dev_err(&pdev->dev, "%s: Invalid number of clocks %d",
|
||||
__func__, clk_cnt);
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
clk_name_array = devm_kzalloc(&pdev->dev, clk_cnt * sizeof(char *),
|
||||
GFP_KERNEL);
|
||||
if (!clk_name_array) {
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = of_property_read_string_array(pdev->dev.of_node, "clock-names",
|
||||
clk_name_array, clk_cnt);
|
||||
|
||||
for (i = 0; i < MAX_CLK; i++) {
|
||||
priv->clk[i] = NULL;
|
||||
for (j = 0; j < clk_cnt; j++) {
|
||||
if (!strcmp(clk_src_name[i], clk_name_array[j])) {
|
||||
clk = devm_clk_get(&pdev->dev, clk_src_name[i]);
|
||||
if (IS_ERR(clk)) {
|
||||
ret = PTR_ERR(clk);
|
||||
dev_err(&pdev->dev, "%s: clk get failed for %s with ret %d\n",
|
||||
__func__, clk_src_name[i], ret);
|
||||
goto err;
|
||||
}
|
||||
priv->clk[i] = clk;
|
||||
dev_dbg(&pdev->dev, "%s: clk get success for clk name %s\n",
|
||||
__func__, clk_src_name[i]);
|
||||
}
|
||||
}
|
||||
}
|
||||
ret = of_property_read_u32(pdev->dev.of_node,
|
||||
"qcom,rx_mclk_mode_muxsel", &muxsel);
|
||||
if (ret) {
|
||||
dev_dbg(&pdev->dev, "%s: could not find qcom,rx_mclk_mode_muxsel entry in dt\n",
|
||||
__func__);
|
||||
} else {
|
||||
priv->rx_clk_muxsel = devm_ioremap(&pdev->dev, muxsel, 0x4);
|
||||
if (!priv->rx_clk_muxsel) {
|
||||
dev_err(&pdev->dev, "%s: ioremap failed for rx muxsel\n",
|
||||
__func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
}
|
||||
ret = of_property_read_u32(pdev->dev.of_node,
|
||||
"qcom,wsa_mclk_mode_muxsel", &muxsel);
|
||||
if (ret) {
|
||||
dev_dbg(&pdev->dev, "%s: could not find qcom,wsa_mclk_mode_muxsel entry in dt\n",
|
||||
__func__);
|
||||
} else {
|
||||
priv->wsa_clk_muxsel = devm_ioremap(&pdev->dev, muxsel, 0x4);
|
||||
if (!priv->wsa_clk_muxsel) {
|
||||
dev_err(&pdev->dev, "%s: ioremap failed for wsa muxsel\n",
|
||||
__func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
}
|
||||
ret = of_property_read_u32(pdev->dev.of_node,
|
||||
"qcom,va_mclk_mode_muxsel", &muxsel);
|
||||
if (ret) {
|
||||
dev_dbg(&pdev->dev, "%s: could not find qcom,va_mclk_mode_muxsel entry in dt\n",
|
||||
__func__);
|
||||
} else {
|
||||
priv->va_clk_muxsel = devm_ioremap(&pdev->dev, muxsel, 0x4);
|
||||
if (!priv->va_clk_muxsel) {
|
||||
dev_err(&pdev->dev, "%s: ioremap failed for va muxsel\n",
|
||||
__func__);
|
||||
return -ENOMEM;
|
||||
}
|
||||
}
|
||||
|
||||
ret = lpass_cdc_register_res_clk(&pdev->dev, lpass_cdc_clk_rsc_cb);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "%s: Failed to register cb %d",
|
||||
__func__, ret);
|
||||
goto err;
|
||||
}
|
||||
priv->dev = &pdev->dev;
|
||||
priv->dev_up = true;
|
||||
priv->dev_up_gfmux = true;
|
||||
mutex_init(&priv->rsc_clk_lock);
|
||||
mutex_init(&priv->fs_gen_lock);
|
||||
dev_set_drvdata(&pdev->dev, priv);
|
||||
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int lpass_cdc_clk_rsc_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct lpass_cdc_clk_rsc *priv = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
lpass_cdc_unregister_res_clk(&pdev->dev);
|
||||
of_platform_depopulate(&pdev->dev);
|
||||
if (!priv)
|
||||
return -EINVAL;
|
||||
mutex_destroy(&priv->rsc_clk_lock);
|
||||
mutex_destroy(&priv->fs_gen_lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id lpass_cdc_clk_rsc_dt_match[] = {
|
||||
{.compatible = "qcom,lpass-cdc-clk-rsc-mngr"},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, lpass_cdc_clk_rsc_dt_match);
|
||||
|
||||
static struct platform_driver lpass_cdc_clk_rsc_mgr = {
|
||||
.driver = {
|
||||
.name = "lpass-cdc-clk-rsc-mngr",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = lpass_cdc_clk_rsc_dt_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = lpass_cdc_clk_rsc_probe,
|
||||
.remove = lpass_cdc_clk_rsc_remove,
|
||||
};
|
||||
|
||||
int lpass_cdc_clk_rsc_mgr_init(void)
|
||||
{
|
||||
return platform_driver_register(&lpass_cdc_clk_rsc_mgr);
|
||||
}
|
||||
|
||||
void lpass_cdc_clk_rsc_mgr_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&lpass_cdc_clk_rsc_mgr);
|
||||
}
|
||||
MODULE_DESCRIPTION("LPASS codec clock resource manager driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
52
asoc/codecs/lpass-cdc/lpass-cdc-clk-rsc.h
Normal file
52
asoc/codecs/lpass-cdc/lpass-cdc-clk-rsc.h
Normal file
@@ -0,0 +1,52 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef LPASS_CDC_CLK_RSC_H
|
||||
#define LPASS_CDC_CLK_RSC_H
|
||||
|
||||
#include <linux/regmap.h>
|
||||
#include <dt-bindings/sound/qcom,lpass-cdc-clk-rsc.h>
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_LPASS_CDC)
|
||||
int lpass_cdc_clk_rsc_mgr_init(void);
|
||||
void lpass_cdc_clk_rsc_mgr_exit(void);
|
||||
void lpass_cdc_clk_rsc_fs_gen_request(struct device *dev,
|
||||
bool enable);
|
||||
int lpass_cdc_clk_rsc_request_clock(struct device *dev,
|
||||
int default_clk_id,
|
||||
int clk_id_req,
|
||||
bool enable);
|
||||
int lpass_cdc_rsc_clk_reset(struct device *dev, int clk_id);
|
||||
void lpass_cdc_clk_rsc_enable_all_clocks(struct device *dev, bool enable);
|
||||
#else
|
||||
static inline void lpass_cdc_clk_rsc_fs_gen_request(struct device *dev,
|
||||
bool enable)
|
||||
{
|
||||
}
|
||||
static inline int lpass_cdc_clk_rsc_mgr_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline void lpass_cdc_clk_rsc_mgr_exit(void)
|
||||
{
|
||||
}
|
||||
static inline int lpass_cdc_clk_rsc_request_clock(struct device *dev,
|
||||
int default_clk_id,
|
||||
int clk_id_req,
|
||||
bool enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int lpass_cdc_rsc_clk_reset(struct device *dev, int clk_id)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline void lpass_cdc_clk_rsc_enable_all_clocks(struct device *dev,
|
||||
bool enable)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* CONFIG_SND_SOC_LPASS_CDC */
|
||||
#endif /* LPASS_CDC_CLK_RSC_H */
|
||||
844
asoc/codecs/lpass-cdc/lpass-cdc-registers.h
Normal file
844
asoc/codecs/lpass-cdc/lpass-cdc-registers.h
Normal file
@@ -0,0 +1,844 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef _LPASS_CDC_REGISTERS_H
|
||||
#define _LPASS_CDC_REGISTERS_H
|
||||
|
||||
#define TX_START_OFFSET 0x0000
|
||||
|
||||
#define LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (TX_START_OFFSET + 0x0000)
|
||||
#define LPASS_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (TX_START_OFFSET + 0x0004)
|
||||
#define LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL (TX_START_OFFSET + 0x0008)
|
||||
#define LPASS_CDC_TX_TOP_CSR_TOP_CFG0 (TX_START_OFFSET + 0x0080)
|
||||
#define LPASS_CDC_TX_TOP_CSR_ANC_CFG (TX_START_OFFSET + 0x0084)
|
||||
#define LPASS_CDC_TX_TOP_CSR_SWR_CTRL (TX_START_OFFSET + 0x0088)
|
||||
#define LPASS_CDC_TX_TOP_CSR_FREQ_MCLK (TX_START_OFFSET + 0x0090)
|
||||
#define LPASS_CDC_TX_TOP_CSR_DEBUG_BUS (TX_START_OFFSET + 0x0094)
|
||||
#define LPASS_CDC_TX_TOP_CSR_DEBUG_EN (TX_START_OFFSET + 0x0098)
|
||||
#define LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL (TX_START_OFFSET + 0x00A4)
|
||||
#define LPASS_CDC_TX_TOP_CSR_I2S_CLK (TX_START_OFFSET + 0x00A8)
|
||||
#define LPASS_CDC_TX_TOP_CSR_I2S_RESET (TX_START_OFFSET + 0x00AC)
|
||||
#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL (TX_START_OFFSET + 0x00C0)
|
||||
#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL (TX_START_OFFSET + 0x00C4)
|
||||
#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL (TX_START_OFFSET + 0x00C8)
|
||||
#define LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL (TX_START_OFFSET + 0x00CC)
|
||||
#define LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL (TX_START_OFFSET + 0x00D0)
|
||||
#define LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL (TX_START_OFFSET + 0x00D4)
|
||||
#define LPASS_CDC_TX_TOP_CSR_SWR_MIC2_CTL (TX_START_OFFSET + 0x00C0)
|
||||
#define LPASS_CDC_TX_TOP_CSR_SWR_MIC3_CTL (TX_START_OFFSET + 0x00C4)
|
||||
#define LPASS_CDC_TX_TOP_CSR_SWR_MIC4_CTL (TX_START_OFFSET + 0x00C8)
|
||||
#define LPASS_CDC_TX_TOP_CSR_SWR_MIC5_CTL (TX_START_OFFSET + 0x00CC)
|
||||
#define LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL (TX_START_OFFSET + 0x00D0)
|
||||
#define LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL (TX_START_OFFSET + 0x00D4)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0 (TX_START_OFFSET + 0x0100)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1 (TX_START_OFFSET + 0x0104)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0 (TX_START_OFFSET + 0x0108)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG1 (TX_START_OFFSET + 0x010C)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0 (TX_START_OFFSET + 0x0110)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG1 (TX_START_OFFSET + 0x0114)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0 (TX_START_OFFSET + 0x0118)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG1 (TX_START_OFFSET + 0x011C)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG0 (TX_START_OFFSET + 0x0120)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG1 (TX_START_OFFSET + 0x0124)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG0 (TX_START_OFFSET + 0x0128)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG1 (TX_START_OFFSET + 0x012C)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG0 (TX_START_OFFSET + 0x0130)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG1 (TX_START_OFFSET + 0x0134)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0 (TX_START_OFFSET + 0x0138)
|
||||
#define LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG1 (TX_START_OFFSET + 0x013C)
|
||||
#define LPASS_CDC_TX_ANC0_CLK_RESET_CTL (TX_START_OFFSET + 0x0200)
|
||||
#define LPASS_CDC_TX_ANC0_MODE_1_CTL (TX_START_OFFSET + 0x0204)
|
||||
#define LPASS_CDC_TX_ANC0_MODE_2_CTL (TX_START_OFFSET + 0x0208)
|
||||
#define LPASS_CDC_TX_ANC0_FF_SHIFT (TX_START_OFFSET + 0x020C)
|
||||
#define LPASS_CDC_TX_ANC0_FB_SHIFT (TX_START_OFFSET + 0x0210)
|
||||
#define LPASS_CDC_TX_ANC0_LPF_FF_A_CTL (TX_START_OFFSET + 0x0214)
|
||||
#define LPASS_CDC_TX_ANC0_LPF_FF_B_CTL (TX_START_OFFSET + 0x0218)
|
||||
#define LPASS_CDC_TX_ANC0_LPF_FB_CTL (TX_START_OFFSET + 0x021C)
|
||||
#define LPASS_CDC_TX_ANC0_SMLPF_CTL (TX_START_OFFSET + 0x0220)
|
||||
#define LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL (TX_START_OFFSET + 0x0224)
|
||||
#define LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL (TX_START_OFFSET + 0x0228)
|
||||
#define LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL (TX_START_OFFSET + 0x022C)
|
||||
#define LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL (TX_START_OFFSET + 0x0230)
|
||||
#define LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL (TX_START_OFFSET + 0x0234)
|
||||
#define LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL (TX_START_OFFSET + 0x0238)
|
||||
#define LPASS_CDC_TX_ANC0_FB_GAIN_CTL (TX_START_OFFSET + 0x023C)
|
||||
#define LPASS_CDC_TX0_TX_PATH_CTL (TX_START_OFFSET + 0x0400)
|
||||
#define LPASS_CDC_TX0_TX_PATH_CFG0 (TX_START_OFFSET + 0x0404)
|
||||
#define LPASS_CDC_TX0_TX_PATH_CFG1 (TX_START_OFFSET + 0x0408)
|
||||
#define LPASS_CDC_TX0_TX_VOL_CTL (TX_START_OFFSET + 0x040C)
|
||||
#define LPASS_CDC_TX0_TX_PATH_SEC0 (TX_START_OFFSET + 0x0410)
|
||||
#define LPASS_CDC_TX0_TX_PATH_SEC1 (TX_START_OFFSET + 0x0414)
|
||||
#define LPASS_CDC_TX0_TX_PATH_SEC2 (TX_START_OFFSET + 0x0418)
|
||||
#define LPASS_CDC_TX0_TX_PATH_SEC3 (TX_START_OFFSET + 0x041C)
|
||||
#define LPASS_CDC_TX0_TX_PATH_SEC4 (TX_START_OFFSET + 0x0420)
|
||||
#define LPASS_CDC_TX0_TX_PATH_SEC5 (TX_START_OFFSET + 0x0424)
|
||||
#define LPASS_CDC_TX0_TX_PATH_SEC6 (TX_START_OFFSET + 0x0428)
|
||||
#define LPASS_CDC_TX0_TX_PATH_SEC7 (TX_START_OFFSET + 0x042C)
|
||||
#define LPASS_CDC_TX1_TX_PATH_CTL (TX_START_OFFSET + 0x0480)
|
||||
#define LPASS_CDC_TX1_TX_PATH_CFG0 (TX_START_OFFSET + 0x0484)
|
||||
#define LPASS_CDC_TX1_TX_PATH_CFG1 (TX_START_OFFSET + 0x0488)
|
||||
#define LPASS_CDC_TX1_TX_VOL_CTL (TX_START_OFFSET + 0x048C)
|
||||
#define LPASS_CDC_TX1_TX_PATH_SEC0 (TX_START_OFFSET + 0x0490)
|
||||
#define LPASS_CDC_TX1_TX_PATH_SEC1 (TX_START_OFFSET + 0x0494)
|
||||
#define LPASS_CDC_TX1_TX_PATH_SEC2 (TX_START_OFFSET + 0x0498)
|
||||
#define LPASS_CDC_TX1_TX_PATH_SEC3 (TX_START_OFFSET + 0x049C)
|
||||
#define LPASS_CDC_TX1_TX_PATH_SEC4 (TX_START_OFFSET + 0x04A0)
|
||||
#define LPASS_CDC_TX1_TX_PATH_SEC5 (TX_START_OFFSET + 0x04A4)
|
||||
#define LPASS_CDC_TX1_TX_PATH_SEC6 (TX_START_OFFSET + 0x04A8)
|
||||
#define LPASS_CDC_TX2_TX_PATH_CTL (TX_START_OFFSET + 0x0500)
|
||||
#define LPASS_CDC_TX2_TX_PATH_CFG0 (TX_START_OFFSET + 0x0504)
|
||||
#define LPASS_CDC_TX2_TX_PATH_CFG1 (TX_START_OFFSET + 0x0508)
|
||||
#define LPASS_CDC_TX2_TX_VOL_CTL (TX_START_OFFSET + 0x050C)
|
||||
#define LPASS_CDC_TX2_TX_PATH_SEC0 (TX_START_OFFSET + 0x0510)
|
||||
#define LPASS_CDC_TX2_TX_PATH_SEC1 (TX_START_OFFSET + 0x0514)
|
||||
#define LPASS_CDC_TX2_TX_PATH_SEC2 (TX_START_OFFSET + 0x0518)
|
||||
#define LPASS_CDC_TX2_TX_PATH_SEC3 (TX_START_OFFSET + 0x051C)
|
||||
#define LPASS_CDC_TX2_TX_PATH_SEC4 (TX_START_OFFSET + 0x0520)
|
||||
#define LPASS_CDC_TX2_TX_PATH_SEC5 (TX_START_OFFSET + 0x0524)
|
||||
#define LPASS_CDC_TX2_TX_PATH_SEC6 (TX_START_OFFSET + 0x0528)
|
||||
#define LPASS_CDC_TX3_TX_PATH_CTL (TX_START_OFFSET + 0x0580)
|
||||
#define LPASS_CDC_TX3_TX_PATH_CFG0 (TX_START_OFFSET + 0x0584)
|
||||
#define LPASS_CDC_TX3_TX_PATH_CFG1 (TX_START_OFFSET + 0x0588)
|
||||
#define LPASS_CDC_TX3_TX_VOL_CTL (TX_START_OFFSET + 0x058C)
|
||||
#define LPASS_CDC_TX3_TX_PATH_SEC0 (TX_START_OFFSET + 0x0590)
|
||||
#define LPASS_CDC_TX3_TX_PATH_SEC1 (TX_START_OFFSET + 0x0594)
|
||||
#define LPASS_CDC_TX3_TX_PATH_SEC2 (TX_START_OFFSET + 0x0598)
|
||||
#define LPASS_CDC_TX3_TX_PATH_SEC3 (TX_START_OFFSET + 0x059C)
|
||||
#define LPASS_CDC_TX3_TX_PATH_SEC4 (TX_START_OFFSET + 0x05A0)
|
||||
#define LPASS_CDC_TX3_TX_PATH_SEC5 (TX_START_OFFSET + 0x05A4)
|
||||
#define LPASS_CDC_TX3_TX_PATH_SEC6 (TX_START_OFFSET + 0x05A8)
|
||||
#define LPASS_CDC_TX4_TX_PATH_CTL (TX_START_OFFSET + 0x0600)
|
||||
#define LPASS_CDC_TX4_TX_PATH_CFG0 (TX_START_OFFSET + 0x0604)
|
||||
#define LPASS_CDC_TX4_TX_PATH_CFG1 (TX_START_OFFSET + 0x0608)
|
||||
#define LPASS_CDC_TX4_TX_VOL_CTL (TX_START_OFFSET + 0x060C)
|
||||
#define LPASS_CDC_TX4_TX_PATH_SEC0 (TX_START_OFFSET + 0x0610)
|
||||
#define LPASS_CDC_TX4_TX_PATH_SEC1 (TX_START_OFFSET + 0x0614)
|
||||
#define LPASS_CDC_TX4_TX_PATH_SEC2 (TX_START_OFFSET + 0x0618)
|
||||
#define LPASS_CDC_TX4_TX_PATH_SEC3 (TX_START_OFFSET + 0x061C)
|
||||
#define LPASS_CDC_TX4_TX_PATH_SEC4 (TX_START_OFFSET + 0x0620)
|
||||
#define LPASS_CDC_TX4_TX_PATH_SEC5 (TX_START_OFFSET + 0x0624)
|
||||
#define LPASS_CDC_TX4_TX_PATH_SEC6 (TX_START_OFFSET + 0x0628)
|
||||
#define LPASS_CDC_TX5_TX_PATH_CTL (TX_START_OFFSET + 0x0680)
|
||||
#define LPASS_CDC_TX5_TX_PATH_CFG0 (TX_START_OFFSET + 0x0684)
|
||||
#define LPASS_CDC_TX5_TX_PATH_CFG1 (TX_START_OFFSET + 0x0688)
|
||||
#define LPASS_CDC_TX5_TX_VOL_CTL (TX_START_OFFSET + 0x068C)
|
||||
#define LPASS_CDC_TX5_TX_PATH_SEC0 (TX_START_OFFSET + 0x0690)
|
||||
#define LPASS_CDC_TX5_TX_PATH_SEC1 (TX_START_OFFSET + 0x0694)
|
||||
#define LPASS_CDC_TX5_TX_PATH_SEC2 (TX_START_OFFSET + 0x0698)
|
||||
#define LPASS_CDC_TX5_TX_PATH_SEC3 (TX_START_OFFSET + 0x069C)
|
||||
#define LPASS_CDC_TX5_TX_PATH_SEC4 (TX_START_OFFSET + 0x06A0)
|
||||
#define LPASS_CDC_TX5_TX_PATH_SEC5 (TX_START_OFFSET + 0x06A4)
|
||||
#define LPASS_CDC_TX5_TX_PATH_SEC6 (TX_START_OFFSET + 0x06A8)
|
||||
#define LPASS_CDC_TX6_TX_PATH_CTL (TX_START_OFFSET + 0x0700)
|
||||
#define LPASS_CDC_TX6_TX_PATH_CFG0 (TX_START_OFFSET + 0x0704)
|
||||
#define LPASS_CDC_TX6_TX_PATH_CFG1 (TX_START_OFFSET + 0x0708)
|
||||
#define LPASS_CDC_TX6_TX_VOL_CTL (TX_START_OFFSET + 0x070C)
|
||||
#define LPASS_CDC_TX6_TX_PATH_SEC0 (TX_START_OFFSET + 0x0710)
|
||||
#define LPASS_CDC_TX6_TX_PATH_SEC1 (TX_START_OFFSET + 0x0714)
|
||||
#define LPASS_CDC_TX6_TX_PATH_SEC2 (TX_START_OFFSET + 0x0718)
|
||||
#define LPASS_CDC_TX6_TX_PATH_SEC3 (TX_START_OFFSET + 0x071C)
|
||||
#define LPASS_CDC_TX6_TX_PATH_SEC4 (TX_START_OFFSET + 0x0720)
|
||||
#define LPASS_CDC_TX6_TX_PATH_SEC5 (TX_START_OFFSET + 0x0724)
|
||||
#define LPASS_CDC_TX6_TX_PATH_SEC6 (TX_START_OFFSET + 0x0728)
|
||||
#define LPASS_CDC_TX7_TX_PATH_CTL (TX_START_OFFSET + 0x0780)
|
||||
#define LPASS_CDC_TX7_TX_PATH_CFG0 (TX_START_OFFSET + 0x0784)
|
||||
#define LPASS_CDC_TX7_TX_PATH_CFG1 (TX_START_OFFSET + 0x0788)
|
||||
#define LPASS_CDC_TX7_TX_VOL_CTL (TX_START_OFFSET + 0x078C)
|
||||
#define LPASS_CDC_TX7_TX_PATH_SEC0 (TX_START_OFFSET + 0x0790)
|
||||
#define LPASS_CDC_TX7_TX_PATH_SEC1 (TX_START_OFFSET + 0x0794)
|
||||
#define LPASS_CDC_TX7_TX_PATH_SEC2 (TX_START_OFFSET + 0x0798)
|
||||
#define LPASS_CDC_TX7_TX_PATH_SEC3 (TX_START_OFFSET + 0x079C)
|
||||
#define LPASS_CDC_TX7_TX_PATH_SEC4 (TX_START_OFFSET + 0x07A0)
|
||||
#define LPASS_CDC_TX7_TX_PATH_SEC5 (TX_START_OFFSET + 0x07A4)
|
||||
#define LPASS_CDC_TX7_TX_PATH_SEC6 (TX_START_OFFSET + 0x07A8)
|
||||
#define TX_MAX_OFFSET (TX_START_OFFSET + 0x07A8)
|
||||
|
||||
#define LPASS_CDC_TX_MACRO_MAX 0x1EB /* 7A8/4 = 1EA + 1 */
|
||||
|
||||
#define RX_START_OFFSET 0x1000
|
||||
#define LPASS_CDC_RX_TOP_TOP_CFG0 (RX_START_OFFSET + 0x0000)
|
||||
#define LPASS_CDC_RX_TOP_SWR_CTRL (RX_START_OFFSET + 0x0008)
|
||||
#define LPASS_CDC_RX_TOP_DEBUG (RX_START_OFFSET + 0x000C)
|
||||
#define LPASS_CDC_RX_TOP_DEBUG_BUS (RX_START_OFFSET + 0x0010)
|
||||
#define LPASS_CDC_RX_TOP_DEBUG_EN0 (RX_START_OFFSET + 0x0014)
|
||||
#define LPASS_CDC_RX_TOP_DEBUG_EN1 (RX_START_OFFSET + 0x0018)
|
||||
#define LPASS_CDC_RX_TOP_DEBUG_EN2 (RX_START_OFFSET + 0x001C)
|
||||
#define LPASS_CDC_RX_TOP_HPHL_COMP_WR_LSB (RX_START_OFFSET + 0x0020)
|
||||
#define LPASS_CDC_RX_TOP_HPHL_COMP_WR_MSB (RX_START_OFFSET + 0x0024)
|
||||
#define LPASS_CDC_RX_TOP_HPHL_COMP_LUT (RX_START_OFFSET + 0x0028)
|
||||
#define LPASS_CDC_RX_TOP_HPHL_COMP_RD_LSB (RX_START_OFFSET + 0x002C)
|
||||
#define LPASS_CDC_RX_TOP_HPHL_COMP_RD_MSB (RX_START_OFFSET + 0x0030)
|
||||
#define LPASS_CDC_RX_TOP_HPHR_COMP_WR_LSB (RX_START_OFFSET + 0x0034)
|
||||
#define LPASS_CDC_RX_TOP_HPHR_COMP_WR_MSB (RX_START_OFFSET + 0x0038)
|
||||
#define LPASS_CDC_RX_TOP_HPHR_COMP_LUT (RX_START_OFFSET + 0x003C)
|
||||
#define LPASS_CDC_RX_TOP_HPHR_COMP_RD_LSB (RX_START_OFFSET + 0x0040)
|
||||
#define LPASS_CDC_RX_TOP_HPHR_COMP_RD_MSB (RX_START_OFFSET + 0x0044)
|
||||
#define LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG0 (RX_START_OFFSET + 0x0070)
|
||||
#define LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG1 (RX_START_OFFSET + 0x0074)
|
||||
#define LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG2 (RX_START_OFFSET + 0x0078)
|
||||
#define LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3 (RX_START_OFFSET + 0x007C)
|
||||
#define LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG0 (RX_START_OFFSET + 0x0080)
|
||||
#define LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG1 (RX_START_OFFSET + 0x0084)
|
||||
#define LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG2 (RX_START_OFFSET + 0x0088)
|
||||
#define LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3 (RX_START_OFFSET + 0x008C)
|
||||
#define LPASS_CDC_RX_TOP_RX_I2S_CTL (RX_START_OFFSET + 0x0090)
|
||||
#define LPASS_CDC_RX_TOP_TX_I2S2_CTL (RX_START_OFFSET + 0x0094)
|
||||
#define LPASS_CDC_RX_TOP_I2S_CLK (RX_START_OFFSET + 0x0098)
|
||||
#define LPASS_CDC_RX_TOP_I2S_RESET (RX_START_OFFSET + 0x009C)
|
||||
#define LPASS_CDC_RX_TOP_I2S_MUX (RX_START_OFFSET + 0x00A0)
|
||||
#define LPASS_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL (RX_START_OFFSET + 0x0100)
|
||||
#define LPASS_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL \
|
||||
(RX_START_OFFSET + 0x0104)
|
||||
#define LPASS_CDC_RX_CLK_RST_CTRL_SWR_CONTROL (RX_START_OFFSET + 0x0108)
|
||||
#define LPASS_CDC_RX_CLK_RST_CTRL_DSD_CONTROL (RX_START_OFFSET + 0x010C)
|
||||
#define LPASS_CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL \
|
||||
(RX_START_OFFSET + 0x0110)
|
||||
#define LPASS_CDC_RX_SOFTCLIP_CRC (RX_START_OFFSET + 0x0140)
|
||||
#define LPASS_CDC_RX_SOFTCLIP_SOFTCLIP_CTRL (RX_START_OFFSET + 0x0144)
|
||||
#define LPASS_CDC_RX_INP_MUX_RX_INT0_CFG0 (RX_START_OFFSET + 0x0180)
|
||||
#define LPASS_CDC_RX_INP_MUX_RX_INT0_CFG1 (RX_START_OFFSET + 0x0184)
|
||||
#define LPASS_CDC_RX_INP_MUX_RX_INT1_CFG0 (RX_START_OFFSET + 0x0188)
|
||||
#define LPASS_CDC_RX_INP_MUX_RX_INT1_CFG1 (RX_START_OFFSET + 0x018C)
|
||||
#define LPASS_CDC_RX_INP_MUX_RX_INT2_CFG0 (RX_START_OFFSET + 0x0190)
|
||||
#define LPASS_CDC_RX_INP_MUX_RX_INT2_CFG1 (RX_START_OFFSET + 0x0194)
|
||||
#define LPASS_CDC_RX_INP_MUX_RX_MIX_CFG4 (RX_START_OFFSET + 0x0198)
|
||||
#define LPASS_CDC_RX_INP_MUX_RX_MIX_CFG5 (RX_START_OFFSET + 0x019C)
|
||||
#define LPASS_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 (RX_START_OFFSET + 0x01A0)
|
||||
#define LPASS_CDC_RX_CLSH_CRC (RX_START_OFFSET + 0x0200)
|
||||
#define LPASS_CDC_RX_CLSH_DLY_CTRL (RX_START_OFFSET + 0x0204)
|
||||
#define LPASS_CDC_RX_CLSH_DECAY_CTRL (RX_START_OFFSET + 0x0208)
|
||||
#define LPASS_CDC_RX_CLSH_HPH_V_PA (RX_START_OFFSET + 0x020C)
|
||||
#define LPASS_CDC_RX_CLSH_EAR_V_PA (RX_START_OFFSET + 0x0210)
|
||||
#define LPASS_CDC_RX_CLSH_HPH_V_HD (RX_START_OFFSET + 0x0214)
|
||||
#define LPASS_CDC_RX_CLSH_EAR_V_HD (RX_START_OFFSET + 0x0218)
|
||||
#define LPASS_CDC_RX_CLSH_K1_MSB (RX_START_OFFSET + 0x021C)
|
||||
#define LPASS_CDC_RX_CLSH_K1_LSB (RX_START_OFFSET + 0x0220)
|
||||
#define LPASS_CDC_RX_CLSH_K2_MSB (RX_START_OFFSET + 0x0224)
|
||||
#define LPASS_CDC_RX_CLSH_K2_LSB (RX_START_OFFSET + 0x0228)
|
||||
#define LPASS_CDC_RX_CLSH_IDLE_CTRL (RX_START_OFFSET + 0x022C)
|
||||
#define LPASS_CDC_RX_CLSH_IDLE_HPH (RX_START_OFFSET + 0x0230)
|
||||
#define LPASS_CDC_RX_CLSH_IDLE_EAR (RX_START_OFFSET + 0x0234)
|
||||
#define LPASS_CDC_RX_CLSH_TEST0 (RX_START_OFFSET + 0x0238)
|
||||
#define LPASS_CDC_RX_CLSH_TEST1 (RX_START_OFFSET + 0x023C)
|
||||
#define LPASS_CDC_RX_CLSH_OVR_VREF (RX_START_OFFSET + 0x0240)
|
||||
#define LPASS_CDC_RX_CLSH_CLSG_CTL (RX_START_OFFSET + 0x0244)
|
||||
#define LPASS_CDC_RX_CLSH_CLSG_CFG1 (RX_START_OFFSET + 0x0248)
|
||||
#define LPASS_CDC_RX_CLSH_CLSG_CFG2 (RX_START_OFFSET + 0x024C)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_PATH_CTL (RX_START_OFFSET + 0x0280)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_CFG (RX_START_OFFSET + 0x0284)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_ADC_CAL1 (RX_START_OFFSET + 0x0288)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_ADC_CAL2 (RX_START_OFFSET + 0x028C)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_ADC_CAL3 (RX_START_OFFSET + 0x0290)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_PK_EST1 (RX_START_OFFSET + 0x0294)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_PK_EST2 (RX_START_OFFSET + 0x0298)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_PK_EST3 (RX_START_OFFSET + 0x029C)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_RF_PROC1 (RX_START_OFFSET + 0x02A0)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_RF_PROC2 (RX_START_OFFSET + 0x02A4)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_TAC1 (RX_START_OFFSET + 0x02A8)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_TAC2 (RX_START_OFFSET + 0x02AC)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_TAC3 (RX_START_OFFSET + 0x02B0)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_TAC4 (RX_START_OFFSET + 0x02B4)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_GAIN_UPD1 (RX_START_OFFSET + 0x02B8)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_GAIN_UPD2 (RX_START_OFFSET + 0x02BC)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_GAIN_UPD3 (RX_START_OFFSET + 0x02C0)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_GAIN_UPD4 (RX_START_OFFSET + 0x02C4)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_GAIN_UPD5 (RX_START_OFFSET + 0x02C8)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_DEBUG1 (RX_START_OFFSET + 0x02CC)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_GAIN_UPD_MON (RX_START_OFFSET + 0x02D0)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_GAIN_MON_VAL (RX_START_OFFSET + 0x02D4)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_BAN (RX_START_OFFSET + 0x02D8)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD1 (RX_START_OFFSET + 0x02DC)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD2 (RX_START_OFFSET + 0x02E0)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD3 (RX_START_OFFSET + 0x02E4)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD4 (RX_START_OFFSET + 0x02E8)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD5 (RX_START_OFFSET + 0x02EC)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD6 (RX_START_OFFSET + 0x02F0)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD7 (RX_START_OFFSET + 0x02F4)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD8 (RX_START_OFFSET + 0x02F8)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD9 (RX_START_OFFSET + 0x02FC)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_ATTN1 (RX_START_OFFSET + 0x0300)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_ATTN2 (RX_START_OFFSET + 0x0304)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_ATTN3 (RX_START_OFFSET + 0x0308)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1 (RX_START_OFFSET + 0x030C)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2 (RX_START_OFFSET + 0x0310)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1 (RX_START_OFFSET + 0x0314)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2 (RX_START_OFFSET + 0x0318)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3 (RX_START_OFFSET + 0x031C)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4 (RX_START_OFFSET + 0x0320)
|
||||
#define LPASS_CDC_RX_BCL_VBAT_DECODE_ST (RX_START_OFFSET + 0x0324)
|
||||
#define LPASS_CDC_RX_INTR_CTRL_CFG (RX_START_OFFSET + 0x0340)
|
||||
#define LPASS_CDC_RX_INTR_CTRL_CLR_COMMIT (RX_START_OFFSET + 0x0344)
|
||||
#define LPASS_CDC_RX_INTR_CTRL_PIN1_MASK0 (RX_START_OFFSET + 0x0360)
|
||||
#define LPASS_CDC_RX_INTR_CTRL_PIN1_STATUS0 (RX_START_OFFSET + 0x0368)
|
||||
#define LPASS_CDC_RX_INTR_CTRL_PIN1_CLEAR0 (RX_START_OFFSET + 0x0370)
|
||||
#define LPASS_CDC_RX_INTR_CTRL_PIN2_MASK0 (RX_START_OFFSET + 0x0380)
|
||||
#define LPASS_CDC_RX_INTR_CTRL_PIN2_STATUS0 (RX_START_OFFSET + 0x0388)
|
||||
#define LPASS_CDC_RX_INTR_CTRL_PIN2_CLEAR0 (RX_START_OFFSET + 0x0390)
|
||||
#define LPASS_CDC_RX_INTR_CTRL_LEVEL0 (RX_START_OFFSET + 0x03C0)
|
||||
#define LPASS_CDC_RX_INTR_CTRL_BYPASS0 (RX_START_OFFSET + 0x03C8)
|
||||
#define LPASS_CDC_RX_INTR_CTRL_SET0 (RX_START_OFFSET + 0x03D0)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_CTL (RX_START_OFFSET + 0x0400)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_CFG0 (RX_START_OFFSET + 0x0404)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_CFG1 (RX_START_OFFSET + 0x0408)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_CFG2 (RX_START_OFFSET + 0x040C)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_CFG3 (RX_START_OFFSET + 0x0410)
|
||||
#define LPASS_CDC_RX_RX0_RX_VOL_CTL (RX_START_OFFSET + 0x0414)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0418)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x041C)
|
||||
#define LPASS_CDC_RX_RX0_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x0420)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_SEC1 (RX_START_OFFSET + 0x0424)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_SEC2 (RX_START_OFFSET + 0x0428)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_SEC3 (RX_START_OFFSET + 0x042C)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_SEC4 (RX_START_OFFSET + 0x0430)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_SEC7 (RX_START_OFFSET + 0x0434)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x0438)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x043C)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x0440)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA1 (RX_START_OFFSET + 0x0444)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA2 (RX_START_OFFSET + 0x0448)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA3 (RX_START_OFFSET + 0x044C)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x0450)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x0454)
|
||||
#define LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x0458)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_CTL (RX_START_OFFSET + 0x0480)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_CFG0 (RX_START_OFFSET + 0x0484)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_CFG1 (RX_START_OFFSET + 0x0488)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_CFG2 (RX_START_OFFSET + 0x048C)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_CFG3 (RX_START_OFFSET + 0x0490)
|
||||
#define LPASS_CDC_RX_RX1_RX_VOL_CTL (RX_START_OFFSET + 0x0494)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0498)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x049C)
|
||||
#define LPASS_CDC_RX_RX1_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x04A0)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_SEC1 (RX_START_OFFSET + 0x04A4)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_SEC2 (RX_START_OFFSET + 0x04A8)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_SEC3 (RX_START_OFFSET + 0x04AC)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_SEC4 (RX_START_OFFSET + 0x04B0)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_SEC7 (RX_START_OFFSET + 0x04B4)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x04B8)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x04BC)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x04C0)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA1 (RX_START_OFFSET + 0x04C4)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA2 (RX_START_OFFSET + 0x04C8)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA3 (RX_START_OFFSET + 0x04CC)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x04D0)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x04D4)
|
||||
#define LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x04D8)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_CTL (RX_START_OFFSET + 0x0500)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_CFG0 (RX_START_OFFSET + 0x0504)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_CFG1 (RX_START_OFFSET + 0x0508)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_CFG2 (RX_START_OFFSET + 0x050C)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_CFG3 (RX_START_OFFSET + 0x0510)
|
||||
#define LPASS_CDC_RX_RX2_RX_VOL_CTL (RX_START_OFFSET + 0x0514)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0518)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x051C)
|
||||
#define LPASS_CDC_RX_RX2_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x0520)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_SEC0 (RX_START_OFFSET + 0x0524)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_SEC1 (RX_START_OFFSET + 0x0528)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_SEC2 (RX_START_OFFSET + 0x052C)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_SEC3 (RX_START_OFFSET + 0x0530)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_SEC4 (RX_START_OFFSET + 0x0534)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_SEC5 (RX_START_OFFSET + 0x0538)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_SEC6 (RX_START_OFFSET + 0x053C)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_SEC7 (RX_START_OFFSET + 0x0540)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x0544)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x0548)
|
||||
#define LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x054C)
|
||||
#define LPASS_CDC_RX_IDLE_DETECT_PATH_CTL (RX_START_OFFSET + 0x0780)
|
||||
#define LPASS_CDC_RX_IDLE_DETECT_CFG0 (RX_START_OFFSET + 0x0784)
|
||||
#define LPASS_CDC_RX_IDLE_DETECT_CFG1 (RX_START_OFFSET + 0x0788)
|
||||
#define LPASS_CDC_RX_IDLE_DETECT_CFG2 (RX_START_OFFSET + 0x078C)
|
||||
#define LPASS_CDC_RX_IDLE_DETECT_CFG3 (RX_START_OFFSET + 0x0790)
|
||||
#define LPASS_CDC_RX_COMPANDER0_CTL0 (RX_START_OFFSET + 0x0800)
|
||||
#define LPASS_CDC_RX_COMPANDER0_CTL1 (RX_START_OFFSET + 0x0804)
|
||||
#define LPASS_CDC_RX_COMPANDER0_CTL2 (RX_START_OFFSET + 0x0808)
|
||||
#define LPASS_CDC_RX_COMPANDER0_CTL3 (RX_START_OFFSET + 0x080C)
|
||||
#define LPASS_CDC_RX_COMPANDER0_CTL4 (RX_START_OFFSET + 0x0810)
|
||||
#define LPASS_CDC_RX_COMPANDER0_CTL5 (RX_START_OFFSET + 0x0814)
|
||||
#define LPASS_CDC_RX_COMPANDER0_CTL6 (RX_START_OFFSET + 0x0818)
|
||||
#define LPASS_CDC_RX_COMPANDER0_CTL7 (RX_START_OFFSET + 0x081C)
|
||||
#define LPASS_CDC_RX_COMPANDER1_CTL0 (RX_START_OFFSET + 0x0840)
|
||||
#define LPASS_CDC_RX_COMPANDER1_CTL1 (RX_START_OFFSET + 0x0844)
|
||||
#define LPASS_CDC_RX_COMPANDER1_CTL2 (RX_START_OFFSET + 0x0848)
|
||||
#define LPASS_CDC_RX_COMPANDER1_CTL3 (RX_START_OFFSET + 0x084C)
|
||||
#define LPASS_CDC_RX_COMPANDER1_CTL4 (RX_START_OFFSET + 0x0850)
|
||||
#define LPASS_CDC_RX_COMPANDER1_CTL5 (RX_START_OFFSET + 0x0854)
|
||||
#define LPASS_CDC_RX_COMPANDER1_CTL6 (RX_START_OFFSET + 0x0858)
|
||||
#define LPASS_CDC_RX_COMPANDER1_CTL7 (RX_START_OFFSET + 0x085C)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL \
|
||||
(RX_START_OFFSET + 0x0A00)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL \
|
||||
(RX_START_OFFSET + 0x0A04)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL \
|
||||
(RX_START_OFFSET + 0x0A08)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL \
|
||||
(RX_START_OFFSET + 0x0A0C)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL \
|
||||
(RX_START_OFFSET + 0x0A10)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL \
|
||||
(RX_START_OFFSET + 0x0A14)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL \
|
||||
(RX_START_OFFSET + 0x0A18)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL \
|
||||
(RX_START_OFFSET + 0x0A1C)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL \
|
||||
(RX_START_OFFSET + 0x0A20)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_CTL (RX_START_OFFSET + 0x0A24)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL \
|
||||
(RX_START_OFFSET + 0x0A28)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL \
|
||||
(RX_START_OFFSET + 0x0A2C)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL \
|
||||
(RX_START_OFFSET + 0x0A30)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL \
|
||||
(RX_START_OFFSET + 0x0A80)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL \
|
||||
(RX_START_OFFSET + 0x0A84)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL \
|
||||
(RX_START_OFFSET + 0x0A88)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL \
|
||||
(RX_START_OFFSET + 0x0A8C)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL \
|
||||
(RX_START_OFFSET + 0x0A90)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL \
|
||||
(RX_START_OFFSET + 0x0A94)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL \
|
||||
(RX_START_OFFSET + 0x0A98)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL \
|
||||
(RX_START_OFFSET + 0x0A9C)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL \
|
||||
(RX_START_OFFSET + 0x0AA0)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_CTL (RX_START_OFFSET + 0x0AA4)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL \
|
||||
(RX_START_OFFSET + 0x0AA8)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL \
|
||||
(RX_START_OFFSET + 0x0AAC)
|
||||
#define LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL \
|
||||
(RX_START_OFFSET + 0x0AB0)
|
||||
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 (RX_START_OFFSET + 0x0B00)
|
||||
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 (RX_START_OFFSET + 0x0B04)
|
||||
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 (RX_START_OFFSET + 0x0B08)
|
||||
#define LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 (RX_START_OFFSET + 0x0B0C)
|
||||
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 (RX_START_OFFSET + 0x0B10)
|
||||
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 (RX_START_OFFSET + 0x0B14)
|
||||
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 (RX_START_OFFSET + 0x0B18)
|
||||
#define LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 (RX_START_OFFSET + 0x0B1C)
|
||||
#define LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL \
|
||||
(RX_START_OFFSET + 0x0B40)
|
||||
#define LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 \
|
||||
(RX_START_OFFSET + 0x0B44)
|
||||
#define LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL \
|
||||
(RX_START_OFFSET + 0x0B50)
|
||||
#define LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 \
|
||||
(RX_START_OFFSET + 0x0B54)
|
||||
#define LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL \
|
||||
(RX_START_OFFSET + 0x0C00)
|
||||
#define LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C04)
|
||||
#define LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL \
|
||||
(RX_START_OFFSET + 0x0C40)
|
||||
#define LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C44)
|
||||
#define LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL \
|
||||
(RX_START_OFFSET + 0x0C80)
|
||||
#define LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C84)
|
||||
#define LPASS_CDC_RX_EC_ASRC0_CLK_RST_CTL (RX_START_OFFSET + 0x0D00)
|
||||
#define LPASS_CDC_RX_EC_ASRC0_CTL0 (RX_START_OFFSET + 0x0D04)
|
||||
#define LPASS_CDC_RX_EC_ASRC0_CTL1 (RX_START_OFFSET + 0x0D08)
|
||||
#define LPASS_CDC_RX_EC_ASRC0_FIFO_CTL (RX_START_OFFSET + 0x0D0C)
|
||||
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB \
|
||||
(RX_START_OFFSET + 0x0D10)
|
||||
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB \
|
||||
(RX_START_OFFSET + 0x0D14)
|
||||
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB \
|
||||
(RX_START_OFFSET + 0x0D18)
|
||||
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB \
|
||||
(RX_START_OFFSET + 0x0D1C)
|
||||
#define LPASS_CDC_RX_EC_ASRC0_STATUS_FIFO (RX_START_OFFSET + 0x0D20)
|
||||
#define LPASS_CDC_RX_EC_ASRC1_CLK_RST_CTL (RX_START_OFFSET + 0x0D40)
|
||||
#define LPASS_CDC_RX_EC_ASRC1_CTL0 (RX_START_OFFSET + 0x0D44)
|
||||
#define LPASS_CDC_RX_EC_ASRC1_CTL1 (RX_START_OFFSET + 0x0D48)
|
||||
#define LPASS_CDC_RX_EC_ASRC1_FIFO_CTL (RX_START_OFFSET + 0x0D4C)
|
||||
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB \
|
||||
(RX_START_OFFSET + 0x0D50)
|
||||
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB \
|
||||
(RX_START_OFFSET + 0x0D54)
|
||||
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB \
|
||||
(RX_START_OFFSET + 0x0D58)
|
||||
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB \
|
||||
(RX_START_OFFSET + 0x0D5C)
|
||||
#define LPASS_CDC_RX_EC_ASRC1_STATUS_FIFO (RX_START_OFFSET + 0x0D60)
|
||||
#define LPASS_CDC_RX_EC_ASRC2_CLK_RST_CTL (RX_START_OFFSET + 0x0D80)
|
||||
#define LPASS_CDC_RX_EC_ASRC2_CTL0 (RX_START_OFFSET + 0x0D84)
|
||||
#define LPASS_CDC_RX_EC_ASRC2_CTL1 (RX_START_OFFSET + 0x0D88)
|
||||
#define LPASS_CDC_RX_EC_ASRC2_FIFO_CTL (RX_START_OFFSET + 0x0D8C)
|
||||
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB \
|
||||
(RX_START_OFFSET + 0x0D90)
|
||||
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB \
|
||||
(RX_START_OFFSET + 0x0D94)
|
||||
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB \
|
||||
(RX_START_OFFSET + 0x0D98)
|
||||
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB \
|
||||
(RX_START_OFFSET + 0x0D9C)
|
||||
#define LPASS_CDC_RX_EC_ASRC2_STATUS_FIFO (RX_START_OFFSET + 0x0DA0)
|
||||
#define LPASS_CDC_RX_DSD0_PATH_CTL (RX_START_OFFSET + 0x0F00)
|
||||
#define LPASS_CDC_RX_DSD0_CFG0 (RX_START_OFFSET + 0x0F04)
|
||||
#define LPASS_CDC_RX_DSD0_CFG1 (RX_START_OFFSET + 0x0F08)
|
||||
#define LPASS_CDC_RX_DSD0_CFG2 (RX_START_OFFSET + 0x0F0C)
|
||||
#define LPASS_CDC_RX_DSD1_PATH_CTL (RX_START_OFFSET + 0x0F80)
|
||||
#define LPASS_CDC_RX_DSD1_CFG0 (RX_START_OFFSET + 0x0F84)
|
||||
#define LPASS_CDC_RX_DSD1_CFG1 (RX_START_OFFSET + 0x0F88)
|
||||
#define LPASS_CDC_RX_DSD1_CFG2 (RX_START_OFFSET + 0x0F8C)
|
||||
#define RX_MAX_OFFSET (RX_START_OFFSET + 0x0F8C)
|
||||
|
||||
#define LPASS_CDC_RX_MACRO_MAX 0x3E4 /* F8C/4 = 3E3 + 1 */
|
||||
|
||||
/* WSA - macro#2 */
|
||||
#define WSA_START_OFFSET 0x2000
|
||||
#define LPASS_CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL \
|
||||
(WSA_START_OFFSET + 0x0000)
|
||||
#define LPASS_CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL \
|
||||
(WSA_START_OFFSET + 0x0004)
|
||||
#define LPASS_CDC_WSA_CLK_RST_CTRL_SWR_CONTROL (WSA_START_OFFSET + 0x0008)
|
||||
#define LPASS_CDC_WSA_TOP_TOP_CFG0 (WSA_START_OFFSET + 0x0080)
|
||||
#define LPASS_CDC_WSA_TOP_TOP_CFG1 (WSA_START_OFFSET + 0x0084)
|
||||
#define LPASS_CDC_WSA_TOP_FREQ_MCLK (WSA_START_OFFSET + 0x0088)
|
||||
#define LPASS_CDC_WSA_TOP_DEBUG_BUS_SEL (WSA_START_OFFSET + 0x008C)
|
||||
#define LPASS_CDC_WSA_TOP_DEBUG_EN0 (WSA_START_OFFSET + 0x0090)
|
||||
#define LPASS_CDC_WSA_TOP_DEBUG_EN1 (WSA_START_OFFSET + 0x0094)
|
||||
#define LPASS_CDC_WSA_TOP_DEBUG_DSM_LB (WSA_START_OFFSET + 0x0098)
|
||||
#define LPASS_CDC_WSA_TOP_RX_I2S_CTL (WSA_START_OFFSET + 0x009C)
|
||||
#define LPASS_CDC_WSA_TOP_TX_I2S_CTL (WSA_START_OFFSET + 0x00A0)
|
||||
#define LPASS_CDC_WSA_TOP_I2S_CLK (WSA_START_OFFSET + 0x00A4)
|
||||
#define LPASS_CDC_WSA_TOP_I2S_RESET (WSA_START_OFFSET + 0x00A8)
|
||||
#define LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 (WSA_START_OFFSET + 0x0100)
|
||||
#define LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 (WSA_START_OFFSET + 0x0104)
|
||||
#define LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0 (WSA_START_OFFSET + 0x0108)
|
||||
#define LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1 (WSA_START_OFFSET + 0x010C)
|
||||
#define LPASS_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0 (WSA_START_OFFSET + 0x0110)
|
||||
#define LPASS_CDC_WSA_RX_INP_MUX_RX_EC_CFG0 (WSA_START_OFFSET + 0x0114)
|
||||
#define LPASS_CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0 (WSA_START_OFFSET + 0x0118)
|
||||
/* VBAT registers */
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_PATH_CTL (WSA_START_OFFSET + 0x0180)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_CFG (WSA_START_OFFSET + 0x0184)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL1 (WSA_START_OFFSET + 0x0188)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL2 (WSA_START_OFFSET + 0x018C)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL3 (WSA_START_OFFSET + 0x0190)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_PK_EST1 (WSA_START_OFFSET + 0x0194)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_PK_EST2 (WSA_START_OFFSET + 0x0198)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_PK_EST3 (WSA_START_OFFSET + 0x019C)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_RF_PROC1 (WSA_START_OFFSET + 0x01A0)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_RF_PROC2 (WSA_START_OFFSET + 0x01A4)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC1 (WSA_START_OFFSET + 0x01A8)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC2 (WSA_START_OFFSET + 0x01AC)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC3 (WSA_START_OFFSET + 0x01B0)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC4 (WSA_START_OFFSET + 0x01B4)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD1 (WSA_START_OFFSET + 0x01B8)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD2 (WSA_START_OFFSET + 0x01BC)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD3 (WSA_START_OFFSET + 0x01C0)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD4 (WSA_START_OFFSET + 0x01C4)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD5 (WSA_START_OFFSET + 0x01C8)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DEBUG1 (WSA_START_OFFSET + 0x01CC)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD_MON \
|
||||
(WSA_START_OFFSET + 0x01D0)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL \
|
||||
(WSA_START_OFFSET + 0x01D4)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BAN (WSA_START_OFFSET + 0x01D8)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD1 \
|
||||
(WSA_START_OFFSET + 0x01DC)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD2 \
|
||||
(WSA_START_OFFSET + 0x01E0)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD3 \
|
||||
(WSA_START_OFFSET + 0x01E4)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD4 \
|
||||
(WSA_START_OFFSET + 0x01E8)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD5 \
|
||||
(WSA_START_OFFSET + 0x01EC)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD6 \
|
||||
(WSA_START_OFFSET + 0x01F0)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD7 \
|
||||
(WSA_START_OFFSET + 0x01F4)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD8 \
|
||||
(WSA_START_OFFSET + 0x01F8)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD9 \
|
||||
(WSA_START_OFFSET + 0x01FC)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1 (WSA_START_OFFSET + 0x0200)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2 (WSA_START_OFFSET + 0x0204)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3 (WSA_START_OFFSET + 0x0208)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1 \
|
||||
(WSA_START_OFFSET + 0x020C)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2 \
|
||||
(WSA_START_OFFSET + 0x0210)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1 \
|
||||
(WSA_START_OFFSET + 0x0214)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2 \
|
||||
(WSA_START_OFFSET + 0x0218)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3 \
|
||||
(WSA_START_OFFSET + 0x021C)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4 \
|
||||
(WSA_START_OFFSET + 0x0220)
|
||||
#define LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST (WSA_START_OFFSET + 0x0224)
|
||||
#define LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x0244)
|
||||
#define LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (WSA_START_OFFSET + 0x0248)
|
||||
#define LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x0264)
|
||||
#define LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 (WSA_START_OFFSET + 0x0268)
|
||||
#define LPASS_CDC_WSA_TX2_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x0284)
|
||||
#define LPASS_CDC_WSA_TX2_SPKR_PROT_PATH_CFG0 (WSA_START_OFFSET + 0x0288)
|
||||
#define LPASS_CDC_WSA_TX3_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x02A4)
|
||||
#define LPASS_CDC_WSA_TX3_SPKR_PROT_PATH_CFG0 (WSA_START_OFFSET + 0x02A8)
|
||||
#define LPASS_CDC_WSA_INTR_CTRL_CFG (WSA_START_OFFSET + 0x0340)
|
||||
#define LPASS_CDC_WSA_INTR_CTRL_CLR_COMMIT (WSA_START_OFFSET + 0x0344)
|
||||
#define LPASS_CDC_WSA_INTR_CTRL_PIN1_MASK0 (WSA_START_OFFSET + 0x0360)
|
||||
#define LPASS_CDC_WSA_INTR_CTRL_PIN1_STATUS0 (WSA_START_OFFSET + 0x0368)
|
||||
#define LPASS_CDC_WSA_INTR_CTRL_PIN1_CLEAR0 (WSA_START_OFFSET + 0x0370)
|
||||
#define LPASS_CDC_WSA_INTR_CTRL_PIN2_MASK0 (WSA_START_OFFSET + 0x0380)
|
||||
#define LPASS_CDC_WSA_INTR_CTRL_PIN2_STATUS0 (WSA_START_OFFSET + 0x0388)
|
||||
#define LPASS_CDC_WSA_INTR_CTRL_PIN2_CLEAR0 (WSA_START_OFFSET + 0x0390)
|
||||
#define LPASS_CDC_WSA_INTR_CTRL_LEVEL0 (WSA_START_OFFSET + 0x03C0)
|
||||
#define LPASS_CDC_WSA_INTR_CTRL_BYPASS0 (WSA_START_OFFSET + 0x03C8)
|
||||
#define LPASS_CDC_WSA_INTR_CTRL_SET0 (WSA_START_OFFSET + 0x03D0)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_CTL (WSA_START_OFFSET + 0x0400)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_CFG0 (WSA_START_OFFSET + 0x0404)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_CFG1 (WSA_START_OFFSET + 0x0408)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_CFG2 (WSA_START_OFFSET + 0x040C)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_CFG3 (WSA_START_OFFSET + 0x0410)
|
||||
#define LPASS_CDC_WSA_RX0_RX_VOL_CTL (WSA_START_OFFSET + 0x0414)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_MIX_CTL (WSA_START_OFFSET + 0x0418)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_MIX_CFG (WSA_START_OFFSET + 0x041C)
|
||||
#define LPASS_CDC_WSA_RX0_RX_VOL_MIX_CTL (WSA_START_OFFSET + 0x0420)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_SEC0 (WSA_START_OFFSET + 0x0424)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_SEC1 (WSA_START_OFFSET + 0x0428)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_SEC2 (WSA_START_OFFSET + 0x042C)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_SEC3 (WSA_START_OFFSET + 0x0430)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_SEC5 (WSA_START_OFFSET + 0x0438)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_SEC6 (WSA_START_OFFSET + 0x043C)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_SEC7 (WSA_START_OFFSET + 0x0440)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_MIX_SEC0 (WSA_START_OFFSET + 0x0444)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_MIX_SEC1 (WSA_START_OFFSET + 0x0448)
|
||||
#define LPASS_CDC_WSA_RX0_RX_PATH_DSMDEM_CTL (WSA_START_OFFSET + 0x044C)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_CTL (WSA_START_OFFSET + 0x0480)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_CFG0 (WSA_START_OFFSET + 0x0484)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_CFG1 (WSA_START_OFFSET + 0x0488)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_CFG2 (WSA_START_OFFSET + 0x048C)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_CFG3 (WSA_START_OFFSET + 0x0490)
|
||||
#define LPASS_CDC_WSA_RX1_RX_VOL_CTL (WSA_START_OFFSET + 0x0494)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_MIX_CTL (WSA_START_OFFSET + 0x0498)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_MIX_CFG (WSA_START_OFFSET + 0x049C)
|
||||
#define LPASS_CDC_WSA_RX1_RX_VOL_MIX_CTL (WSA_START_OFFSET + 0x04A0)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_SEC0 (WSA_START_OFFSET + 0x04A4)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_SEC1 (WSA_START_OFFSET + 0x04A8)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_SEC2 (WSA_START_OFFSET + 0x04AC)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_SEC3 (WSA_START_OFFSET + 0x04B0)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_SEC5 (WSA_START_OFFSET + 0x04B8)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_SEC6 (WSA_START_OFFSET + 0x04BC)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_SEC7 (WSA_START_OFFSET + 0x04C0)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_MIX_SEC0 (WSA_START_OFFSET + 0x04C4)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_MIX_SEC1 (WSA_START_OFFSET + 0x04C8)
|
||||
#define LPASS_CDC_WSA_RX1_RX_PATH_DSMDEM_CTL (WSA_START_OFFSET + 0x04CC)
|
||||
#define LPASS_CDC_WSA_BOOST0_BOOST_PATH_CTL (WSA_START_OFFSET + 0x0500)
|
||||
#define LPASS_CDC_WSA_BOOST0_BOOST_CTL (WSA_START_OFFSET + 0x0504)
|
||||
#define LPASS_CDC_WSA_BOOST0_BOOST_CFG1 (WSA_START_OFFSET + 0x0508)
|
||||
#define LPASS_CDC_WSA_BOOST0_BOOST_CFG2 (WSA_START_OFFSET + 0x050C)
|
||||
#define LPASS_CDC_WSA_BOOST1_BOOST_PATH_CTL (WSA_START_OFFSET + 0x0540)
|
||||
#define LPASS_CDC_WSA_BOOST1_BOOST_CTL (WSA_START_OFFSET + 0x0544)
|
||||
#define LPASS_CDC_WSA_BOOST1_BOOST_CFG1 (WSA_START_OFFSET + 0x0548)
|
||||
#define LPASS_CDC_WSA_BOOST1_BOOST_CFG2 (WSA_START_OFFSET + 0x054C)
|
||||
#define LPASS_CDC_WSA_COMPANDER0_CTL0 (WSA_START_OFFSET + 0x0580)
|
||||
#define LPASS_CDC_WSA_COMPANDER0_CTL1 (WSA_START_OFFSET + 0x0584)
|
||||
#define LPASS_CDC_WSA_COMPANDER0_CTL2 (WSA_START_OFFSET + 0x0588)
|
||||
#define LPASS_CDC_WSA_COMPANDER0_CTL3 (WSA_START_OFFSET + 0x058C)
|
||||
#define LPASS_CDC_WSA_COMPANDER0_CTL4 (WSA_START_OFFSET + 0x0590)
|
||||
#define LPASS_CDC_WSA_COMPANDER0_CTL5 (WSA_START_OFFSET + 0x0594)
|
||||
#define LPASS_CDC_WSA_COMPANDER0_CTL6 (WSA_START_OFFSET + 0x0598)
|
||||
#define LPASS_CDC_WSA_COMPANDER0_CTL7 (WSA_START_OFFSET + 0x059C)
|
||||
#define LPASS_CDC_WSA_COMPANDER1_CTL0 (WSA_START_OFFSET + 0x05C0)
|
||||
#define LPASS_CDC_WSA_COMPANDER1_CTL1 (WSA_START_OFFSET + 0x05C4)
|
||||
#define LPASS_CDC_WSA_COMPANDER1_CTL2 (WSA_START_OFFSET + 0x05C8)
|
||||
#define LPASS_CDC_WSA_COMPANDER1_CTL3 (WSA_START_OFFSET + 0x05CC)
|
||||
#define LPASS_CDC_WSA_COMPANDER1_CTL4 (WSA_START_OFFSET + 0x05D0)
|
||||
#define LPASS_CDC_WSA_COMPANDER1_CTL5 (WSA_START_OFFSET + 0x05D4)
|
||||
#define LPASS_CDC_WSA_COMPANDER1_CTL6 (WSA_START_OFFSET + 0x05D8)
|
||||
#define LPASS_CDC_WSA_COMPANDER1_CTL7 (WSA_START_OFFSET + 0x05DC)
|
||||
#define LPASS_CDC_WSA_SOFTCLIP0_CRC (WSA_START_OFFSET + 0x0600)
|
||||
#define LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL (WSA_START_OFFSET + 0x0604)
|
||||
#define LPASS_CDC_WSA_SOFTCLIP1_CRC (WSA_START_OFFSET + 0x0640)
|
||||
#define LPASS_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL (WSA_START_OFFSET + 0x0644)
|
||||
#define LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL \
|
||||
(WSA_START_OFFSET + 0x0680)
|
||||
#define LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 (WSA_START_OFFSET + 0x0684)
|
||||
#define LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL \
|
||||
(WSA_START_OFFSET + 0x06C0)
|
||||
#define LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0 (WSA_START_OFFSET + 0x06C4)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL (WSA_START_OFFSET + 0x0700)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC0_CTL0 (WSA_START_OFFSET + 0x0704)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC0_CTL1 (WSA_START_OFFSET + 0x0708)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC0_FIFO_CTL (WSA_START_OFFSET + 0x070C)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB \
|
||||
(WSA_START_OFFSET + 0x0710)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB \
|
||||
(WSA_START_OFFSET + 0x0714)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB \
|
||||
(WSA_START_OFFSET + 0x0718)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB \
|
||||
(WSA_START_OFFSET + 0x071C)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO (WSA_START_OFFSET + 0x0720)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL (WSA_START_OFFSET + 0x0740)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC1_CTL0 (WSA_START_OFFSET + 0x0744)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC1_CTL1 (WSA_START_OFFSET + 0x0748)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC1_FIFO_CTL (WSA_START_OFFSET + 0x074C)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB \
|
||||
(WSA_START_OFFSET + 0x0750)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB \
|
||||
(WSA_START_OFFSET + 0x0754)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB \
|
||||
(WSA_START_OFFSET + 0x0758)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB \
|
||||
(WSA_START_OFFSET + 0x075C)
|
||||
#define LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO (WSA_START_OFFSET + 0x0760)
|
||||
#define WSA_MAX_OFFSET (WSA_START_OFFSET + 0x0760)
|
||||
|
||||
#define LPASS_CDC_WSA_MACRO_MAX 0x1D9 /* 0x760/4 = 0x1D8 + 1 registers */
|
||||
|
||||
/* VA macro registers */
|
||||
#define VA_START_OFFSET 0x3000
|
||||
#define LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (VA_START_OFFSET + 0x0000)
|
||||
#define LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL \
|
||||
(VA_START_OFFSET + 0x0004)
|
||||
#define LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL (VA_START_OFFSET + 0x0008)
|
||||
#define LPASS_CDC_VA_TOP_CSR_TOP_CFG0 (VA_START_OFFSET + 0x0080)
|
||||
#define LPASS_CDC_VA_TOP_CSR_DMIC0_CTL (VA_START_OFFSET + 0x0084)
|
||||
#define LPASS_CDC_VA_TOP_CSR_DMIC1_CTL (VA_START_OFFSET + 0x0088)
|
||||
#define LPASS_CDC_VA_TOP_CSR_DMIC2_CTL (VA_START_OFFSET + 0x008C)
|
||||
#define LPASS_CDC_VA_TOP_CSR_DMIC3_CTL (VA_START_OFFSET + 0x0090)
|
||||
#define LPASS_CDC_VA_TOP_CSR_DMIC_CFG (VA_START_OFFSET + 0x0094)
|
||||
#define LPASS_CDC_VA_TOP_CSR_DEBUG_BUS (VA_START_OFFSET + 0x009C)
|
||||
#define LPASS_CDC_VA_TOP_CSR_DEBUG_EN (VA_START_OFFSET + 0x00A0)
|
||||
#define LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL (VA_START_OFFSET + 0x00A4)
|
||||
#define LPASS_CDC_VA_TOP_CSR_I2S_CLK (VA_START_OFFSET + 0x00A8)
|
||||
#define LPASS_CDC_VA_TOP_CSR_I2S_RESET (VA_START_OFFSET + 0x00AC)
|
||||
#define LPASS_CDC_VA_TOP_CSR_CORE_ID_0 (VA_START_OFFSET + 0x00C0)
|
||||
#define LPASS_CDC_VA_TOP_CSR_CORE_ID_1 (VA_START_OFFSET + 0x00C4)
|
||||
#define LPASS_CDC_VA_TOP_CSR_CORE_ID_2 (VA_START_OFFSET + 0x00C8)
|
||||
#define LPASS_CDC_VA_TOP_CSR_CORE_ID_3 (VA_START_OFFSET + 0x00CC)
|
||||
#define VA_TOP_MAX_OFFSET (VA_START_OFFSET + 0x00CC)
|
||||
|
||||
#define LPASS_CDC_VA_MACRO_TOP_MAX 0x34 /* 0x0CC/4 = 0x33 + 1 = 0x34 */
|
||||
|
||||
#define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0 (VA_START_OFFSET + 0x00D0)
|
||||
#define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1 (VA_START_OFFSET + 0x00D4)
|
||||
#define LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2 (VA_START_OFFSET + 0x00D8)
|
||||
#define LPASS_CDC_VA_TOP_CSR_SWR_CTRL (VA_START_OFFSET + 0x00DC)
|
||||
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0 (VA_START_OFFSET + 0x0100)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1 (VA_START_OFFSET + 0x0104)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0 (VA_START_OFFSET + 0x0108)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG1 (VA_START_OFFSET + 0x010C)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG0 (VA_START_OFFSET + 0x0110)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1 (VA_START_OFFSET + 0x0114)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0 (VA_START_OFFSET + 0x0118)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1 (VA_START_OFFSET + 0x011C)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0 (VA_START_OFFSET + 0x0120)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG1 (VA_START_OFFSET + 0x0124)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0 (VA_START_OFFSET + 0x0128)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG1 (VA_START_OFFSET + 0x012C)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0 (VA_START_OFFSET + 0x0130)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG1 (VA_START_OFFSET + 0x0134)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0 (VA_START_OFFSET + 0x0138)
|
||||
#define LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG1 (VA_START_OFFSET + 0x013C)
|
||||
|
||||
#define LPASS_CDC_VA_TX0_TX_PATH_CTL (VA_START_OFFSET + 0x0400)
|
||||
#define LPASS_CDC_VA_TX0_TX_PATH_CFG0 (VA_START_OFFSET + 0x0404)
|
||||
#define LPASS_CDC_VA_TX0_TX_PATH_CFG1 (VA_START_OFFSET + 0x0408)
|
||||
#define LPASS_CDC_VA_TX0_TX_VOL_CTL (VA_START_OFFSET + 0x040C)
|
||||
#define LPASS_CDC_VA_TX0_TX_PATH_SEC0 (VA_START_OFFSET + 0x0410)
|
||||
#define LPASS_CDC_VA_TX0_TX_PATH_SEC1 (VA_START_OFFSET + 0x0414)
|
||||
#define LPASS_CDC_VA_TX0_TX_PATH_SEC2 (VA_START_OFFSET + 0x0418)
|
||||
#define LPASS_CDC_VA_TX0_TX_PATH_SEC3 (VA_START_OFFSET + 0x041C)
|
||||
#define LPASS_CDC_VA_TX0_TX_PATH_SEC4 (VA_START_OFFSET + 0x0420)
|
||||
#define LPASS_CDC_VA_TX0_TX_PATH_SEC5 (VA_START_OFFSET + 0x0424)
|
||||
#define LPASS_CDC_VA_TX0_TX_PATH_SEC6 (VA_START_OFFSET + 0x0428)
|
||||
#define LPASS_CDC_VA_TX0_TX_PATH_SEC7 (VA_START_OFFSET + 0x042C)
|
||||
#define LPASS_CDC_VA_TX1_TX_PATH_CTL (VA_START_OFFSET + 0x0480)
|
||||
#define LPASS_CDC_VA_TX1_TX_PATH_CFG0 (VA_START_OFFSET + 0x0484)
|
||||
#define LPASS_CDC_VA_TX1_TX_PATH_CFG1 (VA_START_OFFSET + 0x0488)
|
||||
#define LPASS_CDC_VA_TX1_TX_VOL_CTL (VA_START_OFFSET + 0x048C)
|
||||
#define LPASS_CDC_VA_TX1_TX_PATH_SEC0 (VA_START_OFFSET + 0x0490)
|
||||
#define LPASS_CDC_VA_TX1_TX_PATH_SEC1 (VA_START_OFFSET + 0x0494)
|
||||
#define LPASS_CDC_VA_TX1_TX_PATH_SEC2 (VA_START_OFFSET + 0x0498)
|
||||
#define LPASS_CDC_VA_TX1_TX_PATH_SEC3 (VA_START_OFFSET + 0x049C)
|
||||
#define LPASS_CDC_VA_TX1_TX_PATH_SEC4 (VA_START_OFFSET + 0x04A0)
|
||||
#define LPASS_CDC_VA_TX1_TX_PATH_SEC5 (VA_START_OFFSET + 0x04A4)
|
||||
#define LPASS_CDC_VA_TX1_TX_PATH_SEC6 (VA_START_OFFSET + 0x04A8)
|
||||
#define LPASS_CDC_VA_TX2_TX_PATH_CTL (VA_START_OFFSET + 0x0500)
|
||||
#define LPASS_CDC_VA_TX2_TX_PATH_CFG0 (VA_START_OFFSET + 0x0504)
|
||||
#define LPASS_CDC_VA_TX2_TX_PATH_CFG1 (VA_START_OFFSET + 0x0508)
|
||||
#define LPASS_CDC_VA_TX2_TX_VOL_CTL (VA_START_OFFSET + 0x050C)
|
||||
#define LPASS_CDC_VA_TX2_TX_PATH_SEC0 (VA_START_OFFSET + 0x0510)
|
||||
#define LPASS_CDC_VA_TX2_TX_PATH_SEC1 (VA_START_OFFSET + 0x0514)
|
||||
#define LPASS_CDC_VA_TX2_TX_PATH_SEC2 (VA_START_OFFSET + 0x0518)
|
||||
#define LPASS_CDC_VA_TX2_TX_PATH_SEC3 (VA_START_OFFSET + 0x051C)
|
||||
#define LPASS_CDC_VA_TX2_TX_PATH_SEC4 (VA_START_OFFSET + 0x0520)
|
||||
#define LPASS_CDC_VA_TX2_TX_PATH_SEC5 (VA_START_OFFSET + 0x0524)
|
||||
#define LPASS_CDC_VA_TX2_TX_PATH_SEC6 (VA_START_OFFSET + 0x0528)
|
||||
#define LPASS_CDC_VA_TX3_TX_PATH_CTL (VA_START_OFFSET + 0x0580)
|
||||
#define LPASS_CDC_VA_TX3_TX_PATH_CFG0 (VA_START_OFFSET + 0x0584)
|
||||
#define LPASS_CDC_VA_TX3_TX_PATH_CFG1 (VA_START_OFFSET + 0x0588)
|
||||
#define LPASS_CDC_VA_TX3_TX_VOL_CTL (VA_START_OFFSET + 0x058C)
|
||||
#define LPASS_CDC_VA_TX3_TX_PATH_SEC0 (VA_START_OFFSET + 0x0590)
|
||||
#define LPASS_CDC_VA_TX3_TX_PATH_SEC1 (VA_START_OFFSET + 0x0594)
|
||||
#define LPASS_CDC_VA_TX3_TX_PATH_SEC2 (VA_START_OFFSET + 0x0598)
|
||||
#define LPASS_CDC_VA_TX3_TX_PATH_SEC3 (VA_START_OFFSET + 0x059C)
|
||||
#define LPASS_CDC_VA_TX3_TX_PATH_SEC4 (VA_START_OFFSET + 0x05A0)
|
||||
#define LPASS_CDC_VA_TX3_TX_PATH_SEC5 (VA_START_OFFSET + 0x05A4)
|
||||
#define LPASS_CDC_VA_TX3_TX_PATH_SEC6 (VA_START_OFFSET + 0x05A8)
|
||||
#define LPASS_CDC_VA_TX4_TX_PATH_CTL (VA_START_OFFSET + 0x0600)
|
||||
#define LPASS_CDC_VA_TX4_TX_PATH_CFG0 (VA_START_OFFSET + 0x0604)
|
||||
#define LPASS_CDC_VA_TX4_TX_PATH_CFG1 (VA_START_OFFSET + 0x0608)
|
||||
#define LPASS_CDC_VA_TX4_TX_VOL_CTL (VA_START_OFFSET + 0x060C)
|
||||
#define LPASS_CDC_VA_TX4_TX_PATH_SEC0 (VA_START_OFFSET + 0x0610)
|
||||
#define LPASS_CDC_VA_TX4_TX_PATH_SEC1 (VA_START_OFFSET + 0x0614)
|
||||
#define LPASS_CDC_VA_TX4_TX_PATH_SEC2 (VA_START_OFFSET + 0x0618)
|
||||
#define LPASS_CDC_VA_TX4_TX_PATH_SEC3 (VA_START_OFFSET + 0x061C)
|
||||
#define LPASS_CDC_VA_TX4_TX_PATH_SEC4 (VA_START_OFFSET + 0x0620)
|
||||
#define LPASS_CDC_VA_TX4_TX_PATH_SEC5 (VA_START_OFFSET + 0x0624)
|
||||
#define LPASS_CDC_VA_TX4_TX_PATH_SEC6 (VA_START_OFFSET + 0x0628)
|
||||
#define LPASS_CDC_VA_TX5_TX_PATH_CTL (VA_START_OFFSET + 0x0680)
|
||||
#define LPASS_CDC_VA_TX5_TX_PATH_CFG0 (VA_START_OFFSET + 0x0684)
|
||||
#define LPASS_CDC_VA_TX5_TX_PATH_CFG1 (VA_START_OFFSET + 0x0688)
|
||||
#define LPASS_CDC_VA_TX5_TX_VOL_CTL (VA_START_OFFSET + 0x068C)
|
||||
#define LPASS_CDC_VA_TX5_TX_PATH_SEC0 (VA_START_OFFSET + 0x0690)
|
||||
#define LPASS_CDC_VA_TX5_TX_PATH_SEC1 (VA_START_OFFSET + 0x0694)
|
||||
#define LPASS_CDC_VA_TX5_TX_PATH_SEC2 (VA_START_OFFSET + 0x0698)
|
||||
#define LPASS_CDC_VA_TX5_TX_PATH_SEC3 (VA_START_OFFSET + 0x069C)
|
||||
#define LPASS_CDC_VA_TX5_TX_PATH_SEC4 (VA_START_OFFSET + 0x06A0)
|
||||
#define LPASS_CDC_VA_TX5_TX_PATH_SEC5 (VA_START_OFFSET + 0x06A4)
|
||||
#define LPASS_CDC_VA_TX5_TX_PATH_SEC6 (VA_START_OFFSET + 0x06A8)
|
||||
#define LPASS_CDC_VA_TX6_TX_PATH_CTL (VA_START_OFFSET + 0x0700)
|
||||
#define LPASS_CDC_VA_TX6_TX_PATH_CFG0 (VA_START_OFFSET + 0x0704)
|
||||
#define LPASS_CDC_VA_TX6_TX_PATH_CFG1 (VA_START_OFFSET + 0x0708)
|
||||
#define LPASS_CDC_VA_TX6_TX_VOL_CTL (VA_START_OFFSET + 0x070C)
|
||||
#define LPASS_CDC_VA_TX6_TX_PATH_SEC0 (VA_START_OFFSET + 0x0710)
|
||||
#define LPASS_CDC_VA_TX6_TX_PATH_SEC1 (VA_START_OFFSET + 0x0714)
|
||||
#define LPASS_CDC_VA_TX6_TX_PATH_SEC2 (VA_START_OFFSET + 0x0718)
|
||||
#define LPASS_CDC_VA_TX6_TX_PATH_SEC3 (VA_START_OFFSET + 0x071C)
|
||||
#define LPASS_CDC_VA_TX6_TX_PATH_SEC4 (VA_START_OFFSET + 0x0720)
|
||||
#define LPASS_CDC_VA_TX6_TX_PATH_SEC5 (VA_START_OFFSET + 0x0724)
|
||||
#define LPASS_CDC_VA_TX6_TX_PATH_SEC6 (VA_START_OFFSET + 0x0728)
|
||||
#define LPASS_CDC_VA_TX7_TX_PATH_CTL (VA_START_OFFSET + 0x0780)
|
||||
#define LPASS_CDC_VA_TX7_TX_PATH_CFG0 (VA_START_OFFSET + 0x0784)
|
||||
#define LPASS_CDC_VA_TX7_TX_PATH_CFG1 (VA_START_OFFSET + 0x0788)
|
||||
#define LPASS_CDC_VA_TX7_TX_VOL_CTL (VA_START_OFFSET + 0x078C)
|
||||
#define LPASS_CDC_VA_TX7_TX_PATH_SEC0 (VA_START_OFFSET + 0x0790)
|
||||
#define LPASS_CDC_VA_TX7_TX_PATH_SEC1 (VA_START_OFFSET + 0x0794)
|
||||
#define LPASS_CDC_VA_TX7_TX_PATH_SEC2 (VA_START_OFFSET + 0x0798)
|
||||
#define LPASS_CDC_VA_TX7_TX_PATH_SEC3 (VA_START_OFFSET + 0x079C)
|
||||
#define LPASS_CDC_VA_TX7_TX_PATH_SEC4 (VA_START_OFFSET + 0x07A0)
|
||||
#define LPASS_CDC_VA_TX7_TX_PATH_SEC5 (VA_START_OFFSET + 0x07A4)
|
||||
#define LPASS_CDC_VA_TX7_TX_PATH_SEC6 (VA_START_OFFSET + 0x07A8)
|
||||
#define VA_MAX_OFFSET (VA_START_OFFSET + 0x07A8)
|
||||
|
||||
#define LPASS_CDC_VA_MACRO_MAX 0x1EB /* 7A8/4 = 1EA + 1 = 1EB */
|
||||
|
||||
#define LPASS_CDC_MAX_REGISTER VA_MAX_OFFSET
|
||||
|
||||
#define LPASS_CDC_REG(reg) (((reg) & 0x0FFF)/4)
|
||||
|
||||
#endif
|
||||
873
asoc/codecs/lpass-cdc/lpass-cdc-regmap.c
Normal file
873
asoc/codecs/lpass-cdc/lpass-cdc-regmap.c
Normal file
@@ -0,0 +1,873 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/regmap.h>
|
||||
#include "lpass-cdc.h"
|
||||
#include "internal.h"
|
||||
|
||||
static const struct reg_default lpass_cdc_defaults[] = {
|
||||
/* TX Macro */
|
||||
{ LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
|
||||
{ LPASS_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
|
||||
{ LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
|
||||
{ LPASS_CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
|
||||
{ LPASS_CDC_TX_TOP_CSR_ANC_CFG, 0x00},
|
||||
{ LPASS_CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
|
||||
{ LPASS_CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
|
||||
{ LPASS_CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
|
||||
{ LPASS_CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
|
||||
{ LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
|
||||
{ LPASS_CDC_TX_TOP_CSR_I2S_CLK, 0x00},
|
||||
{ LPASS_CDC_TX_TOP_CSR_I2S_RESET, 0x00},
|
||||
{ LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00},
|
||||
{ LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_CLK_RESET_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_MODE_1_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_MODE_2_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_FF_SHIFT, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_FB_SHIFT, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_LPF_FF_A_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_LPF_FF_B_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_LPF_FB_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_SMLPF_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00},
|
||||
{ LPASS_CDC_TX_ANC0_FB_GAIN_CTL, 0x00},
|
||||
{ LPASS_CDC_TX0_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_TX0_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_TX0_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_TX0_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_TX0_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_TX0_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_TX0_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_TX0_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_TX0_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_TX0_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_TX0_TX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_TX0_TX_PATH_SEC7, 0x25},
|
||||
{ LPASS_CDC_TX1_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_TX1_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_TX1_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_TX1_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_TX1_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_TX1_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_TX1_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_TX1_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_TX1_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_TX1_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_TX1_TX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_TX2_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_TX2_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_TX2_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_TX2_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_TX2_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_TX2_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_TX2_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_TX2_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_TX2_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_TX2_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_TX2_TX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_TX3_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_TX3_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_TX3_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_TX3_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_TX3_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_TX3_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_TX3_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_TX3_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_TX3_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_TX3_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_TX3_TX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_TX4_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_TX4_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_TX4_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_TX4_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_TX4_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_TX4_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_TX4_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_TX4_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_TX4_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_TX4_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_TX4_TX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_TX5_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_TX5_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_TX5_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_TX5_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_TX5_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_TX5_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_TX5_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_TX5_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_TX5_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_TX5_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_TX5_TX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_TX6_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_TX6_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_TX6_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_TX6_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_TX6_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_TX6_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_TX6_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_TX6_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_TX6_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_TX6_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_TX6_TX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_TX7_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_TX7_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_TX7_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_TX7_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_TX7_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_TX7_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_TX7_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_TX7_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_TX7_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_TX7_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_TX7_TX_PATH_SEC6, 0x00},
|
||||
|
||||
/* RX Macro */
|
||||
{ LPASS_CDC_RX_TOP_TOP_CFG0, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_SWR_CTRL, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_DEBUG, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_DEBUG_BUS, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_DEBUG_EN0, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_DEBUG_EN1, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_DEBUG_EN2, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_HPHL_COMP_WR_LSB, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_HPHL_COMP_WR_MSB, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_HPHL_COMP_LUT, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_HPHL_COMP_RD_LSB, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_HPHL_COMP_RD_MSB, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_HPHR_COMP_WR_LSB, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_HPHR_COMP_WR_MSB, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_HPHR_COMP_LUT, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_HPHR_COMP_RD_LSB, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_HPHR_COMP_RD_MSB, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11},
|
||||
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20},
|
||||
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11},
|
||||
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20},
|
||||
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_RX_I2S_CTL, 0x0C},
|
||||
{ LPASS_CDC_RX_TOP_TX_I2S2_CTL, 0x0C},
|
||||
{ LPASS_CDC_RX_TOP_I2S_CLK, 0x0C},
|
||||
{ LPASS_CDC_RX_TOP_I2S_RESET, 0x00},
|
||||
{ LPASS_CDC_RX_TOP_I2S_MUX, 0x00},
|
||||
{ LPASS_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
|
||||
{ LPASS_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
|
||||
{ LPASS_CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
|
||||
{ LPASS_CDC_RX_CLK_RST_CTRL_DSD_CONTROL, 0x00},
|
||||
{ LPASS_CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL, 0x08},
|
||||
{ LPASS_CDC_RX_SOFTCLIP_CRC, 0x00},
|
||||
{ LPASS_CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x38},
|
||||
{ LPASS_CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00},
|
||||
{ LPASS_CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00},
|
||||
{ LPASS_CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00},
|
||||
{ LPASS_CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00},
|
||||
{ LPASS_CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00},
|
||||
{ LPASS_CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00},
|
||||
{ LPASS_CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00},
|
||||
{ LPASS_CDC_RX_INP_MUX_RX_MIX_CFG5, 0x00},
|
||||
{ LPASS_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00},
|
||||
{ LPASS_CDC_RX_CLSH_CRC, 0x00},
|
||||
{ LPASS_CDC_RX_CLSH_DLY_CTRL, 0x03},
|
||||
{ LPASS_CDC_RX_CLSH_DECAY_CTRL, 0x02},
|
||||
{ LPASS_CDC_RX_CLSH_HPH_V_PA, 0x1C},
|
||||
{ LPASS_CDC_RX_CLSH_EAR_V_PA, 0x39},
|
||||
{ LPASS_CDC_RX_CLSH_HPH_V_HD, 0x0C},
|
||||
{ LPASS_CDC_RX_CLSH_EAR_V_HD, 0x0C},
|
||||
{ LPASS_CDC_RX_CLSH_K1_MSB, 0x01},
|
||||
{ LPASS_CDC_RX_CLSH_K1_LSB, 0x00},
|
||||
{ LPASS_CDC_RX_CLSH_K2_MSB, 0x00},
|
||||
{ LPASS_CDC_RX_CLSH_K2_LSB, 0x80},
|
||||
{ LPASS_CDC_RX_CLSH_IDLE_CTRL, 0x00},
|
||||
{ LPASS_CDC_RX_CLSH_IDLE_HPH, 0x00},
|
||||
{ LPASS_CDC_RX_CLSH_IDLE_EAR, 0x00},
|
||||
{ LPASS_CDC_RX_CLSH_TEST0, 0x07},
|
||||
{ LPASS_CDC_RX_CLSH_TEST1, 0x00},
|
||||
{ LPASS_CDC_RX_CLSH_OVR_VREF, 0x00},
|
||||
{ LPASS_CDC_RX_CLSH_CLSG_CTL, 0x02},
|
||||
{ LPASS_CDC_RX_CLSH_CLSG_CFG1, 0x9A},
|
||||
{ LPASS_CDC_RX_CLSH_CLSG_CFG2, 0x10},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_PATH_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_CFG, 0x10},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_ADC_CAL1, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_ADC_CAL2, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_ADC_CAL3, 0x04},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_PK_EST1, 0xE0},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_PK_EST2, 0x01},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_PK_EST3, 0x40},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_RF_PROC1, 0x2A},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_RF_PROC1, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_TAC1, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_TAC2, 0x18},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_TAC3, 0x18},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_TAC4, 0x03},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_GAIN_UPD1, 0x01},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_GAIN_UPD2, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_GAIN_UPD3, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_GAIN_UPD4, 0x64},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_GAIN_UPD5, 0x01},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_DEBUG1, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_GAIN_UPD_MON, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_GAIN_MON_VAL, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_BAN, 0x0C},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, 0x77},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, 0x01},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, 0x4B},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, 0x01},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_ATTN1, 0x04},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_ATTN2, 0x08},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_ATTN3, 0x0C},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00},
|
||||
{ LPASS_CDC_RX_BCL_VBAT_DECODE_ST, 0x00},
|
||||
{ LPASS_CDC_RX_INTR_CTRL_CFG, 0x00},
|
||||
{ LPASS_CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00},
|
||||
{ LPASS_CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF},
|
||||
{ LPASS_CDC_RX_INTR_CTRL_PIN1_STATUS0, 0x00},
|
||||
{ LPASS_CDC_RX_INTR_CTRL_PIN1_CLEAR0, 0x00},
|
||||
{ LPASS_CDC_RX_INTR_CTRL_PIN2_MASK0, 0xFF},
|
||||
{ LPASS_CDC_RX_INTR_CTRL_PIN2_STATUS0, 0x00},
|
||||
{ LPASS_CDC_RX_INTR_CTRL_PIN2_CLEAR0, 0x00},
|
||||
{ LPASS_CDC_RX_INTR_CTRL_LEVEL0, 0x00},
|
||||
{ LPASS_CDC_RX_INTR_CTRL_BYPASS0, 0x00},
|
||||
{ LPASS_CDC_RX_INTR_CTRL_SET0, 0x00},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_CFG0, 0x00},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_CFG1, 0x64},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_CFG2, 0x8F},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_CFG3, 0x00},
|
||||
{ LPASS_CDC_RX_RX0_RX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E},
|
||||
{ LPASS_CDC_RX_RX0_RX_VOL_MIX_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_SEC1, 0x08},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_SEC2, 0x00},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_SEC3, 0x00},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_SEC4, 0x00},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_SEC7, 0x00},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_MIX_SEC0, 0x08},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_MIX_SEC1, 0x00},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_CTL, 0x08},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA1, 0x00},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA2, 0x00},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA3, 0x00},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55},
|
||||
{ LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_CFG0, 0x00},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_CFG1, 0x64},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_CFG2, 0x8F},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_CFG3, 0x00},
|
||||
{ LPASS_CDC_RX_RX1_RX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E},
|
||||
{ LPASS_CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_SEC1, 0x08},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_SEC2, 0x00},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_SEC3, 0x00},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_SEC4, 0x00},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_SEC7, 0x00},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55},
|
||||
{ LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_CFG0, 0x00},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_CFG1, 0x64},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_CFG2, 0x8F},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_CFG3, 0x00},
|
||||
{ LPASS_CDC_RX_RX2_RX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E},
|
||||
{ LPASS_CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_SEC0, 0x04},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_SEC1, 0x08},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_SEC2, 0x00},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_SEC3, 0x00},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_SEC4, 0x00},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_SEC7, 0x00},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00},
|
||||
{ LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_IDLE_DETECT_PATH_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_IDLE_DETECT_CFG0, 0x07},
|
||||
{ LPASS_CDC_RX_IDLE_DETECT_CFG1, 0x3C},
|
||||
{ LPASS_CDC_RX_IDLE_DETECT_CFG2, 0x00},
|
||||
{ LPASS_CDC_RX_IDLE_DETECT_CFG3, 0x00},
|
||||
{ LPASS_CDC_RX_COMPANDER0_CTL0, 0x60},
|
||||
{ LPASS_CDC_RX_COMPANDER0_CTL1, 0xDB},
|
||||
{ LPASS_CDC_RX_COMPANDER0_CTL2, 0xFF},
|
||||
{ LPASS_CDC_RX_COMPANDER0_CTL3, 0x35},
|
||||
{ LPASS_CDC_RX_COMPANDER0_CTL4, 0xFF},
|
||||
{ LPASS_CDC_RX_COMPANDER0_CTL5, 0x00},
|
||||
{ LPASS_CDC_RX_COMPANDER0_CTL6, 0x01},
|
||||
{ LPASS_CDC_RX_COMPANDER0_CTL7, 0x28},
|
||||
{ LPASS_CDC_RX_COMPANDER1_CTL0, 0x60},
|
||||
{ LPASS_CDC_RX_COMPANDER1_CTL1, 0xDB},
|
||||
{ LPASS_CDC_RX_COMPANDER1_CTL2, 0xFF},
|
||||
{ LPASS_CDC_RX_COMPANDER1_CTL3, 0x35},
|
||||
{ LPASS_CDC_RX_COMPANDER1_CTL4, 0xFF},
|
||||
{ LPASS_CDC_RX_COMPANDER1_CTL5, 0x00},
|
||||
{ LPASS_CDC_RX_COMPANDER1_CTL6, 0x01},
|
||||
{ LPASS_CDC_RX_COMPANDER1_CTL7, 0x28},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_CTL, 0x40},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR1_IIR_CTL, 0x40},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00},
|
||||
{ LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00},
|
||||
{ LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00},
|
||||
{ LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00},
|
||||
{ LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00},
|
||||
{ LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00},
|
||||
{ LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00},
|
||||
{ LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00},
|
||||
{ LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00},
|
||||
{ LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0, 0x01},
|
||||
{ LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0, 0x01},
|
||||
{ LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0, 0x01},
|
||||
{ LPASS_CDC_RX_EC_ASRC0_CLK_RST_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC0_CTL0, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC0_CTL1, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC0_FIFO_CTL, 0xA8},
|
||||
{ LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC0_STATUS_FIFO, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC1_CLK_RST_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC1_CTL0, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC1_CTL1, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC1_FIFO_CTL, 0xA8},
|
||||
{ LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC1_STATUS_FIFO, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC2_CLK_RST_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC2_CTL0, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC2_CTL1, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC2_FIFO_CTL, 0xA8},
|
||||
{ LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB, 0x00},
|
||||
{ LPASS_CDC_RX_EC_ASRC2_STATUS_FIFO, 0x00},
|
||||
{ LPASS_CDC_RX_DSD0_PATH_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_DSD0_CFG0, 0x00},
|
||||
{ LPASS_CDC_RX_DSD0_CFG1, 0x62},
|
||||
{ LPASS_CDC_RX_DSD0_CFG2, 0x96},
|
||||
{ LPASS_CDC_RX_DSD1_PATH_CTL, 0x00},
|
||||
{ LPASS_CDC_RX_DSD1_CFG0, 0x00},
|
||||
{ LPASS_CDC_RX_DSD1_CFG1, 0x62},
|
||||
{ LPASS_CDC_RX_DSD1_CFG2, 0x96},
|
||||
|
||||
/* WSA Macro */
|
||||
{ LPASS_CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
|
||||
{ LPASS_CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
|
||||
{ LPASS_CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
|
||||
{ LPASS_CDC_WSA_TOP_TOP_CFG0, 0x00},
|
||||
{ LPASS_CDC_WSA_TOP_TOP_CFG1, 0x00},
|
||||
{ LPASS_CDC_WSA_TOP_FREQ_MCLK, 0x00},
|
||||
{ LPASS_CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00},
|
||||
{ LPASS_CDC_WSA_TOP_DEBUG_EN0, 0x00},
|
||||
{ LPASS_CDC_WSA_TOP_DEBUG_EN1, 0x00},
|
||||
{ LPASS_CDC_WSA_TOP_DEBUG_DSM_LB, 0x88},
|
||||
{ LPASS_CDC_WSA_TOP_RX_I2S_CTL, 0x0C},
|
||||
{ LPASS_CDC_WSA_TOP_TX_I2S_CTL, 0x0C},
|
||||
{ LPASS_CDC_WSA_TOP_I2S_CLK, 0x02},
|
||||
{ LPASS_CDC_WSA_TOP_I2S_RESET, 0x00},
|
||||
{ LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00},
|
||||
{ LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00},
|
||||
{ LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00},
|
||||
{ LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 0x00},
|
||||
{ LPASS_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 0x00},
|
||||
{ LPASS_CDC_WSA_RX_INP_MUX_RX_EC_CFG0, 0x00},
|
||||
{ LPASS_CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_PATH_CTL, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_CFG, 0x10},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL1, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL2, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL3, 0x04},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_PK_EST1, 0xE0},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_PK_EST2, 0x01},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_PK_EST3, 0x40},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_RF_PROC1, 0x2A},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_RF_PROC2, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC1, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC2, 0x18},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC3, 0x18},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC4, 0x03},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD1, 0x01},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD2, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD3, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD4, 0x64},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD5, 0x01},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DEBUG1, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD_MON, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BAN, 0x0C},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD1, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD2, 0x77},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD3, 0x01},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD4, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD5, 0x4B},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD6, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD7, 0x01},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD8, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD9, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1, 0x04},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2, 0x08},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3, 0x0C},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1, 0xE0},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4, 0x00},
|
||||
{ LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST, 0x00},
|
||||
{ LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02},
|
||||
{ LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00},
|
||||
{ LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02},
|
||||
{ LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x00},
|
||||
{ LPASS_CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x02},
|
||||
{ LPASS_CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x00},
|
||||
{ LPASS_CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x02},
|
||||
{ LPASS_CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x00},
|
||||
{ LPASS_CDC_WSA_INTR_CTRL_CFG, 0x00},
|
||||
{ LPASS_CDC_WSA_INTR_CTRL_CLR_COMMIT, 0x00},
|
||||
{ LPASS_CDC_WSA_INTR_CTRL_PIN1_MASK0, 0xFF},
|
||||
{ LPASS_CDC_WSA_INTR_CTRL_PIN1_STATUS0, 0x00},
|
||||
{ LPASS_CDC_WSA_INTR_CTRL_PIN1_CLEAR0, 0x00},
|
||||
{ LPASS_CDC_WSA_INTR_CTRL_PIN2_MASK0, 0xFF},
|
||||
{ LPASS_CDC_WSA_INTR_CTRL_PIN2_STATUS0, 0x00},
|
||||
{ LPASS_CDC_WSA_INTR_CTRL_PIN2_CLEAR0, 0x00},
|
||||
{ LPASS_CDC_WSA_INTR_CTRL_LEVEL0, 0x00},
|
||||
{ LPASS_CDC_WSA_INTR_CTRL_BYPASS0, 0x00},
|
||||
{ LPASS_CDC_WSA_INTR_CTRL_SET0, 0x00},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_CFG0, 0x00},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_CFG1, 0x64},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_CFG2, 0x8F},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_CFG3, 0x00},
|
||||
{ LPASS_CDC_WSA_RX0_RX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_MIX_CTL, 0x04},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x7E},
|
||||
{ LPASS_CDC_WSA_RX0_RX_VOL_MIX_CTL, 0x00},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_SEC0, 0x04},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_SEC1, 0x08},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_SEC2, 0x00},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_SEC3, 0x00},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_SEC7, 0x00},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_MIX_SEC0, 0x08},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00},
|
||||
{ LPASS_CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_CFG0, 0x00},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_CFG1, 0x64},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_CFG2, 0x8F},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_CFG3, 0x00},
|
||||
{ LPASS_CDC_WSA_RX1_RX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_MIX_CTL, 0x04},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x7E},
|
||||
{ LPASS_CDC_WSA_RX1_RX_VOL_MIX_CTL, 0x00},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_SEC0, 0x04},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_SEC1, 0x08},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_SEC2, 0x00},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_SEC3, 0x00},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_SEC7, 0x00},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_MIX_SEC0, 0x08},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_MIX_SEC1, 0x00},
|
||||
{ LPASS_CDC_WSA_RX1_RX_PATH_DSMDEM_CTL, 0x00},
|
||||
{ LPASS_CDC_WSA_BOOST0_BOOST_PATH_CTL, 0x00},
|
||||
{ LPASS_CDC_WSA_BOOST0_BOOST_CTL, 0xD0},
|
||||
{ LPASS_CDC_WSA_BOOST0_BOOST_CFG1, 0x89},
|
||||
{ LPASS_CDC_WSA_BOOST0_BOOST_CFG2, 0x04},
|
||||
{ LPASS_CDC_WSA_BOOST1_BOOST_PATH_CTL, 0x00},
|
||||
{ LPASS_CDC_WSA_BOOST1_BOOST_CTL, 0xD0},
|
||||
{ LPASS_CDC_WSA_BOOST1_BOOST_CFG1, 0x89},
|
||||
{ LPASS_CDC_WSA_BOOST1_BOOST_CFG2, 0x04},
|
||||
{ LPASS_CDC_WSA_COMPANDER0_CTL0, 0x60},
|
||||
{ LPASS_CDC_WSA_COMPANDER0_CTL1, 0xDB},
|
||||
{ LPASS_CDC_WSA_COMPANDER0_CTL2, 0xFF},
|
||||
{ LPASS_CDC_WSA_COMPANDER0_CTL3, 0x35},
|
||||
{ LPASS_CDC_WSA_COMPANDER0_CTL4, 0xFF},
|
||||
{ LPASS_CDC_WSA_COMPANDER0_CTL5, 0x00},
|
||||
{ LPASS_CDC_WSA_COMPANDER0_CTL6, 0x01},
|
||||
{ LPASS_CDC_WSA_COMPANDER0_CTL7, 0x28},
|
||||
{ LPASS_CDC_WSA_COMPANDER1_CTL0, 0x60},
|
||||
{ LPASS_CDC_WSA_COMPANDER1_CTL1, 0xDB},
|
||||
{ LPASS_CDC_WSA_COMPANDER1_CTL2, 0xFF},
|
||||
{ LPASS_CDC_WSA_COMPANDER1_CTL3, 0x35},
|
||||
{ LPASS_CDC_WSA_COMPANDER1_CTL4, 0xFF},
|
||||
{ LPASS_CDC_WSA_COMPANDER1_CTL5, 0x00},
|
||||
{ LPASS_CDC_WSA_COMPANDER1_CTL6, 0x01},
|
||||
{ LPASS_CDC_WSA_COMPANDER1_CTL7, 0x28},
|
||||
{ LPASS_CDC_WSA_SOFTCLIP0_CRC, 0x00},
|
||||
{ LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38},
|
||||
{ LPASS_CDC_WSA_SOFTCLIP1_CRC, 0x00},
|
||||
{ LPASS_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38},
|
||||
{ LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00},
|
||||
{ LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01},
|
||||
{ LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00},
|
||||
{ LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC0_CTL0, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC0_CTL1, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC1_CTL0, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC1_CTL1, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00},
|
||||
{ LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00},
|
||||
|
||||
/* VA macro */
|
||||
{ LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
|
||||
{ LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
|
||||
{ LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
|
||||
{ LPASS_CDC_VA_TOP_CSR_TOP_CFG0, 0x00},
|
||||
{ LPASS_CDC_VA_TOP_CSR_DMIC0_CTL, 0x00},
|
||||
{ LPASS_CDC_VA_TOP_CSR_DMIC1_CTL, 0x00},
|
||||
{ LPASS_CDC_VA_TOP_CSR_DMIC2_CTL, 0x00},
|
||||
{ LPASS_CDC_VA_TOP_CSR_DMIC3_CTL, 0x00},
|
||||
{ LPASS_CDC_VA_TOP_CSR_DMIC_CFG, 0x80},
|
||||
{ LPASS_CDC_VA_TOP_CSR_DEBUG_BUS, 0x00},
|
||||
{ LPASS_CDC_VA_TOP_CSR_DEBUG_EN, 0x00},
|
||||
{ LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C},
|
||||
{ LPASS_CDC_VA_TOP_CSR_I2S_CLK, 0x00},
|
||||
{ LPASS_CDC_VA_TOP_CSR_I2S_RESET, 0x00},
|
||||
{ LPASS_CDC_VA_TOP_CSR_CORE_ID_0, 0x00},
|
||||
{ LPASS_CDC_VA_TOP_CSR_CORE_ID_1, 0x00},
|
||||
{ LPASS_CDC_VA_TOP_CSR_CORE_ID_2, 0x00},
|
||||
{ LPASS_CDC_VA_TOP_CSR_CORE_ID_3, 0x00},
|
||||
{ LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE},
|
||||
{ LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE},
|
||||
{ LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE},
|
||||
{ LPASS_CDC_VA_TOP_CSR_SWR_CTRL, 0x06},
|
||||
|
||||
/* VA core */
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG1, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG1, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG1, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0, 0x00},
|
||||
{ LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG1, 0x00},
|
||||
{ LPASS_CDC_VA_TX0_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_VA_TX0_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_VA_TX0_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_VA_TX0_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_VA_TX0_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_VA_TX0_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_VA_TX0_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_VA_TX0_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_VA_TX0_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_VA_TX0_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_VA_TX0_TX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_VA_TX0_TX_PATH_SEC7, 0x25},
|
||||
{ LPASS_CDC_VA_TX1_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_VA_TX1_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_VA_TX1_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_VA_TX1_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_VA_TX1_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_VA_TX1_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_VA_TX1_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_VA_TX1_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_VA_TX1_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_VA_TX1_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_VA_TX1_TX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_VA_TX2_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_VA_TX2_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_VA_TX2_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_VA_TX2_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_VA_TX2_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_VA_TX2_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_VA_TX2_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_VA_TX2_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_VA_TX2_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_VA_TX2_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_VA_TX2_TX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_VA_TX3_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_VA_TX3_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_VA_TX3_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_VA_TX3_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_VA_TX3_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_VA_TX3_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_VA_TX3_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_VA_TX3_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_VA_TX3_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_VA_TX3_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_VA_TX3_TX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_VA_TX4_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_VA_TX4_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_VA_TX4_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_VA_TX4_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_VA_TX4_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_VA_TX4_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_VA_TX4_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_VA_TX4_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_VA_TX4_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_VA_TX4_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_VA_TX4_TX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_VA_TX5_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_VA_TX5_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_VA_TX5_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_VA_TX5_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_VA_TX5_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_VA_TX5_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_VA_TX5_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_VA_TX5_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_VA_TX5_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_VA_TX5_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_VA_TX5_TX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_VA_TX6_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_VA_TX6_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_VA_TX6_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_VA_TX6_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_VA_TX6_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_VA_TX6_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_VA_TX6_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_VA_TX6_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_VA_TX6_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_VA_TX6_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_VA_TX6_TX_PATH_SEC6, 0x00},
|
||||
{ LPASS_CDC_VA_TX7_TX_PATH_CTL, 0x04},
|
||||
{ LPASS_CDC_VA_TX7_TX_PATH_CFG0, 0x10},
|
||||
{ LPASS_CDC_VA_TX7_TX_PATH_CFG1, 0x0B},
|
||||
{ LPASS_CDC_VA_TX7_TX_VOL_CTL, 0x00},
|
||||
{ LPASS_CDC_VA_TX7_TX_PATH_SEC0, 0x00},
|
||||
{ LPASS_CDC_VA_TX7_TX_PATH_SEC1, 0x00},
|
||||
{ LPASS_CDC_VA_TX7_TX_PATH_SEC2, 0x01},
|
||||
{ LPASS_CDC_VA_TX7_TX_PATH_SEC3, 0x3C},
|
||||
{ LPASS_CDC_VA_TX7_TX_PATH_SEC4, 0x20},
|
||||
{ LPASS_CDC_VA_TX7_TX_PATH_SEC5, 0x00},
|
||||
{ LPASS_CDC_VA_TX7_TX_PATH_SEC6, 0x00},
|
||||
};
|
||||
|
||||
static bool lpass_cdc_is_readable_register(struct device *dev,
|
||||
unsigned int reg)
|
||||
{
|
||||
struct lpass_cdc_priv *priv = dev_get_drvdata(dev);
|
||||
u16 reg_offset;
|
||||
int macro_id;
|
||||
u8 *reg_tbl = NULL;
|
||||
|
||||
if (!priv)
|
||||
return false;
|
||||
|
||||
macro_id = lpass_cdc_get_macro_id(priv->va_without_decimation,
|
||||
reg);
|
||||
if (macro_id < 0 || !priv->macros_supported[macro_id])
|
||||
return false;
|
||||
|
||||
reg_tbl = lpass_cdc_reg_access[macro_id];
|
||||
reg_offset = (reg - macro_id_base_offset[macro_id])/4;
|
||||
|
||||
if (reg_tbl)
|
||||
return (reg_tbl[reg_offset] & RD_REG);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool lpass_cdc_is_writeable_register(struct device *dev,
|
||||
unsigned int reg)
|
||||
{
|
||||
struct lpass_cdc_priv *priv = dev_get_drvdata(dev);
|
||||
u16 reg_offset;
|
||||
int macro_id;
|
||||
const u8 *reg_tbl = NULL;
|
||||
|
||||
if (!priv)
|
||||
return false;
|
||||
|
||||
macro_id = lpass_cdc_get_macro_id(priv->va_without_decimation,
|
||||
reg);
|
||||
if (macro_id < 0 || !priv->macros_supported[macro_id])
|
||||
return false;
|
||||
|
||||
reg_tbl = lpass_cdc_reg_access[macro_id];
|
||||
reg_offset = (reg - macro_id_base_offset[macro_id])/4;
|
||||
|
||||
if (reg_tbl)
|
||||
return (reg_tbl[reg_offset] & WR_REG);
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool lpass_cdc_is_volatile_register(struct device *dev,
|
||||
unsigned int reg)
|
||||
{
|
||||
/* Update volatile list for rx/tx macros */
|
||||
switch (reg) {
|
||||
case LPASS_CDC_VA_TOP_CSR_CORE_ID_0:
|
||||
case LPASS_CDC_VA_TOP_CSR_CORE_ID_1:
|
||||
case LPASS_CDC_VA_TOP_CSR_CORE_ID_2:
|
||||
case LPASS_CDC_VA_TOP_CSR_CORE_ID_3:
|
||||
case LPASS_CDC_VA_TOP_CSR_DMIC0_CTL:
|
||||
case LPASS_CDC_VA_TOP_CSR_DMIC1_CTL:
|
||||
case LPASS_CDC_VA_TOP_CSR_DMIC2_CTL:
|
||||
case LPASS_CDC_VA_TOP_CSR_DMIC3_CTL:
|
||||
case LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
|
||||
case LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
|
||||
case LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
|
||||
case LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
|
||||
case LPASS_CDC_TX_TOP_CSR_SWR_MIC0_CTL:
|
||||
case LPASS_CDC_TX_TOP_CSR_SWR_MIC1_CTL:
|
||||
case LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL:
|
||||
case LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST:
|
||||
case LPASS_CDC_WSA_INTR_CTRL_PIN1_STATUS0:
|
||||
case LPASS_CDC_WSA_INTR_CTRL_PIN2_STATUS0:
|
||||
case LPASS_CDC_WSA_COMPANDER0_CTL6:
|
||||
case LPASS_CDC_WSA_COMPANDER1_CTL6:
|
||||
case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
|
||||
case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
|
||||
case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
|
||||
case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
|
||||
case LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
|
||||
case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
|
||||
case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
|
||||
case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
|
||||
case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
|
||||
case LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
|
||||
case LPASS_CDC_RX_TOP_HPHL_COMP_RD_LSB:
|
||||
case LPASS_CDC_RX_TOP_HPHL_COMP_WR_LSB:
|
||||
case LPASS_CDC_RX_TOP_HPHL_COMP_RD_MSB:
|
||||
case LPASS_CDC_RX_TOP_HPHL_COMP_WR_MSB:
|
||||
case LPASS_CDC_RX_TOP_HPHR_COMP_RD_LSB:
|
||||
case LPASS_CDC_RX_TOP_HPHR_COMP_WR_LSB:
|
||||
case LPASS_CDC_RX_TOP_HPHR_COMP_RD_MSB:
|
||||
case LPASS_CDC_RX_TOP_HPHR_COMP_WR_MSB:
|
||||
case LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG2:
|
||||
case LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG2:
|
||||
case LPASS_CDC_RX_BCL_VBAT_GAIN_MON_VAL:
|
||||
case LPASS_CDC_RX_BCL_VBAT_DECODE_ST:
|
||||
case LPASS_CDC_RX_INTR_CTRL_PIN1_STATUS0:
|
||||
case LPASS_CDC_RX_INTR_CTRL_PIN2_STATUS0:
|
||||
case LPASS_CDC_RX_COMPANDER0_CTL6:
|
||||
case LPASS_CDC_RX_COMPANDER1_CTL6:
|
||||
case LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB:
|
||||
case LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB:
|
||||
case LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB:
|
||||
case LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB:
|
||||
case LPASS_CDC_RX_EC_ASRC0_STATUS_FIFO:
|
||||
case LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB:
|
||||
case LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB:
|
||||
case LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB:
|
||||
case LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB:
|
||||
case LPASS_CDC_RX_EC_ASRC1_STATUS_FIFO:
|
||||
case LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB:
|
||||
case LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB:
|
||||
case LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB:
|
||||
case LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB:
|
||||
case LPASS_CDC_RX_EC_ASRC2_STATUS_FIFO:
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
const struct regmap_config lpass_cdc_regmap_config = {
|
||||
.reg_bits = 16,
|
||||
.val_bits = 8,
|
||||
.reg_stride = 4,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
.reg_defaults = lpass_cdc_defaults,
|
||||
.num_reg_defaults = ARRAY_SIZE(lpass_cdc_defaults),
|
||||
.max_register = LPASS_CDC_MAX_REGISTER,
|
||||
.writeable_reg = lpass_cdc_is_writeable_register,
|
||||
.volatile_reg = lpass_cdc_is_volatile_register,
|
||||
.readable_reg = lpass_cdc_is_readable_register,
|
||||
};
|
||||
4302
asoc/codecs/lpass-cdc/lpass-cdc-rx-macro.c
Normal file
4302
asoc/codecs/lpass-cdc/lpass-cdc-rx-macro.c
Normal file
File diff suppressed because it is too large
Load Diff
982
asoc/codecs/lpass-cdc/lpass-cdc-tables.c
Normal file
982
asoc/codecs/lpass-cdc/lpass-cdc-tables.c
Normal file
@@ -0,0 +1,982 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include "lpass-cdc.h"
|
||||
#include "internal.h"
|
||||
|
||||
u8 lpass_cdc_tx_reg_access[LPASS_CDC_TX_MACRO_MAX] = {
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_ANC_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_FREQ_MCLK)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_CLK)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_RESET)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_CLK_RESET_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_2_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_SHIFT)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_SHIFT)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_A_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_B_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FB_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_SMLPF_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_GAIN_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX4_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX5_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX6_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX7_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX4_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX4_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX4_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX4_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX4_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX4_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX4_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX4_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX4_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX4_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX4_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX5_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX5_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX5_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX5_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX5_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX5_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX5_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX5_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX5_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX5_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX5_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX6_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX6_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX6_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX6_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX6_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX6_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX6_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX6_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX6_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX6_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX6_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX7_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX7_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX7_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX7_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX7_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX7_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX7_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX7_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX7_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX7_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX7_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
};
|
||||
|
||||
u8 lpass_cdc_tx_reg_access_v2[LPASS_CDC_TX_MACRO_MAX] = {
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_ANC_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_FREQ_MCLK)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_CLK)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_I2S_RESET)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC0_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC2_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_DMIC3_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC0_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_TOP_CSR_SWR_AMIC1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_CLK_RESET_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_MODE_2_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_SHIFT)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_SHIFT)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_A_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FF_B_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_LPF_FB_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_SMLPF_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_DCFLT_SHIFT_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_ADAPT_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_IIR_COEFF_2_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_A_GAIN_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FF_B_GAIN_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_ANC0_FB_GAIN_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX0_TX_PATH_SEC7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX1_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX2_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_TX3_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
};
|
||||
|
||||
u8 lpass_cdc_rx_reg_access[LPASS_CDC_RX_MACRO_MAX] = {
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_TOP_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_SWR_CTRL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DEBUG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DEBUG_BUS)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DEBUG_EN0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DEBUG_EN1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DEBUG_EN2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_HPHL_COMP_WR_LSB)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_HPHL_COMP_WR_MSB)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_HPHL_COMP_LUT)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_HPHL_COMP_RD_LSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_HPHL_COMP_RD_MSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_HPHR_COMP_WR_LSB)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_HPHR_COMP_WR_MSB)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_HPHR_COMP_LUT)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_HPHR_COMP_RD_LSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_HPHR_COMP_RD_MSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG2)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DSD0_DEBUG_CFG3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG2)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_DSD1_DEBUG_CFG3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_RX_I2S_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_TX_I2S2_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_I2S_CLK)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_I2S_RESET)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_TOP_I2S_MUX)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLK_RST_CTRL_DSD_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SOFTCLIP_CRC)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SOFTCLIP_SOFTCLIP_CTRL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INP_MUX_RX_INT0_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INP_MUX_RX_INT0_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INP_MUX_RX_INT1_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INP_MUX_RX_INT1_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INP_MUX_RX_INT2_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INP_MUX_RX_INT2_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INP_MUX_RX_MIX_CFG4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INP_MUX_RX_MIX_CFG5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_CRC)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_DLY_CTRL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_DECAY_CTRL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_HPH_V_PA)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_EAR_V_PA)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_HPH_V_HD)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_EAR_V_HD)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_K1_MSB)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_K1_LSB)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_K2_MSB)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_K2_LSB)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_IDLE_CTRL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_IDLE_HPH)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_IDLE_EAR)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_TEST0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_TEST1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_OVR_VREF)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_CLSG_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_CLSG_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_CLSH_CLSG_CFG2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ADC_CAL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ADC_CAL2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ADC_CAL3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_PK_EST1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_PK_EST2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_PK_EST3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_RF_PROC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_RF_PROC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_TAC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_TAC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_TAC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_TAC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_GAIN_UPD1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_GAIN_UPD2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_GAIN_UPD3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_GAIN_UPD4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_GAIN_UPD5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DEBUG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_GAIN_UPD_MON)] = WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_GAIN_MON_VAL)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_BAN)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ATTN1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ATTN2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_ATTN3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CTL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CTL2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_CFG4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_BCL_VBAT_DECODE_ST)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_CLR_COMMIT)] = WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_PIN1_MASK0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_PIN1_STATUS0)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_PIN1_CLEAR0)] = WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_PIN2_MASK0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_PIN2_STATUS0)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_PIN2_CLEAR0)] = WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_LEVEL0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_BYPASS0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_INTR_CTRL_SET0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_CFG2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_CFG3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_MIX_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_MIX_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_VOL_MIX_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_SEC7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_MIX_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_MIX_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX0_RX_PATH_DSM_DATA6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_CFG3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_MIX_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_MIX_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_VOL_MIX_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_SEC7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_MIX_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX1_RX_PATH_DSM_DATA6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_CFG3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_VOL_MIX_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_SEC7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_MIX_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_RX2_RX_PATH_DSM_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_IDLE_DETECT_CFG3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL6)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER0_CTL7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL6)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_COMPANDER1_CTL7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL)] =
|
||||
RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR1_IIR_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL)] =
|
||||
RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC0_CLK_RST_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC0_CTL0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC0_CTL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC0_FIFO_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC0_STATUS_FIFO)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC1_CLK_RST_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC1_CTL0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC1_CTL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC1_FIFO_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC1_STATUS_FIFO)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC2_CLK_RST_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC2_CTL0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC2_CTL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC2_FIFO_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_EC_ASRC2_STATUS_FIFO)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_DSD0_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_DSD0_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_DSD0_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_DSD0_CFG2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_DSD1_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_DSD1_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_DSD1_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_RX_DSD1_CFG2)] = RD_WR_REG,
|
||||
};
|
||||
|
||||
u8 lpass_cdc_va_reg_access[LPASS_CDC_VA_MACRO_MAX] = {
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC2_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC3_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_CLK)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_RESET)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX4_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX5_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX6_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX7_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX4_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX5_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX6_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX7_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
};
|
||||
|
||||
u8 lpass_cdc_va_top_reg_access[LPASS_CDC_VA_MACRO_TOP_MAX] = {
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG,
|
||||
};
|
||||
|
||||
u8 lpass_cdc_va_reg_access_v2[LPASS_CDC_VA_MACRO_MAX] = {
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC2_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC3_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_CLK)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_RESET)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
};
|
||||
|
||||
u8 lpass_cdc_va_reg_access_v3[LPASS_CDC_VA_MACRO_MAX] = {
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TOP_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC0_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC1_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC2_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC3_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DMIC_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_BUS)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_DEBUG_EN)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_TX_I2S_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_CLK)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_I2S_RESET)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_0)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_1)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_2)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_CORE_ID_3)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_MIC_CTL2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TOP_CSR_SWR_CTRL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX0_TX_PATH_SEC7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX1_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX2_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_VA_TX3_TX_PATH_SEC6)] = RD_WR_REG,
|
||||
};
|
||||
|
||||
u8 lpass_cdc_wsa_reg_access[LPASS_CDC_WSA_MACRO_MAX] = {
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_CLK_RST_CTRL_SWR_CONTROL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_TOP_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_TOP_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_FREQ_MCLK)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_DEBUG_BUS_SEL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_DEBUG_EN0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_DEBUG_EN1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_DEBUG_DSM_LB)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_RX_I2S_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_TX_I2S_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_I2S_CLK)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TOP_I2S_RESET)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_RX_EC_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_PK_EST1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_PK_EST2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_PK_EST3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_RF_PROC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_RF_PROC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_TAC4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DEBUG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD_MON)] = WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BAN)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD8)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD9)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TX1_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TX2_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TX2_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TX3_SPKR_PROT_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_TX3_SPKR_PROT_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_INTR_CTRL_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_INTR_CTRL_CLR_COMMIT)] = WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_INTR_CTRL_PIN1_MASK0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_INTR_CTRL_PIN1_STATUS0)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_INTR_CTRL_PIN1_CLEAR0)] = WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_INTR_CTRL_PIN2_MASK0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_INTR_CTRL_PIN2_STATUS0)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_INTR_CTRL_PIN2_CLEAR0)] = WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_INTR_CTRL_LEVEL0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_INTR_CTRL_BYPASS0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_INTR_CTRL_SET0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_CFG2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_CFG3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_MIX_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_MIX_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_VOL_MIX_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_SEC7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_MIX_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_MIX_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX0_RX_PATH_DSMDEM_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_CFG2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_CFG3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_VOL_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_MIX_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_MIX_CFG)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_VOL_MIX_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_SEC2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_SEC3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_SEC5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_SEC6)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_SEC7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_MIX_SEC0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_MIX_SEC1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_RX1_RX_PATH_DSMDEM_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_BOOST0_BOOST_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_BOOST0_BOOST_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_BOOST0_BOOST_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_BOOST0_BOOST_CFG2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_BOOST1_BOOST_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_BOOST1_BOOST_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_BOOST1_BOOST_CFG1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_BOOST1_BOOST_CFG2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL6)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER0_CTL7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL2)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL3)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL4)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL5)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL6)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_COMPANDER1_CTL7)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SOFTCLIP0_CRC)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SOFTCLIP1_CRC)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_CTL0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_CTL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_FIFO_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_CTL0)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_CTL1)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_FIFO_CTL)] = RD_WR_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB)] = RD_REG,
|
||||
[LPASS_CDC_REG(LPASS_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO)] = RD_REG,
|
||||
};
|
||||
|
||||
u8 *lpass_cdc_reg_access[MAX_MACRO] = {
|
||||
[TX_MACRO] = lpass_cdc_tx_reg_access,
|
||||
[RX_MACRO] = lpass_cdc_rx_reg_access,
|
||||
[WSA_MACRO] = lpass_cdc_wsa_reg_access,
|
||||
[VA_MACRO] = lpass_cdc_va_reg_access,
|
||||
};
|
||||
3518
asoc/codecs/lpass-cdc/lpass-cdc-tx-macro.c
Normal file
3518
asoc/codecs/lpass-cdc/lpass-cdc-tx-macro.c
Normal file
File diff suppressed because it is too large
Load Diff
172
asoc/codecs/lpass-cdc/lpass-cdc-utils.c
Normal file
172
asoc/codecs/lpass-cdc/lpass-cdc-utils.c
Normal file
@@ -0,0 +1,172 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/regmap.h>
|
||||
#include "lpass-cdc.h"
|
||||
#include "internal.h"
|
||||
|
||||
#define REG_BYTES 2
|
||||
#define VAL_BYTES 1
|
||||
|
||||
const u16 macro_id_base_offset[MAX_MACRO] = {
|
||||
TX_START_OFFSET,
|
||||
RX_START_OFFSET,
|
||||
WSA_START_OFFSET,
|
||||
VA_START_OFFSET,
|
||||
};
|
||||
|
||||
int lpass_cdc_get_macro_id(bool va_no_dec_flag, u16 reg)
|
||||
{
|
||||
if (reg >= TX_START_OFFSET
|
||||
&& reg <= TX_MAX_OFFSET)
|
||||
return TX_MACRO;
|
||||
if (reg >= RX_START_OFFSET
|
||||
&& reg <= RX_MAX_OFFSET)
|
||||
return RX_MACRO;
|
||||
if (reg >= WSA_START_OFFSET
|
||||
&& reg <= WSA_MAX_OFFSET)
|
||||
return WSA_MACRO;
|
||||
if (!va_no_dec_flag &&
|
||||
(reg >= VA_START_OFFSET &&
|
||||
reg <= VA_MAX_OFFSET))
|
||||
return VA_MACRO;
|
||||
if (va_no_dec_flag &&
|
||||
(reg >= VA_START_OFFSET &&
|
||||
reg <= VA_TOP_MAX_OFFSET))
|
||||
return VA_MACRO;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int regmap_bus_read(void *context, const void *reg, size_t reg_size,
|
||||
void *val, size_t val_size)
|
||||
{
|
||||
struct device *dev = context;
|
||||
struct lpass_cdc_priv *priv = dev_get_drvdata(dev);
|
||||
u16 *reg_p;
|
||||
u16 __reg;
|
||||
int macro_id, i;
|
||||
u8 temp = 0;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (!priv) {
|
||||
dev_err(dev, "%s: priv is NULL\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
if (!reg || !val) {
|
||||
dev_err(dev, "%s: reg or val is NULL\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
if (reg_size != REG_BYTES) {
|
||||
dev_err(dev, "%s: register size %zd bytes, not supported\n",
|
||||
__func__, reg_size);
|
||||
return ret;
|
||||
}
|
||||
|
||||
reg_p = (u16 *)reg;
|
||||
macro_id = lpass_cdc_get_macro_id(priv->va_without_decimation,
|
||||
reg_p[0]);
|
||||
if (macro_id < 0 || !priv->macros_supported[macro_id])
|
||||
return 0;
|
||||
|
||||
mutex_lock(&priv->io_lock);
|
||||
for (i = 0; i < val_size; i++) {
|
||||
__reg = (reg_p[0] + i * 4) - macro_id_base_offset[macro_id];
|
||||
ret = priv->read_dev(priv, macro_id, __reg, &temp);
|
||||
if (ret < 0) {
|
||||
dev_err_ratelimited(dev,
|
||||
"%s: Codec read failed (%d), reg: 0x%x, size:%zd\n",
|
||||
__func__, ret, reg_p[0] + i * 4, val_size);
|
||||
break;
|
||||
}
|
||||
((u8 *)val)[i] = temp;
|
||||
dev_dbg(dev, "%s: Read 0x%02x from reg 0x%x\n",
|
||||
__func__, temp, reg_p[0] + i * 4);
|
||||
}
|
||||
mutex_unlock(&priv->io_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int regmap_bus_gather_write(void *context,
|
||||
const void *reg, size_t reg_size,
|
||||
const void *val, size_t val_size)
|
||||
{
|
||||
struct device *dev = context;
|
||||
struct lpass_cdc_priv *priv = dev_get_drvdata(dev);
|
||||
u16 *reg_p;
|
||||
u16 __reg;
|
||||
int macro_id, i;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (!priv) {
|
||||
dev_err(dev, "%s: priv is NULL\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
if (!reg || !val) {
|
||||
dev_err(dev, "%s: reg or val is NULL\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
if (reg_size != REG_BYTES) {
|
||||
dev_err(dev, "%s: register size %zd bytes, not supported\n",
|
||||
__func__, reg_size);
|
||||
return ret;
|
||||
}
|
||||
|
||||
reg_p = (u16 *)reg;
|
||||
macro_id = lpass_cdc_get_macro_id(priv->va_without_decimation,
|
||||
reg_p[0]);
|
||||
if (macro_id < 0 || !priv->macros_supported[macro_id])
|
||||
return 0;
|
||||
|
||||
mutex_lock(&priv->io_lock);
|
||||
for (i = 0; i < val_size; i++) {
|
||||
__reg = (reg_p[0] + i * 4) - macro_id_base_offset[macro_id];
|
||||
ret = priv->write_dev(priv, macro_id, __reg, ((u8 *)val)[i]);
|
||||
if (ret < 0) {
|
||||
dev_err_ratelimited(dev,
|
||||
"%s: Codec write failed (%d), reg:0x%x, size:%zd\n",
|
||||
__func__, ret, reg_p[0] + i * 4, val_size);
|
||||
break;
|
||||
}
|
||||
dev_dbg(dev, "Write %02x to reg 0x%x\n", ((u8 *)val)[i],
|
||||
reg_p[0] + i * 4);
|
||||
}
|
||||
mutex_unlock(&priv->io_lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int regmap_bus_write(void *context, const void *data, size_t count)
|
||||
{
|
||||
struct device *dev = context;
|
||||
struct lpass_cdc_priv *priv = dev_get_drvdata(dev);
|
||||
|
||||
if (!priv)
|
||||
return -EINVAL;
|
||||
|
||||
if (count < REG_BYTES) {
|
||||
dev_err(dev, "%s: count %zd bytes < %d, not supported\n",
|
||||
__func__, count, REG_BYTES);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return regmap_bus_gather_write(context, data, REG_BYTES,
|
||||
data + REG_BYTES,
|
||||
count - REG_BYTES);
|
||||
}
|
||||
|
||||
static struct regmap_bus regmap_bus_config = {
|
||||
.write = regmap_bus_write,
|
||||
.gather_write = regmap_bus_gather_write,
|
||||
.read = regmap_bus_read,
|
||||
.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
|
||||
.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
|
||||
};
|
||||
|
||||
struct regmap *lpass_cdc_regmap_init(struct device *dev,
|
||||
const struct regmap_config *config)
|
||||
{
|
||||
return devm_regmap_init(dev, ®map_bus_config, dev, config);
|
||||
}
|
||||
3268
asoc/codecs/lpass-cdc/lpass-cdc-va-macro.c
Normal file
3268
asoc/codecs/lpass-cdc/lpass-cdc-va-macro.c
Normal file
File diff suppressed because it is too large
Load Diff
3323
asoc/codecs/lpass-cdc/lpass-cdc-wsa-macro.c
Normal file
3323
asoc/codecs/lpass-cdc/lpass-cdc-wsa-macro.c
Normal file
File diff suppressed because it is too large
Load Diff
41
asoc/codecs/lpass-cdc/lpass-cdc-wsa-macro.h
Normal file
41
asoc/codecs/lpass-cdc/lpass-cdc-wsa-macro.h
Normal file
@@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
#ifndef LPASS_CDC_WSA_MACRO_H
|
||||
#define LPASS_CDC_WSA_MACRO_H
|
||||
|
||||
/*
|
||||
* Selects compander and smart boost settings
|
||||
* for a given speaker mode
|
||||
*/
|
||||
enum {
|
||||
LPASS_CDC_WSA_MACRO_SPKR_MODE_DEFAULT,
|
||||
LPASS_CDC_WSA_MACRO_SPKR_MODE_1, /* COMP Gain = 12dB, Smartboost Max = 5.5V */
|
||||
};
|
||||
|
||||
/* Rx path gain offsets */
|
||||
enum {
|
||||
LPASS_CDC_WSA_MACRO_GAIN_OFFSET_M1P5_DB,
|
||||
LPASS_CDC_WSA_MACRO_GAIN_OFFSET_0_DB,
|
||||
};
|
||||
|
||||
|
||||
#if IS_ENABLED(CONFIG_WSA_MACRO)
|
||||
extern int lpass_cdc_wsa_macro_set_spkr_mode(struct snd_soc_component *component,
|
||||
int mode);
|
||||
extern int lpass_cdc_wsa_macro_set_spkr_gain_offset(struct snd_soc_component *component,
|
||||
int offset);
|
||||
#else /* CONFIG_WSA_MACRO */
|
||||
static inline int lpass_cdc_wsa_macro_set_spkr_mode(struct snd_soc_component *component,
|
||||
int mode)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int lpass_cdc_wsa_macro_set_spkr_gain_offset(
|
||||
struct snd_soc_component *component,
|
||||
int offset)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_WSA_MACRO */
|
||||
#endif
|
||||
1546
asoc/codecs/lpass-cdc/lpass-cdc.c
Normal file
1546
asoc/codecs/lpass-cdc/lpass-cdc.c
Normal file
File diff suppressed because it is too large
Load Diff
206
asoc/codecs/lpass-cdc/lpass-cdc.h
Normal file
206
asoc/codecs/lpass-cdc/lpass-cdc.h
Normal file
@@ -0,0 +1,206 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef LPASS_CDC_H
|
||||
#define LPASS_CDC_H
|
||||
|
||||
#include <sound/soc.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#define LPASS_CDC_VERSION_1_0 0x0001
|
||||
#define LPASS_CDC_VERSION_1_1 0x0002
|
||||
#define LPASS_CDC_VERSION_1_2 0x0003
|
||||
#define LPASS_CDC_VERSION_2_0 0x0004
|
||||
#define LPASS_CDC_VERSION_2_1 0x0005
|
||||
|
||||
enum {
|
||||
START_MACRO,
|
||||
TX_MACRO = START_MACRO,
|
||||
RX_MACRO,
|
||||
WSA_MACRO,
|
||||
VA_MACRO,
|
||||
MAX_MACRO
|
||||
};
|
||||
|
||||
enum mclk_mux {
|
||||
MCLK_MUX0,
|
||||
MCLK_MUX1,
|
||||
MCLK_MUX_MAX
|
||||
};
|
||||
|
||||
enum {
|
||||
LPASS_CDC_ADC0 = 1,
|
||||
LPASS_CDC_ADC1,
|
||||
LPASS_CDC_ADC2,
|
||||
LPASS_CDC_ADC3,
|
||||
LPASS_CDC_ADC_MAX
|
||||
};
|
||||
|
||||
enum {
|
||||
LPASS_CDC_MACRO_EVT_RX_MUTE = 1, /* for RX mute/unmute */
|
||||
LPASS_CDC_MACRO_EVT_IMPED_TRUE, /* for imped true */
|
||||
LPASS_CDC_MACRO_EVT_IMPED_FALSE, /* for imped false */
|
||||
LPASS_CDC_MACRO_EVT_SSR_DOWN,
|
||||
LPASS_CDC_MACRO_EVT_SSR_UP,
|
||||
LPASS_CDC_MACRO_EVT_WAIT_VA_CLK_RESET,
|
||||
LPASS_CDC_MACRO_EVT_CLK_RESET,
|
||||
LPASS_CDC_MACRO_EVT_REG_WAKE_IRQ,
|
||||
LPASS_CDC_MACRO_EVT_RX_COMPANDER_SOFT_RST,
|
||||
LPASS_CDC_MACRO_EVT_BCS_CLK_OFF,
|
||||
LPASS_CDC_MACRO_EVT_SSR_GFMUX_UP,
|
||||
LPASS_CDC_MACRO_EVT_PRE_SSR_UP,
|
||||
LPASS_CDC_MACRO_EVT_RX_PA_GAIN_UPDATE,
|
||||
LPASS_CDC_MACRO_EVT_HPHL_HD2_ENABLE, /* Enable HD2 cfg for HPHL */
|
||||
LPASS_CDC_MACRO_EVT_HPHR_HD2_ENABLE, /* Enable HD2 cfg for HPHR */
|
||||
};
|
||||
|
||||
enum {
|
||||
DMIC_TX = 0,
|
||||
DMIC_VA = 1,
|
||||
|
||||
};
|
||||
|
||||
struct macro_ops {
|
||||
int (*init)(struct snd_soc_component *component);
|
||||
int (*exit)(struct snd_soc_component *component);
|
||||
u16 num_dais;
|
||||
struct device *dev;
|
||||
struct snd_soc_dai_driver *dai_ptr;
|
||||
int (*mclk_fn)(struct device *dev, bool enable);
|
||||
int (*event_handler)(struct snd_soc_component *component, u16 event,
|
||||
u32 data);
|
||||
int (*reg_wake_irq)(struct snd_soc_component *component, u32 data);
|
||||
int (*set_port_map)(struct snd_soc_component *component, u32 uc,
|
||||
u32 size, void *data);
|
||||
int (*clk_div_get)(struct snd_soc_component *component);
|
||||
int (*reg_evt_listener)(struct snd_soc_component *component, bool en);
|
||||
int (*clk_enable)(struct snd_soc_component *c, bool en);
|
||||
char __iomem *io_base;
|
||||
u16 clk_id_req;
|
||||
u16 default_clk_id;
|
||||
};
|
||||
|
||||
typedef int (*rsc_clk_cb_t)(struct device *dev, u16 event);
|
||||
|
||||
#if IS_ENABLED(CONFIG_SND_SOC_LPASS_CDC)
|
||||
int lpass_cdc_register_res_clk(struct device *dev, rsc_clk_cb_t cb);
|
||||
void lpass_cdc_unregister_res_clk(struct device *dev);
|
||||
bool lpass_cdc_is_va_macro_registered(struct device *dev);
|
||||
int lpass_cdc_register_macro(struct device *dev, u16 macro_id,
|
||||
struct macro_ops *ops);
|
||||
void lpass_cdc_unregister_macro(struct device *dev, u16 macro_id);
|
||||
struct device *lpass_cdc_get_device_ptr(struct device *dev, u16 macro_id);
|
||||
struct device *lpass_cdc_get_rsc_clk_device_ptr(struct device *dev);
|
||||
int lpass_cdc_info_create_codec_entry(
|
||||
struct snd_info_entry *codec_root,
|
||||
struct snd_soc_component *component);
|
||||
int lpass_cdc_register_wake_irq(struct snd_soc_component *component, u32 data);
|
||||
void lpass_cdc_clear_amic_tx_hold(struct device *dev, u16 adc_n);
|
||||
int lpass_cdc_runtime_resume(struct device *dev);
|
||||
int lpass_cdc_runtime_suspend(struct device *dev);
|
||||
int lpass_cdc_set_port_map(struct snd_soc_component *component, u32 size, void *data);
|
||||
int lpass_cdc_register_event_listener(struct snd_soc_component *component,
|
||||
bool enable);
|
||||
void lpass_cdc_wsa_pa_on(struct device *dev, bool adie_lb);
|
||||
bool lpass_cdc_check_core_votes(struct device *dev);
|
||||
int lpass_cdc_tx_mclk_enable(struct snd_soc_component *c, bool enable);
|
||||
int lpass_cdc_get_version(struct device *dev);
|
||||
int lpass_cdc_dmic_clk_enable(struct snd_soc_component *component,
|
||||
u32 dmic, u32 tx_mode, bool enable);
|
||||
#else
|
||||
static inline int lpass_cdc_register_res_clk(struct device *dev, rsc_clk_cb_t cb)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline void lpass_cdc_unregister_res_clk(struct device *dev)
|
||||
{
|
||||
}
|
||||
|
||||
static bool lpass_cdc_is_va_macro_registered(struct device *dev)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline int lpass_cdc_register_macro(struct device *dev,
|
||||
u16 macro_id,
|
||||
struct macro_ops *ops)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void lpass_cdc_unregister_macro(struct device *dev, u16 macro_id)
|
||||
{
|
||||
}
|
||||
|
||||
static inline struct device *lpass_cdc_get_device_ptr(struct device *dev,
|
||||
u16 macro_id)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int lpass_cdc_info_create_codec_entry(
|
||||
struct snd_info_entry *codec_root,
|
||||
struct snd_soc_component *component)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void lpass_cdc_clear_amic_tx_hold(struct device *dev, u16 adc_n)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int lpass_cdc_register_wake_irq(struct snd_soc_component *component,
|
||||
u32 data)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int lpass_cdc_runtime_resume(struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lpass_cdc_runtime_suspend(struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int lpass_cdc_set_port_map(struct snd_soc_component *component,
|
||||
u32 size, void *data)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int lpass_cdc_register_event_listener(
|
||||
struct snd_soc_component *component,
|
||||
bool enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void lpass_cdc_wsa_pa_on(struct device *dev, bool adie_lb)
|
||||
{
|
||||
}
|
||||
|
||||
static inline bool lpass_cdc_check_core_votes(struct device *dev)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static int lpass_cdc_get_version(struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lpass_cdc_dmic_clk_enable(struct snd_soc_component *component,
|
||||
u32 dmic, u32 tx_mode, bool enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static int lpass_cdc_tx_mclk_enable(struct snd_soc_component *c, bool enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_SND_SOC_LPASS_CDC */
|
||||
#endif /* LPASS_CDC_H */
|
||||
Reference in New Issue
Block a user