disp: msm: sde: fix dsc/vdc register dump

DSC and VDC-M sub-block registers are not on contiguous
address range. This change allows dumping the registers
for each individual sub-block.

Change-Id: I06dfc64562211370a0e29f6fc1134351c47722f6
Signed-off-by: Abhijit Kulkarni <[email protected]>

msm/sde/sde_hw_catalog.c

@@ -316,7 +316,9 @@ enum {
 	DSC_PAIR_MASK,
 	DSC_REV,
 	DSC_ENC,
+	DSC_ENC_LEN,
 	DSC_CTL,
+	DSC_CTL_LEN,
 	DSC_422,
 	DSC_PROP_MAX,
 };
@@ -326,7 +328,9 @@ enum {
 	VDC_LEN,
 	VDC_REV,
 	VDC_ENC,
+	VDC_ENC_LEN,
 	VDC_CTL,
+	VDC_CTL_LEN,
 	VDC_PROP_MAX,
 };
 
@@ -748,7 +752,9 @@ static struct sde_prop_type dsc_prop[] = {
 	{DSC_PAIR_MASK, "qcom,sde-dsc-pair-mask", false, PROP_TYPE_U32_ARRAY},
 	{DSC_REV, "qcom,sde-dsc-hw-rev", false, PROP_TYPE_STRING},
 	{DSC_ENC, "qcom,sde-dsc-enc", false, PROP_TYPE_U32_ARRAY},
+	{DSC_ENC_LEN, "qcom,sde-dsc-enc-size", false, PROP_TYPE_U32},
 	{DSC_CTL, "qcom,sde-dsc-ctl", false, PROP_TYPE_U32_ARRAY},
+	{DSC_CTL_LEN, "qcom,sde-dsc-ctl-size", false, PROP_TYPE_U32},
 	{DSC_422, "qcom,sde-dsc-native422-supp", false, PROP_TYPE_U32_ARRAY}
 };
 
@@ -757,7 +763,9 @@ static struct sde_prop_type vdc_prop[] = {
 	{VDC_LEN, "qcom,sde-vdc-size", false, PROP_TYPE_U32},
 	{VDC_REV, "qcom,sde-vdc-hw-rev", false, PROP_TYPE_STRING},
 	{VDC_ENC, "qcom,sde-vdc-enc", false, PROP_TYPE_U32_ARRAY},
+	{VDC_ENC_LEN, "qcom,sde-vdc-enc-size", false, PROP_TYPE_U32},
 	{VDC_CTL, "qcom,sde-vdc-ctl", false, PROP_TYPE_U32_ARRAY},
+	{VDC_CTL_LEN, "qcom,sde-vdc-ctl-size", false, PROP_TYPE_U32},
 };
 
 static struct sde_prop_type cdm_prop[] = {
@@ -2818,8 +2826,12 @@ static int sde_dsc_parse_dt(struct device_node *np,
 		if (dsc_rev == SDE_DSC_HW_REV_1_2) {
 			sblk->enc.base = PROP_VALUE_ACCESS(prop_value,
 					DSC_ENC, i);
+			sblk->enc.len = PROP_VALUE_ACCESS(prop_value,
+					DSC_ENC_LEN, 0);
 			sblk->ctl.base = PROP_VALUE_ACCESS(prop_value,
 					DSC_CTL, i);
+			sblk->ctl.len = PROP_VALUE_ACCESS(prop_value,
+					DSC_CTL_LEN, 0);
 			set_bit(SDE_DSC_HW_REV_1_2, &dsc->features);
 			if (PROP_VALUE_ACCESS(prop_value, DSC_422, i))
 					set_bit(SDE_DSC_NATIVE_422_EN,
@@ -2904,8 +2916,12 @@ static int sde_vdc_parse_dt(struct device_node *np,
 
 		sblk->enc.base = PROP_VALUE_ACCESS(prop_value,
 			VDC_ENC, i);
+		sblk->enc.len = PROP_VALUE_ACCESS(prop_value,
+			VDC_ENC_LEN, 0);
 		sblk->ctl.base = PROP_VALUE_ACCESS(prop_value,
 			VDC_CTL, i);
+		sblk->ctl.len = PROP_VALUE_ACCESS(prop_value,
+			VDC_CTL_LEN, 0);
 		set_bit(SDE_VDC_HW_REV_1_1, &vdc->features);
 	}
 

msm/sde/sde_hw_dsc.c

@@ -240,8 +240,50 @@ struct sde_hw_dsc *sde_hw_dsc_init(enum sde_dsc idx,
 	c->caps = cfg;
 	if (test_bit(SDE_DSC_HW_REV_1_1, &c->caps->features)) {
 		_setup_dsc_ops(&c->ops, c->caps->features);
+		sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
+				c->hw.blk_off,
+				c->hw.blk_off + c->hw.length,
+				c->hw.xin_id);
+
+		if ((c->idx == DSC_0) &&
+				test_bit(SDE_DSC_OUTPUT_CTRL, &cfg->features)) {
+			dsc_ctl_offset = DSC_CTL(c->idx);
+			sde_dbg_reg_register_dump_range(SDE_DBG_NAME,
+					"dsc_ctl",
+					c->hw.blk_off + dsc_ctl_offset,
+					c->hw.blk_off + dsc_ctl_offset +
+						DSC_CTL_BLOCK_SIZE,
+					c->hw.xin_id);
+		}
 	} else if (test_bit(SDE_DSC_HW_REV_1_2, &c->caps->features)) {
+		char blk_name[32];
+
 		sde_dsc1_2_setup_ops(&c->ops, c->caps->features);
+
+		sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
+				c->hw.blk_off,
+				c->hw.blk_off + c->hw.length,
+				c->hw.xin_id);
+
+		snprintf(blk_name, sizeof(blk_name), "dsc_enc_%u",
+				c->idx - DSC_0);
+
+		sde_dbg_reg_register_dump_range(SDE_DBG_NAME,
+				blk_name,
+				c->hw.blk_off + c->caps->sblk->enc.base,
+				c->hw.blk_off + c->caps->sblk->enc.base +
+				c->caps->sblk->enc.len,
+				c->hw.xin_id);
+
+		snprintf(blk_name, sizeof(blk_name), "dsc_ctl_%u",
+				c->idx - DSC_0);
+
+		sde_dbg_reg_register_dump_range(SDE_DBG_NAME,
+				blk_name,
+				c->hw.blk_off + c->caps->sblk->ctl.base,
+				c->hw.blk_off + c->caps->sblk->ctl.base +
+					c->caps->sblk->ctl.len,
+				c->hw.xin_id);
 	} else {
 		SDE_ERROR("failed to setup ops\n");
 		goto blk_init_error;
@@ -253,17 +295,7 @@ struct sde_hw_dsc *sde_hw_dsc_init(enum sde_dsc idx,
 		goto blk_init_error;
 	}
 
-	sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
-		c->hw.blk_off + c->hw.length, c->hw.xin_id);
 
-	if ((c->idx == DSC_0) &&
-			test_bit(SDE_DSC_OUTPUT_CTRL, &cfg->features)) {
-		dsc_ctl_offset = DSC_CTL(c->idx);
-		sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "dsc_ctl",
-			c->hw.blk_off + dsc_ctl_offset,
-			c->hw.blk_off + dsc_ctl_offset + DSC_CTL_BLOCK_SIZE,
-			c->hw.xin_id);
-	}
 
 	return c;
 

msm/sde/sde_hw_vdc.c

@@ -398,6 +398,7 @@ struct sde_hw_vdc *sde_hw_vdc_init(enum sde_vdc idx,
 	struct sde_vdc_cfg *cfg;
 	int rc;
 	u32 vdc_ctl_reg;
+	char blk_name[32];
 
 	c = kzalloc(sizeof(*c), GFP_KERNEL);
 	if (!c)
@@ -420,21 +421,34 @@ struct sde_hw_vdc *sde_hw_vdc_init(enum sde_vdc idx,
 		goto blk_init_error;
 	}
 
-	sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
-		c->hw.blk_off + c->hw.length, c->hw.xin_id);
-
 	if (_vdc_subblk_offset(c, SDE_VDC_CTL, &vdc_ctl_reg)) {
 		SDE_ERROR("vdc ctl not found\n");
 		kfree(c);
 		return ERR_PTR(-EINVAL);
 	}
 
-	if (c->idx == VDC_0) {
-		sde_dbg_reg_register_dump_range(SDE_DBG_NAME, "vdc_ctl",
-				vdc_ctl_reg,
-				vdc_ctl_reg + VDC_CTL_BLOCK_SIZE,
-				c->hw.xin_id);
-	}
+	sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
+		c->hw.blk_off + c->hw.length, c->hw.xin_id);
+
+	snprintf(blk_name, sizeof(blk_name), "vdc_enc_%u",
+			c->idx - VDC_0);
+
+	sde_dbg_reg_register_dump_range(SDE_DBG_NAME,
+			blk_name,
+			c->hw.blk_off + c->caps->sblk->enc.base,
+			c->hw.blk_off + c->caps->sblk->enc.base +
+			c->caps->sblk->enc.len,
+			c->hw.xin_id);
+
+	snprintf(blk_name, sizeof(blk_name), "vdc_ctl_%u",
+			c->idx - VDC_0);
+
+	sde_dbg_reg_register_dump_range(SDE_DBG_NAME,
+			blk_name,
+			c->hw.blk_off + c->caps->sblk->ctl.base,
+			c->hw.blk_off + c->caps->sblk->ctl.base +
+			c->caps->sblk->ctl.len,
+			c->hw.xin_id);
 
 	return c;