msm: camera: isp: Add error irq and debug logs in CSID

Overflow error irq are not enabled. Debug logs are missing
in dual sync function.

This commit:
Adds error irq mask in CSID.
Enables overflow errors and mup frame drop.
Adds logs for dual sync configurations.
Changes return value to IRQ_HANDLED in path bottom_half.
Optimizes function to print path irq status.

CRs-Fixed: 2830502
Change-Id: I6d03ee659082769152cb1ac14a5486e03c273289
Signed-off-by: Gaurav Jindal <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid680.h

@@ -201,7 +201,7 @@ static struct cam_ife_csid_ver2_pxl_reg_info
 		.lut_bank_0_sel_val               = 0,
 		.lut_bank_1_sel_val               = 1,
 		.fatal_err_mask                   = 0x4,
-		.non_fatal_err_mask               = 0x28000,
+		.non_fatal_err_mask               = 0x10080000,
 		.camif_irq_mask                   = 0x800000,
 		.rup_aup_mask                     = 0x10001,
 };
@@ -297,7 +297,7 @@ static struct cam_ife_csid_ver2_pxl_reg_info
 		.lut_bank_0_sel_val               = 0,
 		.lut_bank_1_sel_val               = 1,
 		.fatal_err_mask                   = 0x4,
-		.non_fatal_err_mask               = 0x28000,
+		.non_fatal_err_mask               = 0x10080000,
 		.rup_aup_mask                     = 0x40004,
 };
 
@@ -389,7 +389,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
 		.stripe_loc_shift_val             = 20,
 		.ccif_violation_en                = 1,
 		.fatal_err_mask                   = 0x4,
-		.non_fatal_err_mask               = 0x28000,
+		.non_fatal_err_mask               = 0x10080000,
 		.camif_irq_mask                   = 0x800000,
 		.rup_aup_mask                     = 0x100010,
 };
@@ -481,7 +481,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
 		.stripe_loc_shift_val             = 20,
 		.ccif_violation_en                = 1,
 		.fatal_err_mask                   = 0x4,
-		.non_fatal_err_mask               = 0x28000,
+		.non_fatal_err_mask               = 10080000,
 		.camif_irq_mask                   = 0x800000,
 		.rup_aup_mask                     = 0x200020,
 };
@@ -573,7 +573,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
 		.stripe_loc_shift_val             = 20,
 		.ccif_violation_en                = 1,
 		.fatal_err_mask                   = 0x4,
-		.non_fatal_err_mask               = 0x28000,
+		.non_fatal_err_mask               = 10080000,
 		.camif_irq_mask                   = 0x800000,
 		.rup_aup_mask                     = 0x400040,
 };
@@ -665,7 +665,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
 		.stripe_loc_shift_val             = 20,
 		.ccif_violation_en                = 1,
 		.fatal_err_mask                   = 0x4,
-		.non_fatal_err_mask               = 0x28000,
+		.non_fatal_err_mask               = 10080000,
 		.camif_irq_mask                   = 0x800000,
 		.rup_aup_mask                     = 0x800080,
 };
@@ -757,7 +757,7 @@ static struct cam_ife_csid_ver2_rdi_reg_info
 		.stripe_loc_shift_val            = 20,
 		.ccif_violation_en               = 1,
 		.fatal_err_mask                  = 0x4,
-		.non_fatal_err_mask              = 0x28000,
+		.non_fatal_err_mask              = 10080000,
 		.camif_irq_mask                  = 0x800000,
 		.rup_aup_mask                    = 0x1000100,
 };

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c

@@ -131,6 +131,12 @@ static const struct cam_ife_csid_irq_desc ver2_rx_irq_desc[] = {
 };
 
 static const struct cam_ife_csid_irq_desc ver2_path_irq_desc[] = {
+	{
+		.desc = "",
+	},
+	{
+		.desc = "",
+	},
 	{
 		.desc = "ERROR_FIFO_OVERFLOW",
 	},
@@ -183,7 +189,7 @@ static const struct cam_ife_csid_irq_desc ver2_path_irq_desc[] = {
 		.desc = "FRAME_DROP",
 	},
 	{
-		.desc = "OVERFLOW",
+		.desc = "OVERFLOW_RECOVERY",
 	},
 	{
 		.desc = "ERROR_REC_CCIF_VIOLATION",
@@ -363,14 +369,14 @@ static int cam_ife_csid_ver2_path_top_half(
 
 	for (i = 0; i < th_payload->num_registers; i++)
 		CAM_DBG(CAM_ISP, "CSID:%d status_%d: 0x%X",
-			csid_hw->hw_intf->hw_idx,
+			csid_hw->hw_intf->hw_idx, i,
 			th_payload->evt_status_arr[i]);
 	if (rc) {
 		for (i = 0; i < th_payload->num_registers; i++)
 			CAM_INFO(CAM_ISP, "CSID:%d status_%d: 0x%X",
-				csid_hw->hw_intf->hw_idx,
+				csid_hw->hw_intf->hw_idx, i,
 				th_payload->evt_status_arr[i]);
-		return rc;
+		return IRQ_HANDLED;
 	}
 
 	for (i = 0; i < th_payload->num_registers; i++)
@@ -378,7 +384,7 @@ static int cam_ife_csid_ver2_path_top_half(
 
 	th_payload->evt_payload_priv = evt_payload;
 
-	return rc;
+	return IRQ_HANDLED;
 }
 
 static int cam_ife_csid_ver2_rx_err_top_half(
@@ -404,7 +410,7 @@ static int cam_ife_csid_ver2_rx_err_top_half(
 	if (rc) {
 		for (i = 0; i < th_payload->num_registers; i++)
 			CAM_INFO(CAM_ISP, "CSID:%d status_%d: 0x%X",
-				csid_hw->hw_intf->hw_idx,
+				csid_hw->hw_intf->hw_idx, i,
 				th_payload->evt_status_arr[i]);
 		return IRQ_HANDLED;
 	}
@@ -497,6 +503,7 @@ static int cam_ife_csid_ver2_handle_rx_debug_event(
 
 	return 0;
 }
+
 static int cam_ife_csid_ver2_rx_top_half(
 	uint32_t                                   evt_id,
 	struct cam_irq_th_payload                 *th_payload)
@@ -697,15 +704,14 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
 }
 
 static int cam_ife_csid_ver2_parse_path_irq_status(
-	uint32_t    index,
-	uint32_t    irq_status,
-	uint32_t    debug_mask,
-	uint32_t    err_mask,
-	uint32_t    hw_idx)
+	struct cam_ife_csid_ver2_hw *csid_hw,
+	uint32_t                     index,
+	uint32_t                     err_mask,
+	uint32_t                     irq_status)
 {
-	uint32_t bit_pos = 0;
-	uint32_t temp_status;
-	const uint8_t **irq_reg_tag;
+	const uint8_t                        **irq_reg_tag;
+	uint32_t                               bit_pos = 0;
+	uint32_t                               temp_status;
 
 	irq_reg_tag = cam_ife_csid_get_irq_reg_tag_ptr();
 	temp_status = irq_status & err_mask;
@@ -715,21 +721,22 @@ static int cam_ife_csid_ver2_parse_path_irq_status(
 		if (temp_status & 0x1)
 			CAM_ERR_RATE_LIMIT(CAM_ISP,
 				"CSID[%d] IRQ %s %s ",
-				hw_idx, irq_reg_tag[index],
+				csid_hw->hw_intf->hw_idx, irq_reg_tag[index],
 				ver2_path_irq_desc[bit_pos].desc);
 
 		bit_pos++;
 		temp_status >>= 1;
 	}
 
-	temp_status = irq_status & debug_mask;
+	temp_status = irq_status & csid_hw->debug_info.path_mask;
 	bit_pos = 0;
+
 	while (temp_status) {
 
 		if (temp_status & 0x1)
 			CAM_INFO_RATE_LIMIT(CAM_ISP,
 				"CSID[%d] IRQ %s %s ",
-				hw_idx, irq_reg_tag[index],
+				csid_hw->hw_intf->hw_idx, irq_reg_tag[index],
 				ver2_path_irq_desc[bit_pos].desc);
 
 		bit_pos++;
@@ -801,11 +808,9 @@ static int cam_ife_csid_ver2_ipp_bottom_half(
 			csid_reg->ipp_reg->non_fatal_err_mask;
 
 	cam_ife_csid_ver2_parse_path_irq_status(
+		csid_hw,
 		CAM_IFE_CSID_IRQ_REG_IPP,
-		irq_status_ipp,
-		csid_hw->debug_info.path_mask,
-		err_mask,
-		csid_hw->hw_intf->hw_idx);
+		err_mask, irq_status_ipp);
 
 	cam_ife_csid_ver2_put_evt_payload(csid_hw, &payload,
 			&csid_hw->path_free_payload_list,
@@ -841,11 +846,8 @@ static int cam_ife_csid_ver2_ppp_bottom_half(
 			csid_reg->ppp_reg->non_fatal_err_mask;
 
 	cam_ife_csid_ver2_parse_path_irq_status(
-		CAM_IFE_CSID_IRQ_REG_PPP,
-		irq_status_ppp,
-		csid_hw->debug_info.path_mask,
-		err_mask,
-		csid_hw->hw_intf->hw_idx);
+		csid_hw, CAM_IFE_CSID_IRQ_REG_PPP,
+		err_mask, irq_status_ppp);
 
 	cam_ife_csid_ver2_put_evt_payload(csid_hw, &payload,
 			&csid_hw->path_free_payload_list,
@@ -909,11 +911,8 @@ static int cam_ife_csid_ver2_rdi_bottom_half(
 		if (!path_cfg->handle_camif_irq) {
 			err_mask = rdi_reg->non_fatal_err_mask |
 					rdi_reg->fatal_err_mask;
-			cam_ife_csid_ver2_parse_path_irq_status(i,
-				irq_status_rdi,
-				csid_hw->debug_info.path_mask,
-				err_mask,
-				csid_hw->hw_intf->hw_idx);
+			cam_ife_csid_ver2_parse_path_irq_status(csid_hw, i,
+				err_mask, irq_status_rdi);
 			continue;
 		}
 
@@ -3190,6 +3189,10 @@ static int cam_ife_csid_ver2_top_cfg(
 
 	csid_hw->top_cfg.dual_en = true;
 	csid_hw->top_cfg.dual_sync_core_sel = csid_hw->dual_core_idx + 1;
+	CAM_DBG(CAM_ISP,
+		"CSID[%u] Top dual sync config core_sel: %d sync_mode: %d",
+		hw_idx, csid_hw->sync_mode,
+		csid_hw->top_cfg.dual_sync_core_sel);
 
 	return rc;
 }
@@ -3565,6 +3568,10 @@ static int cam_ife_csid_ver2_dual_sync_cfg(
 	csid_hw->sync_mode = dual_sync_args->sync_mode;
 	csid_hw->dual_core_idx = dual_sync_args->dual_core_id;
 
+	CAM_DBG(CAM_ISP, "CSID[%u] sync_mode %d dual_core_idx: %d",
+		csid_hw->hw_intf->hw_idx, csid_hw->sync_mode,
+		csid_hw->dual_core_idx);
+
 	return 0;
 }
 

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h

@@ -40,8 +40,6 @@
 
 #define CAM_IFE_CSID_VER2_PAYLOAD_MAX           256
 
-#define IFE_CSID_VER2_TOP_IRQ_DONE                               BIT(0)
-#define IFE_CSID_VER2_PATH_INFO_RST_DONE                         BIT(1)
 #define IFE_CSID_VER2_PATH_ERROR_FIFO_OVERFLOW                   BIT(2)
 #define IFE_CSID_VER2_PATH_CAMIF_EOF                             BIT(3)
 #define IFE_CSID_VER2_PATH_CAMIF_SOF                             BIT(4)
@@ -59,7 +57,7 @@
 #define IFE_CSID_VER2_PATH_VCDT_GRP1_SEL                         BIT(16)
 #define IFE_CSID_VER2_PATH_VCDT_GRP_CHANGE                       BIT(17)
 #define IFE_CSID_VER2_PATH_FRAME_DROP                            BIT(18)
-#define IFE_CSID_VER2_PATH_OVERFLOW                              BIT(19)
+#define IFE_CSID_VER2_PATH_OVERFLOW_RECOVERY                     BIT(19)
 #define IFE_CSID_VER2_PATH_ERROR_REC_CCIF_VIOLATION              BIT(20)
 #define IFE_CSID_VER2_PATH_CAMIF_EPOCH0                          BIT(21)
 #define IFE_CSID_VER2_PATH_CAMIF_EPOCH1                          BIT(22)