ASoC: lpass-cdc-clk: Update the clock enable sequence
Update the codec clock sequence as per the hardware recommendation to enable the codec clockes on the latest codec version. Change-Id: I1869d2b28c9aa79979f1aa3c85ca805cea3ef33b Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
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e3ab630202
کامیت
e264b147a5
@@ -16,17 +16,16 @@
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#define DRV_NAME "lpass-cdc-clk-rsc"
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#define LPASS_CDC_CLK_NAME_LENGTH 30
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#define NPL_CLK_OFFSET (TX_NPL_CLK - TX_CORE_CLK)
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static char clk_src_name[MAX_CLK][LPASS_CDC_CLK_NAME_LENGTH] = {
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"tx_core_clk",
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"rx_core_clk",
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"wsa_core_clk",
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"va_core_clk",
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"tx_npl_clk",
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"rx_npl_clk",
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"wsa_npl_clk",
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"va_npl_clk",
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"wsa2_core_clk",
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"rx_tx_core_clk",
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"wsa_tx_core_clk",
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"wsa2_tx_core_clk",
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};
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struct lpass_cdc_clk_rsc {
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@@ -86,10 +85,14 @@ static char __iomem *lpass_cdc_clk_rsc_get_clk_muxsel(struct lpass_cdc_clk_rsc *
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case RX_CORE_CLK:
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return priv->rx_clk_muxsel;
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case WSA_CORE_CLK:
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case WSA2_CORE_CLK:
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return priv->wsa_clk_muxsel;
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case VA_CORE_CLK:
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return priv->va_clk_muxsel;
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case TX_CORE_CLK:
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case RX_TX_CORE_CLK:
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case WSA_TX_CORE_CLK:
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case WSA2_TX_CORE_CLK:
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default:
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dev_err_ratelimited(priv->dev, "%s: Invalid case\n", __func__);
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break;
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@@ -109,7 +112,7 @@ int lpass_cdc_rsc_clk_reset(struct device *dev, int clk_id)
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return -EINVAL;
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}
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if (clk_id < 0 || clk_id >= MAX_CLK - NPL_CLK_OFFSET) {
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if (clk_id < 0 || clk_id >= MAX_CLK) {
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pr_err("%s: Invalid clk_id: %d\n",
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__func__, clk_id);
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return -EINVAL;
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@@ -128,7 +131,6 @@ int lpass_cdc_rsc_clk_reset(struct device *dev, int clk_id)
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}
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mutex_lock(&priv->rsc_clk_lock);
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while (__clk_is_enabled(priv->clk[clk_id])) {
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clk_disable_unprepare(priv->clk[clk_id + NPL_CLK_OFFSET]);
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clk_disable_unprepare(priv->clk[clk_id]);
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count++;
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}
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@@ -138,7 +140,6 @@ int lpass_cdc_rsc_clk_reset(struct device *dev, int clk_id)
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trace_printk("%s: clock reset after ssr, count %d\n", __func__, count);
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while (count--) {
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clk_prepare_enable(priv->clk[clk_id]);
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clk_prepare_enable(priv->clk[clk_id + NPL_CLK_OFFSET]);
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}
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mutex_unlock(&priv->rsc_clk_lock);
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return 0;
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@@ -168,17 +169,11 @@ void lpass_cdc_clk_rsc_enable_all_clocks(struct device *dev, bool enable)
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return;
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}
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mutex_lock(&priv->rsc_clk_lock);
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for (i = 0; i < MAX_CLK - NPL_CLK_OFFSET; i++) {
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for (i = 0; i < MAX_CLK; i++) {
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if (enable) {
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if (priv->clk[i])
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clk_prepare_enable(priv->clk[i]);
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if (priv->clk[i + NPL_CLK_OFFSET])
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clk_prepare_enable(
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priv->clk[i + NPL_CLK_OFFSET]);
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} else {
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if (priv->clk[i + NPL_CLK_OFFSET])
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clk_disable_unprepare(
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priv->clk[i + NPL_CLK_OFFSET]);
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if (priv->clk[i])
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clk_disable_unprepare(priv->clk[i]);
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}
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@@ -203,16 +198,6 @@ static int lpass_cdc_clk_rsc_mux0_clk_request(struct lpass_cdc_clk_rsc *priv,
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__func__, clk_id);
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goto done;
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}
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if (priv->clk[clk_id + NPL_CLK_OFFSET]) {
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ret = clk_prepare_enable(
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priv->clk[clk_id + NPL_CLK_OFFSET]);
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if (ret < 0) {
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dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
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__func__,
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clk_id + NPL_CLK_OFFSET);
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goto err;
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}
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}
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}
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priv->clk_cnt[clk_id]++;
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} else {
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@@ -223,17 +208,9 @@ static int lpass_cdc_clk_rsc_mux0_clk_request(struct lpass_cdc_clk_rsc *priv,
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goto done;
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}
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priv->clk_cnt[clk_id]--;
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if (priv->clk_cnt[clk_id] == 0) {
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if (priv->clk[clk_id + NPL_CLK_OFFSET])
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clk_disable_unprepare(
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priv->clk[clk_id + NPL_CLK_OFFSET]);
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if (priv->clk_cnt[clk_id] == 0)
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clk_disable_unprepare(priv->clk[clk_id]);
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}
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}
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return ret;
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err:
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clk_disable_unprepare(priv->clk[clk_id]);
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done:
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return ret;
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}
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@@ -255,13 +232,11 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
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if (enable) {
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if (priv->clk_cnt[clk_id] == 0) {
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if (clk_id != VA_CORE_CLK) {
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ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
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default_clk_id,
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true);
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if (ret < 0)
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goto done;
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}
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ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
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default_clk_id,
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true);
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if (ret < 0)
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goto done;
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ret = clk_prepare_enable(priv->clk[clk_id]);
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if (ret < 0) {
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@@ -269,34 +244,14 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
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__func__, clk_id);
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goto err_clk;
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}
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if (priv->clk[clk_id + NPL_CLK_OFFSET]) {
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ret = clk_prepare_enable(
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priv->clk[clk_id + NPL_CLK_OFFSET]);
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if (ret < 0) {
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dev_err_ratelimited(priv->dev, "%s:clk_id %d enable failed\n",
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__func__,
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clk_id + NPL_CLK_OFFSET);
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goto err_npl_clk;
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}
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}
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/*
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* Temp SW workaround to address a glitch issue of
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* VA GFMux instance responsible for switching from
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* TX MCLK to VA MCLK. This configuration would be taken
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* care in DSP itself
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*/
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if (clk_id != VA_CORE_CLK) {
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if (priv->dev_up_gfmux) {
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iowrite32(0x1, clk_muxsel);
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muxsel = ioread32(clk_muxsel);
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trace_printk("%s: muxsel value after enable: %d\n",
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__func__, muxsel);
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}
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lpass_cdc_clk_rsc_mux0_clk_request(priv,
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default_clk_id,
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false);
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if (priv->dev_up_gfmux) {
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iowrite32(0x1, clk_muxsel);
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muxsel = ioread32(clk_muxsel);
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trace_printk("%s: muxsel value after enable: %d\n",
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__func__, muxsel);
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}
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lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id,
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false);
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}
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priv->clk_cnt[clk_id]++;
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} else {
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@@ -308,46 +263,24 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
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}
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priv->clk_cnt[clk_id]--;
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if (priv->clk_cnt[clk_id] == 0) {
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if (clk_id != VA_CORE_CLK) {
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ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
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ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
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default_clk_id, true);
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if (!ret) {
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/*
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* Temp SW workaround to address a glitch issue
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* of VA GFMux instance responsible for
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* switching from TX MCLK to VA MCLK.
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* This configuration would be taken
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* care in DSP itself.
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*/
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if (priv->dev_up_gfmux) {
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iowrite32(0x0, clk_muxsel);
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muxsel = ioread32(clk_muxsel);
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trace_printk("%s: muxsel value after disable: %d\n",
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__func__, muxsel);
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}
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}
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if (!ret && priv->dev_up_gfmux) {
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iowrite32(0x0, clk_muxsel);
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muxsel = ioread32(clk_muxsel);
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trace_printk("%s: muxsel value after disable: %d\n",
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__func__, muxsel);
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}
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if (priv->clk[clk_id + NPL_CLK_OFFSET])
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clk_disable_unprepare(
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priv->clk[clk_id + NPL_CLK_OFFSET]);
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clk_disable_unprepare(priv->clk[clk_id]);
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if (clk_id != VA_CORE_CLK) {
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if (!ret)
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lpass_cdc_clk_rsc_mux0_clk_request(priv,
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default_clk_id, false);
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}
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if (!ret)
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lpass_cdc_clk_rsc_mux0_clk_request(priv,
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default_clk_id, false);
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}
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}
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return ret;
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err_npl_clk:
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clk_disable_unprepare(priv->clk[clk_id]);
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err_clk:
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if (clk_id != VA_CORE_CLK)
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lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
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lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
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done:
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return ret;
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}
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@@ -556,12 +489,10 @@ int lpass_cdc_clk_rsc_request_clock(struct device *dev,
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mux_switch = true;
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if (mux_switch) {
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if (clk_id_req != VA_CORE_CLK) {
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ret = lpass_cdc_clk_rsc_mux1_clk_request(priv, clk_id_req,
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ret = lpass_cdc_clk_rsc_mux1_clk_request(priv, clk_id_req,
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enable);
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if (ret < 0)
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goto err;
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}
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if (ret < 0)
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goto err;
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} else {
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ret = lpass_cdc_clk_rsc_mux0_clk_request(priv, clk_id_req, enable);
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if (ret < 0)
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@@ -664,6 +595,7 @@ static int lpass_cdc_clk_rsc_probe(struct platform_device *pdev)
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priv->clk[i] = clk;
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dev_dbg(&pdev->dev, "%s: clk get success for clk name %s\n",
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__func__, clk_src_name[i]);
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break;
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}
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}
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}
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