msm: camera: isp: Add check to dump supported fifo level registers in shima

Add check to dump supported debug register for shima target.
This change prevent unexpected behaviour during reading
unsupported fifo level register.

CRs-Fixed: 2770220
Change-Id: I33608e1ef92ca45acdc04667f61bb2d1536cbb8b
Signed-off-by: Chandan Kumar Jha <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.c

@@ -841,12 +841,22 @@ static void cam_vfe_camif_lite_print_status(uint32_t *status,
 	uint32_t bus_overflow_status = 0, status_0 = 0, status_2 = 0;
 	struct cam_vfe_soc_private *soc_private = NULL;
 	uint32_t val0, val1, val2, val3, val4;
+	uint32_t camera_hw_version;
+	int rc = 0;
+
+	val3 = val4 = 0;
 
 	if (!status) {
 		CAM_ERR(CAM_ISP, "Invalid params");
 		return;
 	}
 
+	rc = cam_cpas_get_cpas_hw_version(&camera_hw_version);
+	if (rc) {
+		CAM_ERR(CAM_ISP, "Failed to get HW version rc:%d", rc);
+		return;
+	}
+
 	bus_overflow_status = status[CAM_IFE_IRQ_BUS_OVERFLOW_STATUS];
 	violation_status = status[CAM_IFE_IRQ_VIOLATION_STATUS];
 	status_0 = status[CAM_IFE_IRQ_CAMIF_REG_STATUS0];
@@ -1010,10 +1020,13 @@ print_state:
 		CAM_CPAS_REG_CAMNOC, 0x1420, true, &val1);
 	cam_cpas_reg_read(soc_private->cpas_handle,
 		CAM_CPAS_REG_CAMNOC, 0x1A20, true, &val2);
-	cam_cpas_reg_read(soc_private->cpas_handle,
-		CAM_CPAS_REG_CAMNOC, 0x7620, true, &val3);
-	cam_cpas_reg_read(soc_private->cpas_handle,
-		CAM_CPAS_REG_CAMNOC, 0x7420, true, &val4);
+
+	if (camera_hw_version == CAM_CPAS_TITAN_580_V100) {
+		cam_cpas_reg_read(soc_private->cpas_handle,
+			CAM_CPAS_REG_CAMNOC, 0x7620, true, &val3);
+		cam_cpas_reg_read(soc_private->cpas_handle,
+			CAM_CPAS_REG_CAMNOC, 0x7420, true, &val4);
+	}
 
 	CAM_INFO(CAM_ISP,
 		"CAMNOC REG[Queued Pending] linear[%d %d] rdi0_wr[%d %d] ubwc_stats0[%d %d] ubwc_stats1[%d %d] rdi1_wr[%d %d]",

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c

@@ -916,12 +916,22 @@ static void cam_vfe_camif_ver3_print_status(uint32_t *status,
 	uint32_t bus_overflow_status = 0, status_0 = 0, status_2 = 0;
 	struct cam_vfe_soc_private *soc_private;
 	uint32_t val0, val1, val2, val3, val4;
+	uint32_t camera_hw_version;
+	int rc = 0;
+
+	val3 = val4 = 0;
 
 	if (!status) {
 		CAM_ERR(CAM_ISP, "Invalid params");
 		return;
 	}
 
+	rc = cam_cpas_get_cpas_hw_version(&camera_hw_version);
+	if (rc) {
+		CAM_ERR(CAM_ISP, "Failed to get HW version rc:%d", rc);
+		return;
+	}
+
 	bus_overflow_status = status[CAM_IFE_IRQ_BUS_OVERFLOW_STATUS];
 	status_0 = status[CAM_IFE_IRQ_CAMIF_REG_STATUS0];
 	status_2 = status[CAM_IFE_IRQ_CAMIF_REG_STATUS2];
@@ -1241,10 +1251,13 @@ print_state:
 		CAM_CPAS_REG_CAMNOC, 0x1420, true, &val1);
 	cam_cpas_reg_read(soc_private->cpas_handle,
 		CAM_CPAS_REG_CAMNOC, 0x1A20, true, &val2);
-	cam_cpas_reg_read(soc_private->cpas_handle,
-		CAM_CPAS_REG_CAMNOC, 0x7620, true, &val3);
-	cam_cpas_reg_read(soc_private->cpas_handle,
-		CAM_CPAS_REG_CAMNOC, 0x7420, true, &val4);
+
+	if (camera_hw_version == CAM_CPAS_TITAN_580_V100) {
+		cam_cpas_reg_read(soc_private->cpas_handle,
+			CAM_CPAS_REG_CAMNOC, 0x7620, true, &val3);
+		cam_cpas_reg_read(soc_private->cpas_handle,
+			CAM_CPAS_REG_CAMNOC, 0x7420, true, &val4);
+	}
 
 	CAM_INFO(CAM_ISP,
 		"CAMNOC REG[Queued Pending] linear[%d %d] rdi0_wr[%d %d] ubwc_stats0[%d %d] ubwc_stats1[%d %d] rdi1_wr[%d %d]",