disp: pll: fix sequence as per hardware recommendations
Update the PLL and PHY power on and clock set sequence as per the hardware recommendations. Move the post link clock phy enable part to the catalog so that it can be programmed after enabling link clock. Change-Id: I9b3b49e5a9ac93bebcb1cb7da63b715a8d5ed85c Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
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@@ -663,6 +663,10 @@ static int dp_ctrl_link_setup(struct dp_ctrl_private *ctrl, bool shallow)
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if (rc)
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break;
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ctrl->catalog->late_phy_init(ctrl->catalog,
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ctrl->link->link_params.lane_count,
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ctrl->orientation);
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dp_ctrl_configure_source_link_params(ctrl, true);
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rc = dp_ctrl_setup_main_link(ctrl);
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