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qcacmn: limit tx completion process count to napi quota

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Tx completion is processed in napi context, which should follow
napi's max quota, otherwise once process count is over napi quota,
it will trigger napi repoll in kernel, meanwhile by current design,
tx completion hard irq will be enabled when the 1st napi process
finished, in such case 2nd napi process will conflict with repoll process,
finally trigger kernel side napi list crash.

Since napi quota is used in serval cases, while for tx completion
process, we want to process tx completion count as many as possbile
in one cycle, set 64k transmit frames account for 1 napi work unit
to gain max tx kpi.

Change-Id: Ic24f131c90b90b0e118edffcab559ddf31779dcf
CRs-Fixed: 3421368
This commit is contained in:
Kai Liu
2023-03-01 19:40:22 +08:00
parent c042d60f04
commit e0657a969c
2 changed files with 12 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
dp/wifi3.0/dp_tx.c
View File

@@ -5648,6 +5648,7 @@ uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id]; struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
int max_reap_limit, ring_near_full; int max_reap_limit, ring_near_full;
uint32_t num_entries; uint32_t num_entries;
uint32_t rquota = quota;
DP_HIST_INIT(); DP_HIST_INIT();
@@ -5674,8 +5675,8 @@ more_data:
num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, num_avail_for_reap = hal_srng_dst_num_valid(hal_soc,
hal_ring_hdl, 0); hal_ring_hdl, 0);
if (num_avail_for_reap >= quota) if (num_avail_for_reap >= rquota)
num_avail_for_reap = quota; num_avail_for_reap = rquota;
dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap); dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc, last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
@@ -5863,8 +5864,10 @@ next_desc:
* *
* One more loop will move the state to normal processing and yield * One more loop will move the state to normal processing and yield
*/ */
if (ring_near_full) if (ring_near_full && rquota) {
rquota -= num_processed;
goto more_data; goto more_data;
}
if (dp_tx_comp_enable_eol_data_check(soc)) { if (dp_tx_comp_enable_eol_data_check(soc)) {
@@ -5876,8 +5879,10 @@ next_desc:
hal_ring_hdl)) { hal_ring_hdl)) {
DP_STATS_INC(soc, tx.hp_oos2, 1); DP_STATS_INC(soc, tx.hp_oos2, 1);
if (!hif_exec_should_yield(soc->hif_handle, if (!hif_exec_should_yield(soc->hif_handle,
int_ctx->dp_intr_id)) int_ctx->dp_intr_id)) {
rquota -= num_processed;
goto more_data; goto more_data;
}
num_avail_for_reap = num_avail_for_reap =
hal_srng_dst_num_valid_locked(soc->hal_soc, hal_srng_dst_num_valid_locked(soc->hal_soc,
@@ -5887,6 +5892,7 @@ next_desc:
(num_avail_for_reap >= (num_avail_for_reap >=
num_entries >> 1))) { num_entries >> 1))) {
DP_STATS_INC(soc, tx.near_full, 1); DP_STATS_INC(soc, tx.near_full, 1);
rquota -= num_processed;
goto more_data; goto more_data;
} }
} }

4
wlan_cfg/wlan_init_cfg.h
View File

@@ -1,6 +1,6 @@
/* /*
* Copyright (c) 2021 The Linux Foundation. All rights reserved. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* *
* Permission to use, copy, modify, and/or distribute this software for * Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the * any purpose with or without fee is hereby granted, provided that the
@@ -41,7 +41,7 @@
* This mask defines how many transmit frames account for 1 NAPI work unit * This mask defines how many transmit frames account for 1 NAPI work unit
* 0 means each tx completion is 1 unit * 0 means each tx completion is 1 unit
*/ */
#define DP_TX_NAPI_BUDGET_DIV_MASK 0 #define DP_TX_NAPI_BUDGET_DIV_MASK 0xffff
/* PPDU Stats Configuration - Configure bitmask for enabling tx ppdu tlv's */ /* PPDU Stats Configuration - Configure bitmask for enabling tx ppdu tlv's */
#define DP_PPDU_TXLITE_STATS_BITMASK_CFG 0x3FFF #define DP_PPDU_TXLITE_STATS_BITMASK_CFG 0x3FFF