video: driver: refine power settings
Added change to address below 2 issues. [1] buffer_counter is not getting incremented for batching usecase, it always runs with max clk and bus votes. So moved buffer_counter increment logic to msm_vidc_queue_buffer, so that it will be used for all usecases. [2] iris2 clock calculations were using core->capabilities but all needed infos were present in inst->capabilities. So junk values from core->capabilities was used in clock calculations and values always shooting to highest corner. Change-Id: I0927899244b5de2bd46d238100fdaecd78c6fe28 Signed-off-by: Govindaraj Rajagopal <grajagop@codeaurora.org>
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@@ -52,13 +52,13 @@ u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size)
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* Even though, most part is common now, in future it may change
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* between them.
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*/
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fw_cycles = fps * core->capabilities[MB_CYCLES_FW].value;
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fw_vpp_cycles = fps * core->capabilities[MB_CYCLES_FW_VPP].value;
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fw_cycles = fps * inst->capabilities->cap[MB_CYCLES_FW].value;
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fw_vpp_cycles = fps * inst->capabilities->cap[MB_CYCLES_FW_VPP].value;
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if (inst->domain == MSM_VIDC_ENCODER) {
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vpp_cycles_per_mb = is_low_power_session(inst) ?
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core->capabilities[MB_CYCLES_LP].value :
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core->capabilities[MB_CYCLES_VPP].value;
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inst->capabilities->cap[MB_CYCLES_LP].value :
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inst->capabilities->cap[MB_CYCLES_VPP].value;
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vpp_cycles = mbs_per_second * vpp_cycles_per_mb /
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inst->capabilities->cap[PIPE].value;
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@@ -90,7 +90,7 @@ u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size)
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vsp_cycles = div_u64(((u64)inst->capabilities->cap[BIT_RATE].value *
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vsp_factor_num), vsp_factor_den);
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base_cycles = core->capabilities[MB_CYCLES_VSP].value;
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base_cycles = inst->capabilities->cap[MB_CYCLES_VSP].value;
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if (inst->codec == MSM_VIDC_VP9) {
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vsp_cycles = div_u64(vsp_cycles * 170, 100);
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} else if (inst->capabilities->cap[ENTROPY_MODE].value ==
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@@ -110,7 +110,7 @@ u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size)
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} else if (inst->domain == MSM_VIDC_DECODER) {
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/* VPP */
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vpp_cycles = mbs_per_second * core->capabilities[MB_CYCLES_VPP].value /
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vpp_cycles = mbs_per_second * inst->capabilities->cap[MB_CYCLES_VPP].value /
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inst->capabilities->cap[PIPE].value;
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/* 21 / 20 is minimum overhead factor */
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vpp_cycles += max(vpp_cycles / 20, fw_vpp_cycles);
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@@ -119,7 +119,7 @@ u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size)
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vpp_cycles += div_u64(vpp_cycles * 59, 1000);
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/* VSP */
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base_cycles = core->capabilities[MB_CYCLES_VSP].value;
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base_cycles = inst->capabilities->cap[MB_CYCLES_VSP].value;
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vsp_cycles = fps * data_size * 8;
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if (inst->codec == MSM_VIDC_VP9) {
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@@ -147,8 +147,8 @@ u64 msm_vidc_calc_freq_iris2(struct msm_vidc_inst *inst, u32 data_size)
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freq = max(vpp_cycles, vsp_cycles);
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freq = max(freq, fw_cycles);
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i_vpr_p(inst, "%s: inst %pK: filled len %d required freq %llu\n",
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__func__, inst, data_size, freq);
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i_vpr_p(inst, "%s: filled len %d required freq %llu\n",
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__func__, data_size, freq);
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return freq;
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}
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