qcacmn: Umac reset support for direct switch

Umac reset support for direct switch.

Change-Id: Ic04880549ef4a38c795165e09a9f0d42673ae5f0
CRs-Fixed: 3438456

dp/wifi3.0/be/dp_be.c

@@ -2865,6 +2865,15 @@ void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
 	arch_ops->dp_tx_ppeds_inuse_desc = dp_ppeds_inuse_desc;
 	arch_ops->dp_tx_ppeds_cfg_astidx_cache_mapping =
 				dp_tx_ppeds_cfg_astidx_cache_mapping;
+#ifdef DP_UMAC_HW_RESET_SUPPORT
+	arch_ops->txrx_soc_ppeds_interrupt_stop = dp_ppeds_interrupt_stop_be;
+	arch_ops->txrx_soc_ppeds_interrupt_start = dp_ppeds_interrupt_start_be;
+	arch_ops->txrx_soc_ppeds_service_status_update =
+					dp_ppeds_service_status_update_be;
+	arch_ops->txrx_soc_ppeds_enabled_check = dp_ppeds_is_enabled_on_soc;
+	arch_ops->txrx_soc_ppeds_txdesc_pool_reset =
+					dp_ppeds_tx_desc_pool_reset;
+#endif
 #endif
 	dp_init_near_full_arch_ops_be(arch_ops);
 	arch_ops->get_reo_qdesc_addr = dp_rx_get_reo_qdesc_addr_be;

dp/wifi3.0/dp_main.c

@@ -1439,10 +1439,14 @@ void dp_srng_deinit(struct dp_soc *soc, struct dp_srng *srng,
 		return;
 	}
 
+	if (dp_check_umac_reset_in_progress(soc))
+		goto srng_cleanup;
+
 	if (soc->arch_ops.dp_free_ppeds_interrupts)
 		soc->arch_ops.dp_free_ppeds_interrupts(soc, srng, ring_type,
 						       ring_num);
 
+srng_cleanup:
 	hal_srng_cleanup(soc->hal_soc, srng->hal_srng);
 	srng->hal_srng = NULL;
 }
@@ -9853,28 +9857,114 @@ static QDF_STATUS dp_umac_reset_action_trigger_recovery(struct dp_soc *soc)
 	return dp_umac_reset_notify_action_completion(soc, action);
 }
 
+#ifdef WLAN_SUPPORT_PPEDS
 /**
- * dp_umac_reset_handle_pre_reset() - Handle Umac prereset interrupt from FW
+ * dp_umac_reset_service_handle_n_notify_done()
+ *	Handle Umac pre reset for direct switch
  * @soc: dp soc handle
  *
  * Return: QDF_STATUS
  */
-static QDF_STATUS dp_umac_reset_handle_pre_reset(struct dp_soc *soc)
+static QDF_STATUS dp_umac_reset_service_handle_n_notify_done(struct dp_soc *soc)
 {
-	if (wlan_cfg_get_dp_soc_is_ppeds_enabled(soc->wlan_cfg_ctx)) {
-		dp_err("Umac reset is currently not supported in DS config");
-		qdf_assert_always(0);
-	}
+	if (!soc->arch_ops.txrx_soc_ppeds_enabled_check ||
+	    !soc->arch_ops.txrx_soc_ppeds_service_status_update ||
+	    !soc->arch_ops.txrx_soc_ppeds_interrupt_stop)
+		goto non_ppeds;
 
-	dp_reset_interrupt_ring_masks(soc);
+	/*
+	 * Check if ppeds is enabled on SoC.
+	 */
+	if (!soc->arch_ops.txrx_soc_ppeds_enabled_check(soc))
+		goto non_ppeds;
 
-	dp_pause_tx_hardstart(soc);
-	dp_pause_reo_send_cmd(soc);
+	/*
+	 * Start the UMAC pre reset done service.
+	 */
+	soc->arch_ops.txrx_soc_ppeds_service_status_update(soc, true);
+
+	dp_register_notify_umac_pre_reset_fw_callback(soc);
+
+	soc->arch_ops.txrx_soc_ppeds_interrupt_stop(soc);
+
+	dp_soc_ppeds_stop((struct cdp_soc_t *)soc);
+
+	/*
+	 * UMAC pre reset service complete
+	 */
+	soc->arch_ops.txrx_soc_ppeds_service_status_update(soc, false);
+
+	soc->umac_reset_ctx.nbuf_list = NULL;
+	return QDF_STATUS_SUCCESS;
 
+non_ppeds:
+	dp_register_notify_umac_pre_reset_fw_callback(soc);
 	dp_check_n_notify_umac_prereset_done(soc);
+	soc->umac_reset_ctx.nbuf_list = NULL;
+	return QDF_STATUS_SUCCESS;
+}
+
+static inline void dp_umac_reset_ppeds_txdesc_pool_reset(struct dp_soc *soc,
+							 qdf_nbuf_t *nbuf_list)
+{
+	if (!soc->arch_ops.txrx_soc_ppeds_enabled_check ||
+	    !soc->arch_ops.txrx_soc_ppeds_txdesc_pool_reset)
+		return;
+
+	/*
+	 * Deinit of PPEDS Tx desc rings.
+	 */
+	if (soc->arch_ops.txrx_soc_ppeds_enabled_check(soc))
+		soc->arch_ops.txrx_soc_ppeds_txdesc_pool_reset(soc, nbuf_list);
+}
+
+static inline void dp_umac_reset_ppeds_start(struct dp_soc *soc)
+{
+	if (!soc->arch_ops.txrx_soc_ppeds_enabled_check ||
+	    !soc->arch_ops.txrx_soc_ppeds_start ||
+	    !soc->arch_ops.txrx_soc_ppeds_interrupt_start)
+		return;
 
+	/*
+	 * Start PPEDS node and enable interrupt.
+	 */
+	if (soc->arch_ops.txrx_soc_ppeds_enabled_check(soc)) {
+		soc->arch_ops.txrx_soc_ppeds_start(soc);
+		soc->arch_ops.txrx_soc_ppeds_interrupt_start(soc);
+	}
+}
+#else
+static QDF_STATUS dp_umac_reset_service_handle_n_notify_done(struct dp_soc *soc)
+{
+	dp_register_notify_umac_pre_reset_fw_callback(soc);
+	dp_check_n_notify_umac_prereset_done(soc);
 	soc->umac_reset_ctx.nbuf_list = NULL;
+	return QDF_STATUS_SUCCESS;
+}
+
+static inline void dp_umac_reset_ppeds_txdesc_pool_reset(struct dp_soc *soc,
+							 qdf_nbuf_t *nbuf_list)
+{
+}
+
+static inline void dp_umac_reset_ppeds_start(struct dp_soc *soc)
+{
+}
+#endif
+
+/**
+ * dp_umac_reset_handle_pre_reset() - Handle Umac prereset interrupt from FW
+ * @soc: dp soc handle
+ *
+ * Return: QDF_STATUS
+ */
+static QDF_STATUS dp_umac_reset_handle_pre_reset(struct dp_soc *soc)
+{
+	dp_reset_interrupt_ring_masks(soc);
 
+	dp_pause_tx_hardstart(soc);
+	dp_pause_reo_send_cmd(soc);
+	dp_umac_reset_service_handle_n_notify_done(soc);
 	return QDF_STATUS_SUCCESS;
 }
 
@@ -9897,6 +9987,8 @@ static QDF_STATUS dp_umac_reset_handle_post_reset(struct dp_soc *soc)
 
 		dp_cleanup_reo_cmd_module(soc);
 
+		dp_umac_reset_ppeds_txdesc_pool_reset(soc, nbuf_list);
+
 		dp_tx_desc_pool_cleanup(soc, nbuf_list);
 
 		dp_reset_tid_q_setup(soc);
@@ -9922,6 +10014,8 @@ static QDF_STATUS dp_umac_reset_handle_post_reset_complete(struct dp_soc *soc)
 
 	dp_resume_reo_send_cmd(soc);
 
+	dp_umac_reset_ppeds_start(soc);
+
 	dp_restore_interrupt_ring_masks(soc);
 
 	dp_resume_tx_hardstart(soc);

dp/wifi3.0/dp_rings_main.c

@@ -810,6 +810,15 @@ static void dp_srng_msi_setup(struct dp_soc *soc, struct dp_srng *srng,
 		 (uint64_t)ring_params->msi_addr);
 
 	vector = msi_irq_start + (reg_msi_grp_num % msi_data_count);
+
+	/*
+	 * During umac reset ppeds interrupts free is not called.
+	 * Avoid registering interrupts again.
+	 *
+	 */
+	if (dp_check_umac_reset_in_progress(soc))
+		goto configure_msi2;
+
 	if (soc->arch_ops.dp_register_ppeds_interrupts)
 		if (soc->arch_ops.dp_register_ppeds_interrupts(soc, srng,
 							       vector,

dp/wifi3.0/dp_types.h

@@ -2232,6 +2232,11 @@ enum dp_context_type {
  * @dp_tx_desc_pool_alloc: Allocate arch specific TX descriptor pool
  * @dp_tx_desc_pool_free: Free arch specific TX descriptor pool
  * @txrx_srng_init: Init txrx srng
+ * @txrx_soc_ppeds_interrupt_stop:
+ * @txrx_soc_ppeds_interrupt_start:
+ * @txrx_soc_ppeds_service_status_update:
+ * @txrx_soc_ppeds_enabled_check:
+ * @txrx_soc_ppeds_txdesc_pool_reset:
  */
 struct dp_arch_ops {
 	/* INIT/DEINIT Arch Ops */
@@ -2470,6 +2475,15 @@ struct dp_arch_ops {
 
 	QDF_STATUS (*txrx_srng_init)(struct dp_soc *soc, struct dp_srng *srng,
 				     int ring_type, int ring_num, int mac_id);
+#ifdef WLAN_SUPPORT_PPEDS
+	void (*txrx_soc_ppeds_interrupt_stop)(struct dp_soc *soc);
+	void (*txrx_soc_ppeds_interrupt_start)(struct dp_soc *soc);
+	void (*txrx_soc_ppeds_service_status_update)(struct dp_soc *soc,
+						     bool enable);
+	bool (*txrx_soc_ppeds_enabled_check)(struct dp_soc *soc);
+	void (*txrx_soc_ppeds_txdesc_pool_reset)(struct dp_soc *soc,
+						 qdf_nbuf_t *nbuf_list);
+#endif
 };
 
 /**

dp/wifi3.0/dp_umac_reset.c

@@ -62,12 +62,6 @@ dp_umac_reset_send_setup_cmd(struct dp_soc *soc)
 	uint32_t msi_base_data, msi_vector_start;
 	struct dp_htt_umac_reset_setup_cmd_params params;
 
-	if (wlan_cfg_get_dp_soc_is_ppeds_enabled(soc->wlan_cfg_ctx)) {
-		dp_umac_reset_err(
-			"Umac reset is currently not supported in DS config");
-		return QDF_STATUS_E_NOSUPPORT;
-	}
-
 	umac_reset_ctx = &soc->umac_reset_ctx;
 	qdf_mem_zero(&params, sizeof(params));
 	ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",