diff --git a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c
index 8ac49505f8..e395b13d64 100644
--- a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c
+++ b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c
@@ -36,6 +36,7 @@
 #include "cpastop_v165_100.h"
 #include "cpastop_v780_100.h"
 #include "cpastop_v640_200.h"
+#include "cpastop_v640_210.h"
 #include "cpastop_v880_100.h"
 #include "cpastop_v980_100.h"
 #include "cpastop_v860_100.h"
@@ -74,6 +75,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		0,
+		0,
 	},
 	/* for camera_170 */
 	{
@@ -83,6 +85,7 @@ static const uint32_t cam_cpas_hw_version_map
 		CAM_CPAS_TITAN_170_V120,
 		0,
 		CAM_CPAS_TITAN_170_V200,
+		0,
 	},
 	/* for camera_175 */
 	{
@@ -92,6 +95,7 @@ static const uint32_t cam_cpas_hw_version_map
 		CAM_CPAS_TITAN_175_V120,
 		CAM_CPAS_TITAN_175_V130,
 		0,
+		0,
 	},
 	/* for camera_480 */
 	{
@@ -101,6 +105,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		0,
+		0,
 	},
 	/* for camera_580 */
 	{
@@ -110,6 +115,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		0,
+		0,
 	},
 	/* for camera_520 */
 	{
@@ -119,6 +125,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		0,
+		0,
 
 	},
 	/* for camera_540 */
@@ -129,6 +136,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		0,
+		0,
 	},
 	/* for camera_545 */
 	{
@@ -138,6 +146,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		0,
+		0,
 	},
 	/* for camera_570 */
 	{
@@ -147,6 +156,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		CAM_CPAS_TITAN_570_V200,
+		0,
 	},
 	/* for camera_680 */
 	{
@@ -156,6 +166,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		0,
+		0,
 	},
 	/* for camera_165 */
 	{
@@ -165,6 +176,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		0,
+		0,
 	},
 	/* for camera_780 */
 	{
@@ -174,6 +186,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		0,
+		0,
 	},
 	/* for camera_640 */
 	{
@@ -183,6 +196,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		CAM_CPAS_TITAN_640_V200,
+		CAM_CPAS_TITAN_640_V210,
 	},
 	/* for camera_880 */
 	{
@@ -192,6 +206,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		0,
+		0,
 	},
 	/* for camera_980 */
 	{
@@ -201,6 +216,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		0,
+		0,
 	},
 	/* for camera_860 */
 	{
@@ -210,6 +226,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		0,
+		0,
 	},
 	/* for camera_770 */
 	{
@@ -219,6 +236,7 @@ static const uint32_t cam_cpas_hw_version_map
 		0,
 		0,
 		0,
+		0,
 	},
 };
 
@@ -338,6 +356,10 @@ static int cam_cpas_translate_camera_cpas_version_id(
 		*cpas_version_id = CAM_CPAS_VERSION_ID_200;
 		break;
 
+	case CAM_CPAS_VERSION_210:
+		*cpas_version_id = CAM_CPAS_VERSION_ID_210;
+		break;
+
 	default:
 		CAM_ERR(CAM_CPAS, "Invalid cpas version %u",
 			cpas_version);
@@ -1436,6 +1458,11 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw,
 		cpas_info = &cam640_cpas200_cpas_info;
 		cpas_top_info = &cam640_cpas200_cpas_top_info;
 		break;
+	case CAM_CPAS_TITAN_640_V210:
+		alloc_camnoc_info[CAM_CAMNOC_HW_COMBINED] = &cam640_cpas210_camnoc_info;
+		cpas_info = &cam640_cpas210_cpas_info;
+		cpas_top_info = &cam640_cpas210_cpas_top_info;
+		break;
 	case CAM_CPAS_TITAN_880_V100:
 		alloc_camnoc_info[CAM_CAMNOC_HW_COMBINED] = &cam880_cpas100_camnoc_info;
 		cpas_info = &cam880_cpas100_cpas_info;
diff --git a/drivers/cam_cpas/cpas_top/cpastop_v640_210.h b/drivers/cam_cpas/cpas_top/cpastop_v640_210.h
new file mode 100644
index 0000000000..6c6772b3a8
--- /dev/null
+++ b/drivers/cam_cpas/cpas_top/cpastop_v640_210.h
@@ -0,0 +1,583 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CPASTOP_V640_210_H_
+#define _CPASTOP_V640_210_H_
+
+#define TEST_IRQ_ENABLE 0
+
+static struct cam_camnoc_irq_sbm cam_cpas_v640_210_irq_sbm = {
+	.sbm_enable = {
+		.access_type = CAM_REG_TYPE_READ_WRITE,
+		.enable = true,
+		.offset = 0x6840, /* CAM_NOC_SBM_FAULTINEN0_LOW */
+		.value = 0x2 |    /* SBM_FAULTINEN0_LOW_PORT1_MASK */
+			0x04 |     /* SBM_FAULTINEN0_LOW_PORT2_MASK */
+			0x08 |     /* SBM_FAULTINEN0_LOW_PORT3_MASK */
+			0x10 |    /* SBM_FAULTINEN0_LOW_PORT4_MASK */
+			0x20 |    /* SBM_FAULTINEN0_LOW_PORT5_MASK */
+			(TEST_IRQ_ENABLE ?
+			0x80 :    /* SBM_FAULTINEN0_LOW_PORT7_MASK */
+			0x0),
+	},
+	.sbm_status = {
+		.access_type = CAM_REG_TYPE_READ,
+		.enable = true,
+		.offset = 0x6848, /* CAM_NOC_SBM_FAULTINSTATUS0_LOW */
+	},
+	.sbm_clear = {
+		.access_type = CAM_REG_TYPE_WRITE,
+		.enable = true,
+		.offset = 0x6880, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
+		.value = TEST_IRQ_ENABLE ? 0x5 : 0x1,
+	}
+};
+
+static struct cam_camnoc_irq_err
+	cam_cpas_v640_210_irq_err[] = {
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR,
+		.enable = false,
+		.sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x6608, /* CAM_NOC_ERL_MAINCTL_LOW */
+			.value = 1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x6610, /* CAM_NOC_ERL_ERRVLD_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x6618, /* CAM_NOC_ERL_ERRCLR_LOW */
+			.value = 1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x5DA0, /* WR_NIU_ENCERREN_LOW */
+			.value = 0XF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x5D90, /* WR_NIU_ENCERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x5D98, /* WR_NIU_ENCERRCLR_LOW */
+			.value = 0X1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR,
+		.enable = true,
+		.sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x5F20, /* CAM_NOC_IPE_0_RD_NIU_DECERREN_LOW */
+			.value = 0xFF,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x5F10, /* CAM_NOC_IPE_0_RD_NIU_DECERRSTATUS_LOW */
+		},
+		.err_clear = {
+			.access_type = CAM_REG_TYPE_WRITE,
+			.enable = true,
+			.offset = 0x5F18, /* CAM_NOC_IPE_0_RD_NIU_DECERRCLR_LOW */
+			.value = 0X1,
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT,
+		.enable = false,
+		.sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */
+		.err_enable = {
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.enable = true,
+			.offset = 0x6888, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */
+			.value = 0x1,
+		},
+		.err_status = {
+			.access_type = CAM_REG_TYPE_READ,
+			.enable = true,
+			.offset = 0x6890, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */
+		},
+		.err_clear = {
+			.enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */
+		},
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1,
+		.enable = false,
+	},
+	{
+		.irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2,
+		.enable = false,
+	},
+};
+
+static struct cam_camnoc_specific
+	cam_cpas_v640_210_camnoc_specific[] = {
+	{
+		.port_type = CAM_CAMNOC_TFE_BAYER_STATS,
+		.port_name = "TFE_BAYER",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5830, /*PRIORITYLUT_LOW */
+			.value = 0x55554433,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5834, /* PRIORITYLUT_HIGH */
+			.value = 0x66666666,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5838, /* URGENCY_LOW */
+			.value = 0x00001030,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5840, /* DANGERLUT_LOW */
+			.value = 0xffffff00,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5848, /* SAFELUT_LOW */
+			.value = 0x0000000f,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4208, /* QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4220, /* QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4224, /* QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x5820, /* UBWC_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_TFE_RAW,
+		.port_name = "TFE_RDI_RAW",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5A30, /* PRIORITYLUT_LOW */
+			.value = 0x33333333,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5A34, /* PRIORITYLUT_HIGH */
+			.value = 0x33333333,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5A38, /* URGENCY_LOW */
+			.value = 0x00001030,
+		},
+		.danger_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5A40, /* DANGERLUT_LOW */
+			.value = 0xffffff00,
+		},
+		.safe_lut = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5A48, /* SAFELUT_LOW */
+			.value = 0x000f,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4408, /* QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4420, /* QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4424, /* QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x5A20, /* STATS_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_OPE_BPS_WR,
+		.port_name = "OPE_BPS_WR",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5C30, /* PRIORITYLUT_LOW */
+			.value = 0x33333333,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5C34, /* PRIORITYLUT_HIGH */
+			.value = 0x33333333,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5C38, /* URGENCY_LOW */
+			.value = 0x00000030,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5C40, /* DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5C48, /* SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			/*
+			 * Do not explicitly set ubwc config register.
+			 * Power on default values are taking care of required
+			 * register settings.
+			 */
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4608, /* QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4620, /* QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4624, /* QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x5C20, /* MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_OPE_BPS_CDM_RD,
+		.port_name = "OPE_BPS_CDM_RD",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5E30, /* IPE_WR_PRIORITYLUT_LOW */
+			.value = 0x55554433,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5E34, /* IPE_WR_PRIORITYLUT_HIGH */
+			.value = 0x66666666,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5E38, /* IPE_WR_URGENCY_LOW */
+			.value = 0x3,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5E40, /* IPE_WR_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x5E48, /* IPE_WR_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4808, /* IPE_WR_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4820, /* IPE_WR_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4824, /* IPE_WR_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_CRE,
+		.port_name = "CRE_RD_WR",
+		.enable = true,
+		.priority_lut_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6030, /* BPS_WR_PRIORITYLUT_LOW */
+			.value = 0x33333333,
+		},
+		.priority_lut_high = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6034, /* BPS_WR_PRIORITYLUT_HIGH */
+			.value = 0x33333333,
+		},
+		.urgency = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6038, /* BPS_WR_URGENCY_LOW */
+			.value = 0x03,
+		},
+		.danger_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6040, /* BPS_WR_DANGERLUT_LOW */
+			.value = 0x0,
+		},
+		.safe_lut = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x6048, /* BPS_WR_SAFELUT_LOW */
+			.value = 0x0,
+		},
+		.ubwc_ctl = {
+			.enable = false,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4A08, /* BPS_WR_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4A20, /* BPS_WR_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4A24, /* BPS_WR_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x6020, /* BPS_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
+	},
+	{
+		.port_type = CAM_CAMNOC_ICP,
+		.port_name = "ICP",
+		.enable = false,
+		.flag_out_set0_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_WRITE,
+			.masked_value = 0,
+			.offset = 0x6888,
+			.value = 0x100000,
+		},
+		.qosgen_mainctl = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4008, /* ICP_QOSGEN_MAINCTL */
+			.value = 0x0,
+		},
+		.qosgen_shaping_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4020, /* ICP_QOSGEN_SHAPING_LOW */
+			.value = 0x0,
+		},
+		.qosgen_shaping_high = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ_WRITE,
+			.masked_value = 0,
+			.offset = 0x4024, /* ICP_QOSGEN_SHAPING_HIGH */
+			.value = 0x0,
+		},
+	},
+};
+
+static struct cam_camnoc_err_logger_info cam640_cpas210_err_logger_offsets = {
+	.mainctrl     =  0x6608, /* ERRLOGGER_MAINCTL_LOW */
+	.errvld       =  0x6610, /* ERRLOGGER_ERRVLD_LOW */
+	.errlog0_low  =  0x6620, /* ERRLOGGER_ERRLOG0_LOW */
+	.errlog0_high =  0x6624, /* ERRLOGGER_ERRLOG0_HIGH */
+	.errlog1_low  =  0x6628, /* ERRLOGGER_ERRLOG1_LOW */
+	.errlog1_high =  0x662c, /* ERRLOGGER_ERRLOG1_HIGH */
+	.errlog2_low  =  0x6630, /* ERRLOGGER_ERRLOG2_LOW */
+	.errlog2_high =  0x6634, /* ERRLOGGER_ERRLOG2_HIGH */
+	.errlog3_low  =  0x6638, /* ERRLOGGER_ERRLOG3_LOW */
+	.errlog3_high =  0x663c, /* ERRLOGGER_ERRLOG3_HIGH */
+};
+
+static struct cam_cpas_hw_errata_wa_list cam640_cpas210_errata_wa_list = {
+};
+
+static struct cam_camnoc_info cam640_cpas210_camnoc_info = {
+	.specific = &cam_cpas_v640_210_camnoc_specific[0],
+	.specific_size = ARRAY_SIZE(cam_cpas_v640_210_camnoc_specific),
+	.irq_sbm = &cam_cpas_v640_210_irq_sbm,
+	.irq_err = &cam_cpas_v640_210_irq_err[0],
+	.irq_err_size = ARRAY_SIZE(cam_cpas_v640_210_irq_err),
+	.err_logger = &cam640_cpas210_err_logger_offsets,
+	.errata_wa_list = &cam640_cpas210_errata_wa_list,
+};
+
+static struct cam_cpas_camnoc_qchannel cam640_cpas210_qchannel_info = {
+	.qchannel_ctrl   = 0x14,
+	.qchannel_status = 0x18,
+};
+
+static struct cam_cpas_info cam640_cpas210_cpas_info = {
+	.hw_caps_info = {
+		.num_caps_registers = 1,
+		.hw_caps_offsets = {0x8},
+	},
+	.qchannel_info = {&cam640_cpas210_qchannel_info},
+	.num_qchannel = 1,
+};
+
+static struct cam_cpas_top_regs cam640_cpas210_cpas_top_info = {
+	.tpg_mux_sel_enabled = true,
+	.tpg_mux_sel_shift   = 0x0,
+	.tpg_mux_sel         = 0x1C,
+};
+
+#endif /* _CPASTOP_V640_210_H_ */
+
diff --git a/drivers/cam_cpas/include/cam_cpas_api.h b/drivers/cam_cpas/include/cam_cpas_api.h
index 02054a29be..ca776b92ae 100644
--- a/drivers/cam_cpas/include/cam_cpas_api.h
+++ b/drivers/cam_cpas/include/cam_cpas_api.h
@@ -102,6 +102,7 @@ enum cam_cpas_version {
 	CAM_CPAS_VERSION_120  = 0x10020000,
 	CAM_CPAS_VERSION_130  = 0x10030000,
 	CAM_CPAS_VERSION_200  = 0x20000000,
+	CAM_CPAS_VERSION_210  = 0x20010000,
 	CAM_CPAS_VERSION_MAX
 };
 
@@ -141,6 +142,7 @@ enum cam_cpas_version_map_id {
 	CAM_CPAS_VERSION_ID_120  = 0x3,
 	CAM_CPAS_VERSION_ID_130  = 0x4,
 	CAM_CPAS_VERSION_ID_200  = 0x5,
+	CAM_CPAS_VERSION_ID_210  = 0x6,
 	CAM_CPAS_VERSION_ID_MAX
 };
 
@@ -170,6 +172,7 @@ enum cam_cpas_hw_version {
 	CAM_CPAS_TITAN_680_V110 = 0x680110,
 	CAM_CPAS_TITAN_780_V100 = 0x780100,
 	CAM_CPAS_TITAN_640_V200 = 0x640200,
+	CAM_CPAS_TITAN_640_V210 = 0x640210,
 	CAM_CPAS_TITAN_880_V100 = 0x880100,
 	CAM_CPAS_TITAN_980_V100 = 0x980100,
 	CAM_CPAS_TITAN_860_V100 = 0x860100,
diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid640_210.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid640_210.h
new file mode 100644
index 0000000000..0dd72fd1dc
--- /dev/null
+++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid640_210.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CAM_TFE_CSID_640_210_H_
+#define _CAM_TFE_CSID_640_210_H_
+
+#include "cam_tfe_csid_core.h"
+#include "cam_tfe_csid640.h"
+
+#define CAM_TFE_CSID_VERSION_V640_210               0x60040000
+
+static struct cam_tfe_csid_hw_info cam_tfe_csid640_210_hw_info = {
+	.csid_reg = &cam_tfe_csid_640_reg_offset,
+	.hw_dts_version = CAM_TFE_CSID_VERSION_V640_210,
+};
+
+#endif /*_CAM_TFE_CSID_640_210_H_ */
diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe640_210.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe640_210.h
new file mode 100644
index 0000000000..e2fa7b3836
--- /dev/null
+++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe640_210.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+
+#ifndef _CAM_TFE640_210_H_
+#define _CAM_TFE640_210_H_
+#include "cam_tfe_core.h"
+#include "cam_tfe_bus.h"
+#include "cam_tfe640.h"
+
+struct cam_tfe_hw_info cam_tfe640_210 = {
+	.top_irq_mask = {
+		0x00001834,
+		0x00001838,
+		0x0000183C,
+	},
+	.top_irq_clear = {
+		0x00001840,
+		0x00001844,
+		0x00001848,
+	},
+	.top_irq_status = {
+		0x0000184C,
+		0x00001850,
+		0x00001854,
+	},
+	.top_irq_cmd                       = 0x00001830,
+	.global_clear_bitmask              = 0x00000001,
+	.bus_irq_mask = {
+		0x00003018,
+		0x0000301C,
+	},
+	.bus_irq_clear = {
+		0x00003020,
+		0x00003024,
+	},
+	.bus_irq_status = {
+		0x00003028,
+		0x0000302C,
+	},
+	.bus_irq_cmd = 0x00003030,
+	.bus_violation_reg = 0x00003064,
+	.bus_overflow_reg = 0x00003068,
+	.bus_image_size_vilation_reg = 0x3070,
+	.bus_overflow_clear_cmd = 0x3060,
+	.debug_status_top = 0x30D8,
+
+	.reset_irq_mask = {
+		0x00000001,
+		0x00000000,
+		0x00000000,
+	},
+	.error_irq_mask = {
+		0x000F0F00,
+		0x00000000,
+		0x0000003F,
+	},
+	.bus_reg_irq_mask = {
+		0x00000002,
+		0x00000000,
+	},
+	.bus_error_irq_mask = {
+		0xC0000000,
+		0x00000000,
+	},
+
+	.num_clc = 39,
+	.clc_hw_status_info            = tfe640_clc_hw_info,
+	.bus_version                   = CAM_TFE_BUS_1_0,
+	.bus_hw_info                   = &tfe640_bus_hw_info,
+
+	.top_version                   = CAM_TFE_TOP_1_0,
+	.top_hw_info                   = &tfe640_top_hw_info,
+};
+
+#endif /* _CAM_TFE640_210_H_ */