msm: camera: isp: Use CSID Interrrupts for non SFE use cases

In Non-SFE use cases, camif interrupts from CSID are sufficient to
run the state machine. In SFE cases, interrupts from VFE can be
used to drive the state machine.
This commit adds changes to subscribe the IRQs based on the
use case.

Change-Id: I75c2bc4f6e0754ef1e80a2d4f291b18f16900475
CRs-Fixed: 3153295
Signed-off-by: Gaurav Jindal <[email protected]>

drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c

@@ -2986,6 +2986,11 @@ static int cam_ife_hw_mgr_acquire_ife_src_for_sfe(
 	vfe_acquire.vfe_in.is_offline = ife_ctx->flags.is_offline;
 	vfe_acquire.priv = ife_ctx;
 	vfe_acquire.event_cb = cam_ife_hw_mgr_event_handler;
+	vfe_acquire.vfe_in.handle_camif_irq = true;
+	if (ife_hw_mgr->csid_camif_irq_support && ife_ctx->ctx_type !=
+		CAM_IFE_CTX_TYPE_SFE)
+		vfe_acquire.vfe_in.handle_camif_irq = false;
+
 	if (!acquire_lcr)
 		vfe_acquire.vfe_in.res_id =
 			CAM_ISP_HW_VFE_IN_CAMIF;
@@ -3147,6 +3152,11 @@ static int cam_ife_hw_mgr_acquire_res_ife_src(
 		vfe_acquire.vfe_in.is_offline = ife_ctx->flags.is_offline;
 		vfe_acquire.priv = ife_ctx;
 		vfe_acquire.event_cb = cam_ife_hw_mgr_event_handler;
+		vfe_acquire.vfe_in.handle_camif_irq = true;
+
+		if (ife_hw_mgr->csid_camif_irq_support && ife_ctx->ctx_type !=
+			CAM_IFE_CTX_TYPE_SFE)
+			vfe_acquire.vfe_in.handle_camif_irq = false;
 
 		switch (csid_res->res_id) {
 		case CAM_IFE_PIX_PATH_RES_IPP:
@@ -3296,6 +3306,9 @@ static int cam_ife_hw_mgr_acquire_csid_hw(
 		can_use_lite = cam_ife_mgr_check_can_use_lite(
 			csid_acquire, ife_ctx);
 
+	if (ife_hw_mgr->csid_camif_irq_support && ife_ctx->ctx_type != CAM_IFE_CTX_TYPE_SFE)
+		csid_acquire->handle_camif_irq = true;
+
 	/* Try acquiring CSID from previously acquired HW */
 	list_for_each_entry(csid_res_iterator, &ife_ctx->res_list_ife_csid,
 		list) {
@@ -4065,6 +4078,10 @@ static int cam_ife_hw_mgr_acquire_offline_res_ife_camif(
 	vfe_acquire.vfe_in.in_port = in_port;
 	vfe_acquire.vfe_in.is_fe_enabled = ife_ctx->flags.is_fe_enabled;
 	vfe_acquire.vfe_in.is_offline = ife_ctx->flags.is_offline;
+	vfe_acquire.vfe_in.handle_camif_irq = true;
+	if (ife_hw_mgr->csid_camif_irq_support && ife_ctx->ctx_type !=
+		CAM_IFE_CTX_TYPE_SFE)
+		vfe_acquire.vfe_in.handle_camif_irq = false;
 
 	if (!acquire_lcr)
 		vfe_acquire.vfe_in.res_id = CAM_ISP_HW_VFE_IN_CAMIF;
@@ -9249,6 +9266,46 @@ static inline int cam_isp_validate_bw_limiter_blob(
 	return 0;
 }
 
+static int cam_isp_blob_csid_init_config_update(
+	struct cam_hw_prepare_update_args *prepare,
+	struct cam_isp_init_config        *init_config)
+{
+	int i, rc = -EINVAL;
+	struct cam_hw_intf                    *hw_intf;
+	struct cam_ife_hw_mgr_ctx             *ctx = NULL;
+	struct cam_isp_hw_mgr_res             *hw_mgr_res;
+	struct cam_isp_hw_init_config_update   init_cfg_update;
+
+	ctx = prepare->ctxt_to_hw_map;
+
+	/* Assign init config */
+	init_cfg_update.init_config = init_config;
+	list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid, list) {
+		for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) {
+			if (!hw_mgr_res->hw_res[i])
+				continue;
+
+			hw_intf = hw_mgr_res->hw_res[i]->hw_intf;
+			if (hw_intf && hw_intf->hw_ops.process_cmd) {
+				init_cfg_update.node_res =
+					hw_mgr_res->hw_res[i];
+				CAM_DBG(CAM_ISP, "Init config update for res_id: %u",
+					hw_mgr_res->res_id);
+
+				rc = hw_intf->hw_ops.process_cmd(
+					hw_intf->hw_priv,
+					CAM_ISP_HW_CMD_INIT_CONFIG_UPDATE,
+					&init_cfg_update,
+					sizeof(
+					struct cam_isp_hw_init_config_update));
+				if (rc)
+					CAM_ERR(CAM_ISP, "Init cfg update failed rc: %d", rc);
+			}
+		}
+	}
+
+	return rc;
+}
 static int cam_isp_blob_ife_init_config_update(
 	struct cam_hw_prepare_update_args *prepare,
 	struct cam_isp_init_config        *init_config)
@@ -9954,11 +10011,19 @@ static int cam_isp_packet_generic_blob_handler(void *user_data,
 		}
 
 		init_config = (struct cam_isp_init_config *)blob_data;
-		rc = cam_isp_blob_ife_init_config_update(
-			prepare, init_config);
+
+		rc = cam_isp_blob_csid_init_config_update(prepare, init_config);
+		if (rc) {
+			CAM_ERR(CAM_ISP,
+				"CSID Init config failed for req: %llu rc: %d",
+				 prepare->packet->header.request_id, rc);
+			break;
+		}
+
+		rc = cam_isp_blob_ife_init_config_update(prepare, init_config);
 		if (rc)
 			CAM_ERR(CAM_ISP,
-				"Init config failed for req: %llu rc: %d",
+				"IFE Init config failed for req: %llu rc: %d",
 				 prepare->packet->header.request_id, rc);
 	}
 		break;
@@ -12579,6 +12644,8 @@ static int cam_ife_hw_mgr_handle_csid_rup(
 			break;
 		ife_hwr_irq_rup_cb(ife_hw_mgr_ctx->common.cb_priv,
 			CAM_ISP_HW_EVENT_REG_UPDATE, &rup_event_data);
+		CAM_DBG(CAM_ISP, "RUP done for CSID:%d source %d", event_info->hw_idx,
+			event_info->res_id);
 		break;
 	default:
 		CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d",
@@ -12586,18 +12653,50 @@ static int cam_ife_hw_mgr_handle_csid_rup(
 		break;
 	}
 
-	CAM_DBG(CAM_ISP, "RUP done for CSID:%d source %d", event_info->hw_idx,
-		event_info->res_id);
-
 	return 0;
 }
 
+static int cam_ife_hw_mgr_handle_csid_eof(
+	struct cam_ife_hw_mgr_ctx        *ctx,
+	struct cam_isp_hw_event_info     *event_info)
+{
+	cam_hw_event_cb_func                     ife_hwr_irq_rup_cb;
+	struct cam_isp_hw_eof_event_data         eof_done_event_data;
+
+	ife_hwr_irq_rup_cb = ctx->common.event_cb;
+
+	switch (event_info->res_id) {
+	case CAM_IFE_PIX_PATH_RES_IPP:
+	case CAM_IFE_PIX_PATH_RES_RDI_0:
+	case CAM_IFE_PIX_PATH_RES_RDI_1:
+	case CAM_IFE_PIX_PATH_RES_RDI_2:
+	case CAM_IFE_PIX_PATH_RES_RDI_3:
+	case CAM_IFE_PIX_PATH_RES_RDI_4:
+	case CAM_IFE_PIX_PATH_RES_PPP:
+		if (atomic_read(&ctx->overflow_pending))
+			break;
+		ife_hwr_irq_rup_cb(ctx->common.cb_priv,
+			CAM_ISP_HW_EVENT_EOF, &eof_done_event_data);
+		CAM_DBG(CAM_ISP,
+			"Received CSID[%u] CAMIF EOF res: %d", event_info->hw_idx,
+			event_info->res_id);
+		break;
+	default:
+		CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d",
+			event_info->res_id);
+		break;
+	}
+
+	return 0;
+}
 static int cam_ife_hw_mgr_handle_csid_camif_sof(
 	struct cam_ife_hw_mgr_ctx            *ctx,
 	struct cam_isp_hw_event_info         *event_info)
 {
-	int rc = 0;
-	cam_hw_event_cb_func ife_hw_irq_sof_cb = ctx->common.event_cb;
+	int                                    rc = 0;
+	cam_hw_event_cb_func ife_hw_irq_sof_cb     = ctx->common.event_cb;
+	struct cam_isp_hw_sof_event_data       sof_done_event_data = {0};
+	struct timespec64                      ts;
 
 	if (event_info->is_secondary_evt) {
 		struct cam_isp_hw_secondary_event_data sec_evt_data;
@@ -12609,8 +12708,53 @@ static int cam_ife_hw_mgr_handle_csid_camif_sof(
 		sec_evt_data.evt_type = CAM_ISP_HW_SEC_EVENT_SOF;
 		rc = ife_hw_irq_sof_cb(ctx->common.cb_priv,
 			CAM_ISP_HW_SECONDARY_EVENT, (void *)&sec_evt_data);
+		goto end;
 	}
 
+	switch (event_info->res_id) {
+	case CAM_IFE_PIX_PATH_RES_IPP:
+	case CAM_IFE_PIX_PATH_RES_RDI_0:
+	case CAM_IFE_PIX_PATH_RES_RDI_1:
+	case CAM_IFE_PIX_PATH_RES_RDI_2:
+	case CAM_IFE_PIX_PATH_RES_RDI_3:
+	case CAM_IFE_PIX_PATH_RES_RDI_4:
+	case CAM_IFE_PIX_PATH_RES_PPP:
+		if (atomic_read(&ctx->overflow_pending))
+			break;
+		if (ctx->ctx_config &
+			CAM_IFE_CTX_CFG_FRAME_HEADER_TS) {
+			sof_done_event_data.timestamp = 0x0;
+			ktime_get_boottime_ts64(&ts);
+			sof_done_event_data.boot_time =
+			(uint64_t)((ts.tv_sec * 1000000000) +
+			ts.tv_nsec);
+			CAM_DBG(CAM_ISP, "boot_time 0x%llx",
+				sof_done_event_data.boot_time);
+		} else {
+			if (ctx->flags.is_offline)
+				cam_ife_hw_mgr_get_offline_sof_timestamp(
+				&sof_done_event_data.timestamp,
+				&sof_done_event_data.boot_time);
+			else
+				cam_ife_mgr_cmd_get_sof_timestamp(
+				ctx, &sof_done_event_data.timestamp,
+				&sof_done_event_data.boot_time, NULL);
+		}
+
+		ife_hw_irq_sof_cb(ctx->common.cb_priv,
+			CAM_ISP_HW_EVENT_SOF, (void *)&sof_done_event_data);
+
+		CAM_DBG(CAM_ISP,
+			"Received CSID[%u] CAMIF SOF res: %d", event_info->hw_idx,
+			event_info->res_id);
+
+		break;
+	default:
+		CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d",
+			event_info->res_id);
+		break;
+	}
+end:
 	return rc;
 }
 
@@ -12620,6 +12764,7 @@ static int cam_ife_hw_mgr_handle_csid_camif_epoch(
 {
 	int rc = 0;
 	cam_hw_event_cb_func ife_hw_irq_epoch_cb = ctx->common.event_cb;
+	struct cam_isp_hw_epoch_event_data    epoch_done_event_data  = {0};
 
 	if (event_info->is_secondary_evt) {
 		struct cam_isp_hw_secondary_event_data sec_evt_data;
@@ -12631,8 +12776,32 @@ static int cam_ife_hw_mgr_handle_csid_camif_epoch(
 		sec_evt_data.evt_type = CAM_ISP_HW_SEC_EVENT_EPOCH;
 		rc = ife_hw_irq_epoch_cb(ctx->common.cb_priv,
 			CAM_ISP_HW_SECONDARY_EVENT, (void *)&sec_evt_data);
+		goto end;
 	}
 
+	switch (event_info->res_id) {
+	case CAM_IFE_PIX_PATH_RES_IPP:
+	case CAM_IFE_PIX_PATH_RES_RDI_0:
+	case CAM_IFE_PIX_PATH_RES_RDI_1:
+	case CAM_IFE_PIX_PATH_RES_RDI_2:
+	case CAM_IFE_PIX_PATH_RES_RDI_3:
+	case CAM_IFE_PIX_PATH_RES_RDI_4:
+	case CAM_IFE_PIX_PATH_RES_PPP:
+		if (atomic_read(&ctx->overflow_pending))
+			break;
+		epoch_done_event_data.frame_id_meta = event_info->reg_val;
+		ife_hw_irq_epoch_cb(ctx->common.cb_priv,
+			CAM_ISP_HW_EVENT_EPOCH, (void *)&epoch_done_event_data);
+
+		CAM_DBG(CAM_ISP,
+			"Received CSID[%u] CAMIF Epoch res: %d", event_info->hw_idx,
+			event_info->res_id);
+		break;
+	default:
+		CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", event_info->res_id);
+		break;
+	}
+end:
 	return rc;
 }
 
@@ -13247,7 +13416,9 @@ static int cam_ife_hw_mgr_handle_csid_event(
 	case CAM_ISP_HW_EVENT_EPOCH:
 		rc = cam_ife_hw_mgr_handle_csid_camif_epoch(ctx, event_info);
 		break;
-
+	case CAM_ISP_HW_EVENT_EOF:
+		rc = cam_ife_hw_mgr_handle_csid_eof(ctx, event_info);
+		break;
 	default:
 		CAM_ERR(CAM_ISP, "Event: %u not handled for CSID", evt_id);
 		rc = -EINVAL;
@@ -13353,6 +13524,8 @@ static int cam_ife_hw_mgr_sort_dev_with_caps(
 			ife_hw_mgr->csid_hw_caps[i].global_reset_en;
 		ife_hw_mgr->csid_rup_en =
 			ife_hw_mgr->csid_hw_caps[i].rup_en;
+		ife_hw_mgr->csid_camif_irq_support =
+			ife_hw_mgr->csid_hw_caps[i].camif_irq_support;
 	}
 
 	/* get caps for ife devices */

drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h

@@ -394,6 +394,7 @@ struct cam_isp_sys_cache_info {
  * @hw_pid_support         hw pid support for this target
  * @csid_rup_en            Reg update at CSID side
  * @csid_global_reset_en   CSID global reset enable
+ * @csid_camif_irq_support CSID camif IRQ support
  * @isp_caps               Capability of underlying SFE/IFE HW
  * @path_port_map          Mapping of outport to IFE mux
  */
@@ -419,6 +420,7 @@ struct cam_ife_hw_mgr {
 	bool                             hw_pid_support;
 	bool                             csid_rup_en;
 	bool                             csid_global_reset_en;
+	bool                             csid_camif_irq_support;
 	struct cam_isp_ife_sfe_hw_caps   isp_caps;
 	struct cam_isp_hw_path_port_map  path_port_map;
 

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid680.h

@@ -481,7 +481,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.lut_bank_1_sel_val               = 1,
 		.fatal_err_mask                   = 0x186004,
 		.non_fatal_err_mask               = 0x10000000,
-		.camif_irq_mask                   = 0x800000,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x10001,
 		.top_irq_mask                     = 0x10,
 		.epoch0_shift_val                 = 16,
@@ -675,7 +679,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                = 1,
 		.fatal_err_mask                   = 0x186004,
 		.non_fatal_err_mask               = 0x10000000,
-		.camif_irq_mask                   = 0x800000,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x100010,
 		.top_irq_mask                     = 0x100,
 		.epoch0_shift_val                 = 16,
@@ -769,7 +777,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                = 1,
 		.fatal_err_mask                   = 0x186004,
 		.non_fatal_err_mask               = 0x10000000,
-		.camif_irq_mask                   = 0x800000,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x200020,
 		.top_irq_mask                     = 0x200,
 		.epoch0_shift_val                 = 16,
@@ -863,7 +875,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                = 1,
 		.fatal_err_mask                   = 0x186004,
 		.non_fatal_err_mask               = 0x10000000,
-		.camif_irq_mask                   = 0x800000,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x400040,
 		.top_irq_mask                     = 0x400,
 		.epoch0_shift_val                 = 16,
@@ -957,7 +973,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                = 1,
 		.fatal_err_mask                   = 0x186004,
 		.non_fatal_err_mask               = 0x10000000,
-		.camif_irq_mask                   = 0x800000,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x800080,
 		.top_irq_mask                     = 0x800,
 		.epoch0_shift_val                 = 16,
@@ -1051,7 +1071,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en               = 1,
 		.fatal_err_mask                  = 0x186004,
 		.non_fatal_err_mask              = 0x10000000,
-		.camif_irq_mask                  = 0x800000,
+		.sof_irq_mask                    = 0x10,
+		.rup_irq_mask                    = 0x800000,
+		.epoch0_irq_mask                 = 0x200000,
+		.epoch1_irq_mask                 = 0x400000,
+		.eof_irq_mask                    = 0x8,
 		.rup_aup_mask                    = 0x1000100,
 		.top_irq_mask                    = 0x1000,
 		.epoch0_shift_val                = 16,
@@ -1209,7 +1233,7 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.timestamp_strobe_val                    = 0x2,
 	.rst_location_shift_val                  = 4,
 	.rst_mode_shift_val                      = 0,
-	.epoch_div_factor                        = 2,
+	.epoch_factor                            = 50,
 	.global_reset                            = 1,
 	.rup_supported                           = 1,
 	.only_master_rup                         = 1,
@@ -1219,6 +1243,7 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.format_measure_width_shift_val          = 0x0,
 	.top_reset_irq_mask                      = 0x1,
 	.top_buf_done_irq_mask                   = 0x2000,
+	.camif_irq_support                       = true,
 };
 
 static struct cam_ife_csid_ver2_top_reg_info

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid780.h

@@ -514,7 +514,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.lut_bank_1_sel_val               = 1,
 		.fatal_err_mask                   = 0x186007,
 		.non_fatal_err_mask               = 0x10000000,
-		.camif_irq_mask                   = 0x800000,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x10001,
 		.top_irq_mask                     = 0x10,
 		.epoch0_shift_val                 = 16,
@@ -714,7 +718,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                = 1,
 		.fatal_err_mask                   = 0x186005,
 		.non_fatal_err_mask               = 0x10000000,
-		.camif_irq_mask                   = 0x800000,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x100010,
 		.top_irq_mask                     = 0x100,
 		.epoch0_shift_val                 = 16,
@@ -815,7 +823,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                = 1,
 		.fatal_err_mask                   = 0x186005,
 		.non_fatal_err_mask               = 0x10000000,
-		.camif_irq_mask                   = 0x800000,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x200020,
 		.top_irq_mask                     = 0x200,
 		.epoch0_shift_val                 = 16,
@@ -915,7 +927,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                = 1,
 		.fatal_err_mask                   = 0x186005,
 		.non_fatal_err_mask               = 0x10000000,
-		.camif_irq_mask                   = 0x800000,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x400040,
 		.top_irq_mask                     = 0x400,
 		.epoch0_shift_val                 = 16,
@@ -1013,7 +1029,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                = 1,
 		.fatal_err_mask                   = 0x186005,
 		.non_fatal_err_mask               = 0x10000000,
-		.camif_irq_mask                   = 0x800000,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x800080,
 		.top_irq_mask                     = 0x800,
 		.epoch0_shift_val                 = 16,
@@ -1110,7 +1130,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en               = 1,
 		.fatal_err_mask                  = 0x186005,
 		.non_fatal_err_mask              = 0x10000000,
-		.camif_irq_mask                  = 0x800000,
+		.sof_irq_mask                    = 0x10,
+		.rup_irq_mask                    = 0x800000,
+		.epoch0_irq_mask                 = 0x200000,
+		.epoch1_irq_mask                 = 0x400000,
+		.eof_irq_mask                    = 0x8,
 		.rup_aup_mask                    = 0x1000100,
 		.top_irq_mask                    = 0x1000,
 		.epoch0_shift_val                = 16,
@@ -1275,7 +1299,7 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.top_reset_irq_mask                      = 0x1,
 	.rst_location_shift_val                  = 4,
 	.rst_mode_shift_val                      = 0,
-	.epoch_div_factor                        = 4,
+	.epoch_factor                            = 50,
 	.global_reset                            = 1,
 	.rup_supported                           = 1,
 	.only_master_rup                         = 1,
@@ -1286,6 +1310,7 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.top_buf_done_irq_mask                   = 0x2000,
 	.decode_format_payload_only              = 0xF,
 	.timestamp_enabled_in_cfg0               = true,
+	.camif_irq_support                       = true,
 	.sfe_ipp_input_rdi_res                   = BIT(CAM_IFE_PIX_PATH_RES_RDI_0),
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c

@@ -1635,31 +1635,25 @@ static int cam_ife_csid_ver2_ipp_bottom_half(
 	evt_info.res_type = CAM_ISP_RESOURCE_PIX_PATH;
 	evt_info.reg_val  = irq_status_ipp;
 
-	if (irq_status_ipp & IFE_CSID_VER2_PATH_CAMIF_EOF) {
-		if (csid_hw->event_cb)
-			csid_hw->event_cb(csid_hw->token,
-				CAM_ISP_HW_EVENT_EOF, (void *)&evt_info);
+	if (!csid_hw->event_cb) {
+		CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID[%u] event cb not registered",
+			csid_hw->hw_intf->hw_idx);
+		goto end;
 	}
 
-	if (irq_status_ipp & IFE_CSID_VER2_PATH_CAMIF_SOF) {
-		if (csid_hw->event_cb)
-			csid_hw->event_cb(csid_hw->token,
-				CAM_ISP_HW_EVENT_SOF, (void *)&evt_info);
-	}
+	path_reg = csid_reg->path_reg[res->res_id];
+	if (irq_status_ipp & path_reg->eof_irq_mask)
+		csid_hw->event_cb(csid_hw->token, CAM_ISP_HW_EVENT_EOF, (void *)&evt_info);
 
-	if (irq_status_ipp & IFE_CSID_VER2_PATH_RUP_DONE) {
-		if (csid_hw->event_cb)
-			csid_hw->event_cb(csid_hw->token,
-				CAM_ISP_HW_EVENT_REG_UPDATE, (void *)&evt_info);
-	}
+	if (irq_status_ipp & path_reg->sof_irq_mask)
+		csid_hw->event_cb(csid_hw->token, CAM_ISP_HW_EVENT_SOF, (void *)&evt_info);
 
-	if (irq_status_ipp & IFE_CSID_VER2_PATH_CAMIF_EPOCH0) {
-		if (csid_hw->event_cb)
-			csid_hw->event_cb(csid_hw->token,
-				CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info);
-	}
+	if (irq_status_ipp & path_reg->rup_irq_mask)
+		csid_hw->event_cb(csid_hw->token, CAM_ISP_HW_EVENT_REG_UPDATE, (void *)&evt_info);
+
+	if (irq_status_ipp & path_reg->epoch0_irq_mask)
+		csid_hw->event_cb(csid_hw->token, CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info);
 
-	path_reg = csid_reg->path_reg[res->res_id];
 	err_mask = path_reg->fatal_err_mask | path_reg->non_fatal_err_mask;
 	spin_lock(&csid_hw->lock_state);
 	if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) {
@@ -1788,7 +1782,6 @@ static int cam_ife_csid_ver2_rdi_bottom_half(
 	uint32_t                                      irq_status_rdi;
 	uint32_t                                      err_mask;
 	uint32_t                                      err_type = 0;
-	bool                                          skip_evt_notify = false;
 	struct cam_isp_hw_event_info                  evt_info;
 	int                                           rc = 0;
 
@@ -1868,59 +1861,36 @@ static int cam_ife_csid_ver2_rdi_bottom_half(
 	evt_info.hw_type = CAM_ISP_HW_TYPE_CSID;
 
 	/* Check for specific secondary events */
-	if (path_cfg->sec_evt_config.en_secondary_evt) {
-		if ((irq_status_rdi & IFE_CSID_VER2_PATH_CAMIF_SOF) &&
+	if (path_cfg->sec_evt_config.en_secondary_evt &&
+		((irq_status_rdi & IFE_CSID_VER2_PATH_SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP) &&
+		(path_cfg->sec_evt_config.evt_type & CAM_IFE_CSID_EVT_SENSOR_SYNC_FRAME_DROP)))
+		cam_ife_csid_ver2_handle_event_err(csid_hw, irq_status_rdi,
+			CAM_ISP_HW_ERROR_CSID_SENSOR_FRAME_DROP, true, res);
+
+	if (irq_status_rdi & rdi_reg->eof_irq_mask)
+		csid_hw->event_cb(csid_hw->token, CAM_ISP_HW_EVENT_EOF, (void *)&evt_info);
+
+	if ((irq_status_rdi & rdi_reg->sof_irq_mask)) {
+		if (path_cfg->sec_evt_config.en_secondary_evt &&
 			(path_cfg->sec_evt_config.evt_type & CAM_IFE_CSID_EVT_SOF)) {
 			evt_info.is_secondary_evt = true;
-			csid_hw->event_cb(csid_hw->token,
-				CAM_ISP_HW_EVENT_SOF, (void *)&evt_info);
-			skip_evt_notify = true;
 		}
+		csid_hw->event_cb(csid_hw->token, CAM_ISP_HW_EVENT_SOF,	(void *)&evt_info);
+	}
 
-		if ((irq_status_rdi & IFE_CSID_VER2_PATH_CAMIF_EPOCH0) &&
+	if (irq_status_rdi & rdi_reg->rup_irq_mask)
+		csid_hw->event_cb(csid_hw->token, CAM_ISP_HW_EVENT_REG_UPDATE, (void *)&evt_info);
+
+	if ((irq_status_rdi & rdi_reg->epoch0_irq_mask)) {
+		if (path_cfg->sec_evt_config.en_secondary_evt &&
 			(path_cfg->sec_evt_config.evt_type & CAM_IFE_CSID_EVT_EPOCH)) {
 			evt_info.is_secondary_evt = true;
-			csid_hw->event_cb(csid_hw->token,
-				CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info);
-			skip_evt_notify = true;
-		}
-
-		if ((irq_status_rdi &
-			IFE_CSID_VER2_PATH_SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP) &&
-			(path_cfg->sec_evt_config.evt_type &
-			CAM_IFE_CSID_EVT_SENSOR_SYNC_FRAME_DROP)) {
-			cam_ife_csid_ver2_handle_event_err(csid_hw,
-				irq_status_rdi, CAM_ISP_HW_ERROR_CSID_SENSOR_FRAME_DROP, true, res);
 		}
+		csid_hw->event_cb(csid_hw->token, CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info);
 	}
-
-	evt_info.is_secondary_evt = false;
-	if (!path_cfg->handle_camif_irq)
-		goto end;
-
-	if (irq_status_rdi & IFE_CSID_VER2_PATH_CAMIF_EOF)
-		csid_hw->event_cb(csid_hw->token,
-				CAM_ISP_HW_EVENT_EOF,
-				(void *)&evt_info);
-
-	if (!skip_evt_notify && (irq_status_rdi & IFE_CSID_VER2_PATH_CAMIF_SOF))
-		csid_hw->event_cb(csid_hw->token,
-				CAM_ISP_HW_EVENT_SOF,
-				(void *)&evt_info);
-
-	if (irq_status_rdi & IFE_CSID_VER2_PATH_RUP_DONE)
-		csid_hw->event_cb(csid_hw->token,
-				CAM_ISP_HW_EVENT_REG_UPDATE,
-				(void *)&evt_info);
-
-	if (!skip_evt_notify && (irq_status_rdi & IFE_CSID_VER2_PATH_CAMIF_EPOCH0))
-		csid_hw->event_cb(csid_hw->token,
-				CAM_ISP_HW_EVENT_EPOCH,
-				(void *)&evt_info);
 end:
 	cam_ife_csid_ver2_put_evt_payload(csid_hw, &payload,
-			&csid_hw->path_free_payload_list,
-			&csid_hw->path_payload_lock);
+		&csid_hw->path_free_payload_list, &csid_hw->path_payload_lock);
 
 	return rc;
 }
@@ -1960,6 +1930,7 @@ int cam_ife_csid_ver2_get_hw_caps(void *hw_priv,
 	hw_caps->only_master_rup = csid_reg->cmn_reg->only_master_rup;
 	hw_caps->is_lite = soc_private->is_ife_csid_lite;
 	hw_caps->sfe_ipp_input_rdi_res = csid_reg->cmn_reg->sfe_ipp_input_rdi_res;
+	hw_caps->camif_irq_support = csid_reg->cmn_reg->camif_irq_support;
 
 	CAM_DBG(CAM_ISP,
 		"CSID:%d num-rdis:%d, num-pix:%d, major:%d minor:%d ver:%d",
@@ -2534,13 +2505,17 @@ static int cam_ife_csid_ver_config_camif(
 	case CAM_IFE_PIX_PATH_RES_RDI_2:
 	case CAM_IFE_PIX_PATH_RES_RDI_3:
 	case CAM_IFE_PIX_PATH_RES_RDI_4:
-		path_cfg->camif_data.epoch0 =
-		(path_cfg->end_line - path_cfg->start_line) /
-		csid_reg->cmn_reg->epoch_div_factor;
+		path_cfg->epoch_cfg = (path_cfg->end_line  - path_cfg->start_line) *
+			csid_reg->cmn_reg->epoch_factor / 100;
 
-		CAM_DBG(CAM_ISP, "CSID[%d] res_id: %u epoch0: 0x%x",
-			csid_hw->hw_intf->hw_idx, reserve->res_id,
-			path_cfg->camif_data.epoch0);
+		if (path_cfg->epoch_cfg > path_cfg->end_line)
+			path_cfg->epoch_cfg = path_cfg->end_line;
+
+		if (path_cfg->horizontal_bin || path_cfg->qcfa_bin)
+			path_cfg->epoch_cfg >>= 1;
+
+		CAM_DBG(CAM_ISP, "CSID[%d] res_id: %u epoch factor: 0x%x",
+			csid_hw->hw_intf->hw_idx, reserve->res_id, path_cfg->epoch_cfg);
 		break;
 	default:
 		CAM_DBG(CAM_ISP, "No CAMIF epoch update for res: %u", reserve->res_id);
@@ -2728,6 +2703,7 @@ int cam_ife_csid_ver2_reserve(void *hw_priv,
 	res->cdm_ops = reserve->cdm_ops;
 	csid_hw->flags.sfe_en = reserve->sfe_en;
 	path_cfg->sfe_shdr = reserve->sfe_inline_shdr;
+	path_cfg->handle_camif_irq = reserve->handle_camif_irq;
 	csid_hw->flags.offline_mode = reserve->is_offline;
 	reserve->need_top_cfg = csid_reg->need_top_cfg;
 
@@ -3394,25 +3370,25 @@ static int cam_ife_csid_ver2_program_rdi_path(
 			csid_hw->hw_intf->hw_idx, res->res_id);
 
 		/*Program the camif part */
-		cam_io_w_mb(path_cfg->camif_data.epoch0 <<
-			path_reg->epoch0_shift_val,
+		cam_io_w_mb(path_cfg->epoch_cfg << path_reg->epoch0_shift_val,
 			mem_base + path_reg->epoch_irq_cfg_addr);
 	}
 
 	val = csid_hw->debug_info.path_mask;
 
 	if (res->is_rdi_primary_res) {
-		val |= path_reg->camif_irq_mask;
-		path_cfg->handle_camif_irq = true;
+		val |= path_reg->rup_irq_mask;
+		if (path_cfg->handle_camif_irq)
+			val |= path_reg->sof_irq_mask | path_reg->eof_irq_mask;
 	}
 
 	/* Enable secondary events dictated by HW mgr for RDI paths */
 	if (path_cfg->sec_evt_config.en_secondary_evt) {
 		if (path_cfg->sec_evt_config.evt_type & CAM_IFE_CSID_EVT_SOF)
-			val |= IFE_CSID_VER2_PATH_CAMIF_SOF;
+			val |= path_reg->sof_irq_mask;
 
 		if (path_cfg->sec_evt_config.evt_type & CAM_IFE_CSID_EVT_EPOCH)
-			val |= IFE_CSID_VER2_PATH_CAMIF_EPOCH0;
+			val |= path_reg->epoch0_irq_mask;
 
 		CAM_DBG(CAM_ISP,
 			"Enable camif: %d evt irq for res: %s",
@@ -3480,12 +3456,12 @@ static int cam_ife_csid_ver2_program_ipp_path(
 	mem_base = soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base;
 	path_cfg = (struct cam_ife_csid_ver2_path_cfg *)res->res_priv;
 
-	cam_io_w_mb(path_cfg->camif_data.epoch0 << path_reg->epoch0_shift_val,
+	cam_io_w_mb(path_cfg->epoch_cfg << path_reg->epoch0_shift_val,
 		mem_base + path_reg->epoch_irq_cfg_addr);
 
 	CAM_DBG(CAM_ISP, "csid[%d] frame_cfg 0x%x epoch_cfg 0x%x",
 			csid_hw->hw_intf->hw_idx,
-			val, path_cfg->camif_data.epoch0);
+			val, path_cfg->epoch_cfg);
 
 	path_cfg->irq_reg_idx = cam_ife_csid_get_rt_irq_idx(
 			CAM_IFE_CSID_IRQ_REG_IPP,
@@ -3497,8 +3473,10 @@ static int cam_ife_csid_ver2_program_ipp_path(
 
 	if (path_cfg->sync_mode == CAM_ISP_HW_SYNC_NONE ||
 		path_cfg->sync_mode == CAM_ISP_HW_SYNC_MASTER) {
-		val |= path_reg->camif_irq_mask;
-		path_cfg->handle_camif_irq = true;
+		val |= path_reg->rup_irq_mask;
+		if (path_cfg->handle_camif_irq)
+			val |= path_reg->sof_irq_mask | path_reg->epoch0_irq_mask |
+				path_reg->eof_irq_mask;
 	}
 
 	irq_mask = path_reg->fatal_err_mask | path_reg->non_fatal_err_mask;
@@ -3644,9 +3622,6 @@ static int cam_ife_csid_ver2_program_ppp_path(
 
 	path_cfg = (struct cam_ife_csid_ver2_path_cfg *)res->res_priv;
 
-	cam_io_w_mb(path_cfg->camif_data.epoch0 << path_reg->epoch0_shift_val,
-		mem_base + path_reg->epoch_irq_cfg_addr);
-
 	path_cfg->irq_reg_idx = cam_ife_csid_get_rt_irq_idx(
 				CAM_IFE_CSID_IRQ_REG_PPP,
 				csid_reg->cmn_reg->num_pix,
@@ -5335,6 +5310,37 @@ static int cam_ife_csid_ver2_rdi_lcr_cfg(
 	return 0;
 }
 
+static int cam_ife_csid_init_config_update(
+	void *cmd_args, uint32_t arg_size)
+{
+	struct cam_isp_hw_init_config_update *init_cfg = cmd_args;
+	struct cam_isp_resource_node *res = init_cfg->node_res;
+	struct cam_ife_csid_ver2_path_cfg *path_cfg = NULL;
+
+	if (arg_size != sizeof(struct cam_isp_hw_init_config_update)) {
+		CAM_ERR(CAM_ISP, "Invalid args size expected: %zu actual: %zu",
+			sizeof(struct cam_isp_hw_init_config_update),
+			arg_size);
+		return -EINVAL;
+	}
+
+	path_cfg = (struct cam_ife_csid_ver2_path_cfg *)res->res_priv;
+	path_cfg->epoch_cfg = (path_cfg->end_line - path_cfg->start_line) *
+		init_cfg->init_config->epoch_cfg.epoch_factor / 100;
+
+	if (path_cfg->epoch_cfg > path_cfg->end_line)
+		path_cfg->epoch_cfg = path_cfg->end_line;
+
+	if (path_cfg->horizontal_bin || path_cfg->qcfa_bin)
+		path_cfg->epoch_cfg >>= 1;
+
+	CAM_DBG(CAM_ISP,
+		"Init Update for res_name: %s epoch_factor: %x",
+		res->res_name, path_cfg->epoch_cfg);
+
+	return 0;
+}
+
 static int cam_ife_csid_ver2_process_cmd(void *hw_priv,
 	uint32_t cmd_type, void *cmd_args, uint32_t arg_size)
 {
@@ -5422,6 +5428,9 @@ static int cam_ife_csid_ver2_process_cmd(void *hw_priv,
 		/* Not supported on ver2 */
 		rc = 0;
 		break;
+	case CAM_ISP_HW_CMD_INIT_CONFIG_UPDATE:
+		rc = cam_ife_csid_init_config_update(cmd_args, arg_size);
+		break;
 	default:
 		CAM_ERR(CAM_ISP, "CSID:%d unsupported cmd:%d",
 			csid_hw->hw_intf->hw_idx, cmd_type);

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h

@@ -115,17 +115,6 @@ struct cam_ife_csid_ver2_evt_payload {
 	uint32_t                    irq_reg_val;
 };
 
-/*
- * struct cam_ife_csid_ver2_camif_data: place holder for camif parameters
- *
- * @epoch0_cfg:   Epoch 0 configuration value
- * @epoch1_cfg:   Epoch 1 configuration value
- */
-struct cam_ife_csid_ver2_camif_data {
-	uint32_t epoch0;
-	uint32_t epoch1;
-};
-
 /*
  * struct cam_ife_csid_ver2_path_cfg: place holder for path parameters
  *
@@ -155,6 +144,7 @@ struct cam_ife_csid_ver2_camif_data {
  * @irq_reg_idx:            IRQ Reg index
  * @sof_cnt:                SOF counter
  * @num_frames_discard:     number of frames to discard
+ * @epoch_cfg:              Epoch configured value
  * @sync_mode   :           Sync mode--> master/slave/none
  * @vfr_en   :              flag to indicate if variable frame rate is enabled
  * @frame_id_dec_en:        flag to indicate if frame id decoding is enabled
@@ -171,7 +161,6 @@ struct cam_ife_csid_ver2_camif_data {
  *
  */
 struct cam_ife_csid_ver2_path_cfg {
-	struct cam_ife_csid_ver2_camif_data  camif_data;
 	struct timespec64                    error_ts;
 	struct cam_ife_csid_path_format      path_format[CAM_ISP_VC_DT_CFG];
 	struct cam_csid_secondary_evt_config sec_evt_config;
@@ -198,17 +187,18 @@ struct cam_ife_csid_ver2_path_cfg {
 	uint32_t                             irq_reg_idx;
 	uint32_t                             sof_cnt;
 	uint32_t                             num_frames_discard;
+	uint32_t                             epoch_cfg;
 	enum cam_isp_hw_sync_mode            sync_mode;
 	bool                                 vfr_en;
 	bool                                 frame_id_dec_en;
 	bool                                 crop_enable;
 	bool                                 drop_enable;
-	bool                                 handle_camif_irq;
 	bool                                 discard_init_frames;
 	bool                                 skip_discard_frame_cfg;
 	bool                                 sfe_shdr;
 	bool                                 lcr_en;
 	bool                                 csid_out_unpack_msb;
+	bool                                 handle_camif_irq;
 };
 
 struct cam_ife_csid_ver2_top_reg_info {
@@ -347,7 +337,11 @@ struct cam_ife_csid_ver2_path_reg_info {
 	uint32_t fatal_err_mask;
 	uint32_t non_fatal_err_mask;
 	uint32_t pix_pattern_shift;
-	uint32_t camif_irq_mask;
+	uint32_t rup_irq_mask;
+	uint32_t sof_irq_mask;
+	uint32_t eof_irq_mask;
+	uint32_t epoch0_irq_mask;
+	uint32_t epoch1_irq_mask;
 	uint32_t rup_aup_mask;
 	uint32_t top_irq_mask;
 	uint32_t epoch0_cfg_val;
@@ -465,6 +459,7 @@ struct cam_ife_csid_ver2_common_reg_info {
 	uint32_t only_master_rup;
 	uint32_t sfe_ipp_input_rdi_res;
 	bool     timestamp_enabled_in_cfg0;
+	bool     camif_irq_support;
 
 	/* Masks */
 	uint32_t pxl_cnt_mask;
@@ -492,7 +487,7 @@ struct cam_ife_csid_ver2_common_reg_info {
 	uint32_t top_err_irq_mask;
 	uint32_t top_reset_irq_mask;
 	uint32_t top_buf_done_irq_mask;
-	uint32_t epoch_div_factor;
+	uint32_t epoch_factor;
 	uint32_t decode_format_payload_only;
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite680.h

@@ -419,6 +419,7 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.global_reset                                 = 1,
 	.rup_supported                                = 1,
 	.only_master_rup                              = 1,
+	.camif_irq_support                            = true,
 };
 
 static struct cam_ife_csid_csi2_rx_reg_info
@@ -584,7 +585,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.start_master_sel_shift_val       = 4,
 		.fatal_err_mask                   = 0x4,
 		.non_fatal_err_mask               = 0x10080000,
-		.camif_irq_mask                   = 0x800000,
+		.sof_irq_mask                     = 0x10,
+		.rup_irq_mask                     = 0x800000,
+		.epoch0_irq_mask                  = 0x200000,
+		.epoch1_irq_mask                  = 0x400000,
+		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x10001,
 		.top_irq_mask                     = 0x10,
 };
@@ -672,7 +677,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en              = 1,
 		.fatal_err_mask                 = 0x4,
 		.non_fatal_err_mask             = 0x10080000,
-		.camif_irq_mask                 = 0x800000,
+		.sof_irq_mask                   = 0x10,
+		.rup_irq_mask                   = 0x800000,
+		.epoch0_irq_mask                = 0x200000,
+		.epoch1_irq_mask                = 0x400000,
+		.eof_irq_mask                   = 0x8,
 		.rup_aup_mask                   = 0x100010,
 		.top_irq_mask                   = 0x100,
 		.epoch0_shift_val               = 16,
@@ -762,7 +771,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en              = 1,
 		.fatal_err_mask                 = 0x4,
 		.non_fatal_err_mask             = 0x10080000,
-		.camif_irq_mask                 = 0x800000,
+		.sof_irq_mask                   = 0x10,
+		.rup_irq_mask                   = 0x800000,
+		.epoch0_irq_mask                = 0x200000,
+		.epoch1_irq_mask                = 0x400000,
+		.eof_irq_mask                   = 0x8,
 		.rup_aup_mask                   = 0x200020,
 		.top_irq_mask                   = 0x200,
 		.epoch0_shift_val               = 16,
@@ -852,7 +865,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en              = 1,
 		.fatal_err_mask                 = 0x4,
 		.non_fatal_err_mask             = 0x10080000,
-		.camif_irq_mask                 = 0x800000,
+		.sof_irq_mask                   = 0x10,
+		.rup_irq_mask                   = 0x800000,
+		.epoch0_irq_mask                = 0x200000,
+		.epoch1_irq_mask                = 0x400000,
+		.eof_irq_mask                   = 0x8,
 		.rup_aup_mask                   = 0x400040,
 		.top_irq_mask                   = 0x400,
 		.epoch0_shift_val               = 16,
@@ -942,7 +959,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en              = 1,
 		.fatal_err_mask                 = 0x4,
 		.non_fatal_err_mask             = 0x10080000,
-		.camif_irq_mask                 = 0x800000,
+		.sof_irq_mask                   = 0x10,
+		.rup_irq_mask                   = 0x800000,
+		.epoch0_irq_mask                = 0x200000,
+		.epoch1_irq_mask                = 0x400000,
+		.eof_irq_mask                   = 0x8,
 		.rup_aup_mask                   = 0x800080,
 		.top_irq_mask                   = 0x800,
 		.epoch0_shift_val               = 16,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite780.h

@@ -457,6 +457,7 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.top_buf_done_irq_mask                        = 0x2000,
 	.decode_format_payload_only                   = 0xF,
 	.timestamp_enabled_in_cfg0                    = true,
+	.camif_irq_support                            = true,
 };
 
 static struct cam_ife_csid_csi2_rx_reg_info
@@ -622,7 +623,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.start_master_sel_shift_val           = 4,
 		.fatal_err_mask                       = 0x7,
 		.non_fatal_err_mask                   = 0x10080000,
-		.camif_irq_mask                       = 0x800000,
+		.sof_irq_mask                         = 0x10,
+		.rup_irq_mask                         = 0x800000,
+		.epoch0_irq_mask                      = 0x200000,
+		.epoch1_irq_mask                      = 0x400000,
+		.eof_irq_mask                         = 0x8,
 		.rup_aup_mask                         = 0x10001,
 		.top_irq_mask                         = 0x10,
 };
@@ -710,7 +715,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                   = 1,
 		.fatal_err_mask                      = 0x5,
 		.non_fatal_err_mask                  = 0x10080000,
-		.camif_irq_mask                      = 0x800000,
+		.sof_irq_mask                         = 0x10,
+		.rup_irq_mask                         = 0x800000,
+		.epoch0_irq_mask                      = 0x200000,
+		.epoch1_irq_mask                      = 0x400000,
+		.eof_irq_mask                         = 0x8,
 		.rup_aup_mask                        = 0x100010,
 		.top_irq_mask                        = 0x100,
 };
@@ -798,7 +807,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                   = 1,
 		.fatal_err_mask                      = 0x5,
 		.non_fatal_err_mask                  = 0x10080000,
-		.camif_irq_mask                      = 0x800000,
+		.sof_irq_mask                         = 0x10,
+		.rup_irq_mask                         = 0x800000,
+		.epoch0_irq_mask                      = 0x200000,
+		.epoch1_irq_mask                      = 0x400000,
+		.eof_irq_mask                         = 0x8,
 		.rup_aup_mask                        = 0x200020,
 		.top_irq_mask                        = 0x200,
 };
@@ -886,7 +899,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                   = 1,
 		.fatal_err_mask                      = 0x5,
 		.non_fatal_err_mask                  = 0x10080000,
-		.camif_irq_mask                      = 0x800000,
+		.sof_irq_mask                         = 0x10,
+		.rup_irq_mask                         = 0x800000,
+		.epoch0_irq_mask                      = 0x200000,
+		.epoch1_irq_mask                      = 0x400000,
+		.eof_irq_mask                         = 0x8,
 		.rup_aup_mask                        = 0x400040,
 		.top_irq_mask                        = 0x400,
 };
@@ -974,7 +991,11 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                   = 1,
 		.fatal_err_mask                      = 0x5,
 		.non_fatal_err_mask                  = 0x10080000,
-		.camif_irq_mask                      = 0x800000,
+		.sof_irq_mask                         = 0x10,
+		.rup_irq_mask                         = 0x800000,
+		.epoch0_irq_mask                      = 0x200000,
+		.epoch1_irq_mask                      = 0x400000,
+		.eof_irq_mask                         = 0x8,
 		.rup_aup_mask                        = 0x800080,
 		.top_irq_mask                        = 0x800,
 };

drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h

@@ -78,6 +78,7 @@ enum cam_ife_csid_secondary_evt_type {
  * @global_reset_en:       flag to indicate if global reset is enabled
  * @rup_en:                flag to indicate if rup is on csid side
  * @only_master_rup:       flag to indicate if only master RUP
+ * @camif_irq_support:     flag to indicate if CSID supports CAMIF irq
  */
 struct cam_ife_csid_hw_caps {
 	uint32_t      num_rdis;
@@ -91,6 +92,7 @@ struct cam_ife_csid_hw_caps {
 	bool          global_reset_en;
 	bool          rup_en;
 	bool          only_master_rup;
+	bool          camif_irq_support;
 };
 
 struct cam_isp_out_port_generic_info {
@@ -200,6 +202,7 @@ struct cam_csid_secondary_evt_config {
  * @cb_priv:             Private pointer to return to callback
  * @sfe_en:              Flag to indicate if SFE is enabled
  * @use_wm_pack:         [OUT]Flag to indicate if WM packing is to be used for packing
+ * @handle_camif_irq:    Flag to indicate if CSID IRQ is enabled
  *
  */
 struct cam_csid_hw_reserve_resource_args {
@@ -225,6 +228,7 @@ struct cam_csid_hw_reserve_resource_args {
 	void                                     *cb_priv;
 	bool                                      sfe_en;
 	bool                                      use_wm_pack;
+	bool                                      handle_camif_irq;
 };
 
 /**

drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h

@@ -175,6 +175,7 @@ struct cam_vfe_hw_vfe_out_acquire_args {
  * @in_port:                 Input port details to acquire
  * @is_fe_enabled:           Flag to indicate if FE is enabled
  * @is_offline:              Flag to indicate Offline IFE
+ * @handle_camif_irq:        Flag to handle the cmaif irq in VFE
  */
 struct cam_vfe_hw_vfe_in_acquire_args {
 	struct cam_isp_resource_node         *rsrc_node;
@@ -186,6 +187,7 @@ struct cam_vfe_hw_vfe_in_acquire_args {
 	struct cam_isp_in_port_generic_info  *in_port;
 	bool                                  is_fe_enabled;
 	bool                                  is_offline;
+	bool                                  handle_camif_irq;
 };
 
 /*

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c

@@ -76,7 +76,6 @@ struct cam_vfe_mux_ver4_data {
 	uint32_t                           last_line;
 	uint32_t                           hbi_value;
 	uint32_t                           vbi_value;
-	bool                               enable_sof_irq_debug;
 	uint32_t                           irq_debug_cnt;
 	uint32_t                           camif_debug;
 	uint32_t                           horizontal_bin;
@@ -84,18 +83,19 @@ struct cam_vfe_mux_ver4_data {
 	uint32_t                           dual_hw_idx;
 	uint32_t                           is_dual;
 	uint32_t                           epoch_factor;
-	bool                               is_fe_enabled;
-	bool                               is_offline;
-	bool                               is_lite;
-	bool                               is_pixel_path;
-	bool                               sfe_binned_epoch_cfg;
-
 	struct timespec64                  sof_ts;
 	struct timespec64                  epoch_ts;
 	struct timespec64                  eof_ts;
 	struct timespec64                  error_ts;
 	enum cam_vfe_top_ver4_fsm_state    fsm_state;
 	uint32_t                           n_frame_irqs;
+	bool                               is_fe_enabled;
+	bool                               is_offline;
+	bool                               is_lite;
+	bool                               is_pixel_path;
+	bool                               sfe_binned_epoch_cfg;
+	bool                               enable_sof_irq_debug;
+	bool                               handle_camif_irq;
 };
 
 static int cam_vfe_top_ver4_get_path_port_map(struct cam_vfe_top_ver4_priv *top_priv,
@@ -745,6 +745,7 @@ int cam_vfe_top_acquire_resource(
 	res_data->hbi_value      = 0;
 	res_data->sfe_binned_epoch_cfg =
 		acquire_data->vfe_in.in_port->sfe_binned_epoch_cfg;
+	res_data->handle_camif_irq   = acquire_data->vfe_in.handle_camif_irq;
 
 	if (res_data->is_dual)
 		res_data->dual_hw_idx = acquire_data->vfe_in.dual_hw_idx;
@@ -1601,9 +1602,11 @@ skip_core_cfg:
 	/* Skip subscribing to timing irqs in these scenarios:
 	 *     1. Resource is dual IFE slave
 	 *     2. Resource is not primary RDI
+	 *     3. non-sfe use cases, such cases are taken care in CSID.
 	 */
 	if (((rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) && rsrc_data->is_dual) ||
-		(!rsrc_data->is_pixel_path && !vfe_res->is_rdi_primary_res))
+		(!rsrc_data->is_pixel_path && !vfe_res->is_rdi_primary_res) ||
+		!rsrc_data->handle_camif_irq)
 		goto subscribe_err;
 
 	irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = rsrc_data->reg_data->sof_irq_mask |