msm: camera: csiphy: Enable PN9 infinite loop for test

Enable PN9 infinite loop for test. Also move the PN9 status
check from polling to one time read at streamoff.

CRs-Fixed: 3054225
Change-Id: Ia4d8ff17e3c78f37adb68ad9a4afb076fe2bda45
Signed-off-by: Jigarkumar Zala <[email protected]>

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

@@ -1484,33 +1484,40 @@ int cam_csiphy_util_update_aon_ops(
 	return rc;
 }
 
-static void __cam_csiphy_read_2phase_bist_debug_status(
-	struct csiphy_device *csiphy_dev)
+static void __cam_csiphy_read_2phase_bist_counter_status(
+	struct csiphy_device *csiphy_dev, uint32_t *counter)
 {
-	int i = 0;
+	int i = 0, lane_count;
 	int bist_status_arr_size =
-		csiphy_dev->ctrl_reg->csiphy_bist_reg->num_status_err_check_reg;
-	struct csiphy_reg_t *csiphy_common_reg = NULL;
-	void __iomem *csiphybase = NULL;
-
-	csiphybase = csiphy_dev->soc_info.reg_map[0].mem_base;
+		csiphy_dev->ctrl_reg->csiphy_bist_reg->number_of_counters;
+	uint32_t base_offset = 0;
+	void __iomem *phy_base = NULL;
+	uint32_t val = 0;
+	uint32_t offset_betwn_lane = 0;
+	struct bist_reg_settings_t *bist_reg = NULL;
+
+	phy_base = csiphy_dev->soc_info.reg_map[0].mem_base;
+	bist_reg = csiphy_dev->ctrl_reg->csiphy_bist_reg;
+	offset_betwn_lane =
+		csiphy_dev->ctrl_reg->csiphy_reg.size_offset_betn_lanes;
 
 	for (i = 0; i < bist_status_arr_size; i++) {
-		csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_bist_reg
-			->bist_status_err_check_arr[i];
-		switch (csiphy_common_reg->csiphy_param_type) {
-		case CSIPHY_2PH_REGS:
-			CAM_INFO(CAM_CSIPHY, "OFFSET: 0x%x value: 0x%x",
-				csiphybase + csiphy_common_reg->reg_addr,
-				cam_io_r(csiphybase + csiphy_common_reg->reg_addr));
-		break;
+		base_offset = bist_reg->bist_counter_2ph_base_offset + (0x4 * i);
+		val = 0;
+		for (lane_count = 0; lane_count < CAM_CSIPHY_MAX_DPHY_LANES; lane_count++) {
+			CAM_DBG(CAM_CSIPHY, "value to be read from addr: 0x%x is 0x%x",
+				base_offset + (lane_count * offset_betwn_lane),
+				(cam_io_r(phy_base + base_offset + (lane_count * offset_betwn_lane))));
+			val |= ((cam_io_r(phy_base + base_offset + (lane_count * offset_betwn_lane))));
 		}
+		*counter |= (val << (i * 8));
+		CAM_DBG(CAM_CSIPHY, "COUNTER VALUE is 0x%x", *counter);
 	}
 
 	return;
 }
 
-static void __cam_csiphy_poll_2phase_pattern_status(
+static void __cam_csiphy_get_2phase_pattern_status(
 	struct csiphy_device *csiphy_dev)
 {
 	int i = 0;
@@ -1518,32 +1525,19 @@ static void __cam_csiphy_poll_2phase_pattern_status(
 		csiphy_dev->ctrl_reg->csiphy_bist_reg->num_status_reg;
 	struct csiphy_reg_t *csiphy_common_reg = NULL;
 	void __iomem *csiphybase = NULL;
-	uint32_t status = 0x00;
+	uint32_t status = 0;
+	uint32_t counter = 0;
+	struct bist_reg_settings_t *bist_reg = NULL;
 
+	CAM_DBG(CAM_CSIPHY, "ENTER");
 	csiphybase = csiphy_dev->soc_info.reg_map[0].mem_base;
-
-	do {
-		usleep_range(2000, 2010);
-		for (i = 0; i < bist_status_arr_size; i++) {
-			csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_bist_reg->bist_arry[i];
-			switch (csiphy_common_reg->csiphy_param_type) {
-			case CSIPHY_2PH_REGS:
-				status |= cam_io_r(csiphybase + csiphy_common_reg->reg_addr);
-			break;
-			}
-
-			if (status != 0) {
-				CAM_INFO(CAM_CSIPHY, "PN9 Pattern Test is completed");
-				break;
-			}
-		}
-	} while (!status);
+	bist_reg = csiphy_dev->ctrl_reg->csiphy_bist_reg;
 
 	/* This loop is to read every lane status value
 	 * in case if loop breaks with only last lane.
 	 */
 	for (i = 0; i < bist_status_arr_size; i++) {
-		csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_bist_reg->bist_arry[i];
+		csiphy_common_reg = &bist_reg->bist_status_arr[i];
 		switch (csiphy_common_reg->csiphy_param_type) {
 		case CSIPHY_2PH_REGS:
 			status |= cam_io_r(csiphybase + csiphy_common_reg->reg_addr);
@@ -1551,41 +1545,110 @@ static void __cam_csiphy_poll_2phase_pattern_status(
 		}
 	}
 
-	if (status == csiphy_dev->ctrl_reg->csiphy_bist_reg->expected_status_val)
-		CAM_INFO(CAM_CSIPHY, "PN9 Pattern received successfully");
-	else
-		__cam_csiphy_read_2phase_bist_debug_status(csiphy_dev);
+	/* Read the Counter value for possible corrupted headers */
+	__cam_csiphy_read_2phase_bist_counter_status(csiphy_dev, &counter);
+
+	if ((status & PREAMBLE_PATTERN_BIST_DONE) &&
+		(status & bist_reg->error_status_val_2ph)) {
+		/**
+		 * This condition happen when CSIPHY try to read status after sensor
+		 * streamoff. In this case error bit is set due to postamble detection
+		 * which is bit(4). In this scenraio this is not consider as an error.
+		 * We need to check for status2/3 counter value to determine if there are
+		 * more header that is corrupted than 2. Counter always shows value of 2
+		 * with postamble packet.
+		 *
+		 */
+		if (counter <= PREAMBLE_MAX_ERR_COUNT_ALLOWED) {
+			CAM_INFO(CAM_CSIPHY,
+				"PN9 Pattern rxced succesfully:: counter value: 0x%x, Status0: 0x%x",
+				counter, status);
+		} else {
+			CAM_INFO(CAM_CSIPHY,
+				"PN9 Pattern is corrupted:: counter value: 0x%x, Status0: 0x%x",
+				counter, status);
+		}
+	} else if ((status & PREAMBLE_PATTERN_BIST_DONE) &&
+		!(status & bist_reg->error_status_val_2ph)) {
+		/**
+		 * This condition happen when CSIPHY try to read status with some counter
+		 * value is set to check against. In this case error bit is not expected
+		 * to be set.
+		 */
+		CAM_INFO(CAM_CSIPHY,
+			"PN9 Pattern rxced succesfully:: counter value: 0x%x, Status0: 0x%x",
+			counter, status);
+	} else {
+		CAM_INFO(CAM_CSIPHY,
+			"PN9 Pattern is corrupted:: counter value: 0x%x Status0: 0x%x",
+			counter, status);
+	}
 
 	return;
 }
 
-static void __cam_csiphy_read_3phase_bist_debug_status(
-	struct csiphy_device *csiphy_dev)
+static void __cam_csiphy_2ph_status_checker_ops(
+	struct csiphy_device *csiphy_dev, bool set)
 {
 	int i = 0;
-	int bist_status_arr_size =
-		csiphy_dev->ctrl_reg->csiphy_bist_reg->num_status_err_check_reg;
-	struct csiphy_reg_t *csiphy_common_reg = NULL;
 	void __iomem *csiphybase = NULL;
+	uint32_t base_offset = 0;
+	uint32_t read_back_value;
+	uint32_t lane_offset = 0;
+	uint32_t offset_betwn_lane = 0;
+	struct bist_reg_settings_t *bist_reg = NULL;
 
 	csiphybase = csiphy_dev->soc_info.reg_map[0].mem_base;
+	bist_reg = csiphy_dev->ctrl_reg->csiphy_bist_reg;
+	base_offset = bist_reg->set_status_update_2ph_base_offset;
+	offset_betwn_lane =
+		csiphy_dev->ctrl_reg->csiphy_reg.size_offset_betn_lanes;
+
+	/* Set checker bit to read the correct status1 value */
+	for (i = 0; i < CAM_CSIPHY_MAX_DPHY_LANES; i++) {
+		lane_offset = base_offset + (i * offset_betwn_lane);
+		read_back_value = cam_io_r(csiphybase + lane_offset);
+		set ? (read_back_value |= PREAMBLE_PATTERN_SET_CHECKER) :
+			(read_back_value &= ~PREAMBLE_PATTERN_SET_CHECKER);
+		cam_io_w_mb(read_back_value, csiphybase + lane_offset);
+	}
+}
+
+static void __cam_csiphy_read_3phase_bist_counter_status(
+	struct csiphy_device *csiphy_dev, uint32_t *counter)
+{
+	int i = 0, lane_count;
+	int bist_status_arr_size =
+		csiphy_dev->ctrl_reg->csiphy_bist_reg->number_of_counters;
+	uint32_t base_offset = 0;
+	void __iomem *phy_base = NULL;
+	uint32_t val = 0;
+	uint32_t offset_betwn_lane = 0;
+	struct bist_reg_settings_t *bist_reg = NULL;
+
+	phy_base = csiphy_dev->soc_info.reg_map[0].mem_base;
+	bist_reg = csiphy_dev->ctrl_reg->csiphy_bist_reg;
+	offset_betwn_lane =
+		csiphy_dev->ctrl_reg->csiphy_reg.size_offset_betn_lanes;
 
 	for (i = 0; i < bist_status_arr_size; i++) {
-		csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_bist_reg
-			->bist_status_err_check_arr[i];
-		switch (csiphy_common_reg->csiphy_param_type) {
-		case CSIPHY_3PH_REGS:
-				CAM_INFO(CAM_CSIPHY, "OFFSET: 0x%x value: 0x%x",
-					csiphybase + csiphy_common_reg->reg_addr,
-					cam_io_r(csiphybase + csiphy_common_reg->reg_addr));
-		break;
+		base_offset = bist_reg->bist_counter_3ph_base_offset + (0x4 * i);
+		val = 0;
+		for (lane_count = 0; lane_count < CAM_CSIPHY_MAX_CPHY_LANES; lane_count++) {
+			CAM_DBG(CAM_CSIPHY, "value to be read from addr: 0x%x is 0x%x",
+				base_offset + (lane_count * offset_betwn_lane),
+				(cam_io_r(phy_base + base_offset + (lane_count * offset_betwn_lane))));
+			val |= ((cam_io_r(phy_base + base_offset + (lane_count * offset_betwn_lane))));
 		}
+
+		*counter |= (val << (i * 8));
+		CAM_DBG(CAM_CSIPHY, "COUNTER VALUE is 0x%x", *counter);
 	}
 
 	return;
 }
 
-static void __cam_csiphy_poll_3phase_pattern_status(
+static void __cam_csiphy_get_3phase_pattern_status(
 	struct csiphy_device *csiphy_dev)
 {
 	int i = 0;
@@ -1593,31 +1656,25 @@ static void __cam_csiphy_poll_3phase_pattern_status(
 		csiphy_dev->ctrl_reg->csiphy_bist_reg->num_status_reg;
 	struct csiphy_reg_t *csiphy_common_reg = NULL;
 	void __iomem *csiphybase = NULL;
-	uint32_t status1 = 0x00;
+	uint32_t base_offset = 0;
+	uint32_t lane_offset = 0;
+	uint32_t status1 = 0, status0 = 0;
+	uint32_t counter = 0;
+	uint32_t offset_betwn_lane = 0;
+	struct bist_reg_settings_t *bist_reg = NULL;
 
+	CAM_DBG(CAM_CSIPHY, "ENTER");
 	csiphybase = csiphy_dev->soc_info.reg_map[0].mem_base;
-
-	do {
-		usleep_range(2000, 2010);
-		for (i = 0; i < bist_status_arr_size; i++) {
-			csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_bist_reg->bist_status_arr[i];
-			switch (csiphy_common_reg->csiphy_param_type) {
-			case CSIPHY_3PH_REGS:
-				status1 |= cam_io_r(csiphybase + csiphy_common_reg->reg_addr);
-			break;
-			}
-			if (status1 != 0) {
-				CAM_INFO(CAM_CSIPHY, "PN9 Pattern test is completed");
-				break;
-			}
-		}
-	} while (!status1);
+	bist_reg = csiphy_dev->ctrl_reg->csiphy_bist_reg;
+	base_offset = bist_reg->bist_sensor_data_3ph_status_base_offset;
+	offset_betwn_lane =
+		csiphy_dev->ctrl_reg->csiphy_reg.size_offset_betn_lanes;
 
 	/* This loop is to read every lane status value
 	 * in case if loop breaks with only last lane.
 	 */
 	for (i = 0; i < bist_status_arr_size; i++) {
-		csiphy_common_reg = &csiphy_dev->ctrl_reg->csiphy_bist_reg->bist_status_arr[i];
+		csiphy_common_reg = &bist_reg->bist_status_arr[i];
 		switch (csiphy_common_reg->csiphy_param_type) {
 		case CSIPHY_3PH_REGS:
 			status1 |= cam_io_r(csiphybase + csiphy_common_reg->reg_addr);
@@ -1625,44 +1682,97 @@ static void __cam_csiphy_poll_3phase_pattern_status(
 		}
 	}
 
-	if (status1 == csiphy_dev->ctrl_reg->csiphy_bist_reg->expected_status_val)
-		CAM_INFO(CAM_CSIPHY, "PN9 Pattern received successfully");
-	else
-		__cam_csiphy_read_3phase_bist_debug_status(csiphy_dev);
+	/* Read Status0 value to detect sensor related communication */
+	for (i = 0; i < CAM_CSIPHY_MAX_CPHY_LANES; i++) {
+		lane_offset = base_offset + (i * offset_betwn_lane);
+		status0 |= cam_io_r(csiphybase + lane_offset);
+	}
+
+
+	/* Read the Counter value for possible corrupted headers */
+	__cam_csiphy_read_3phase_bist_counter_status(csiphy_dev, &counter);
+
+	if ((status1 & PREAMBLE_PATTERN_BIST_DONE) &&
+		(status1 & bist_reg->error_status_val_3ph)) {
+		/**
+		 * This condition happen when CSIPHY try to read status after sensor
+		 * streamoff. In this case error bit is set due to postamble detection
+		 * which is bit(4). In this scenraio this is not consider as an error.
+		 * We need to check for status2/3 counter value to determine if there are
+		 * more header that is corrupted than 2. Counter always shows value of 2
+		 * with postamble packet.
+		 *
+		 */
+		if (counter <= PREAMBLE_MAX_ERR_COUNT_ALLOWED) {
+			CAM_INFO(CAM_CSIPHY,
+				"PN9 Pattern rxced succesfully after sensor streamoff:: counter value: 0x%x Status1: 0x%x Status0: 0x%x",
+				counter, status1, status0);
+		} else {
+			CAM_INFO(CAM_CSIPHY,
+				"PN9 Pattern is corrupted:: counter value: 0x%x Status1: 0x%x Status0: 0x%x",
+				counter, status1, status0);
+		}
+	} else if ((status1 & PREAMBLE_PATTERN_BIST_DONE) &&
+		!(status1 & bist_reg->error_status_val_3ph)) {
+		/**
+		 * This condition happen when CSIPHY try to read status with some counter
+		 * value is set to check against. In this case error bit is not expected
+		 * to be set.
+		 */
+		CAM_INFO(CAM_CSIPHY,
+			"PN9 Pattern rxced succesfully before sensor streamoff:: counter value: 0x%x Status1: 0x%x Status0: 0x%x",
+			counter, status1, status0);
+	} else {
+		CAM_INFO(CAM_CSIPHY,
+			"PN9 Pattern is corrupted:: counter value: 0x%x Status1: 0x%x Status0: 0x%x",
+			counter, status1, status0);
+	}
 
 	return;
 }
 
-static void __cam_csiphy_poll_preamble_status(
-	struct csiphy_device *csiphy_dev, int offset)
+static void __cam_csiphy_3ph_status_checker_ops(
+	struct csiphy_device *csiphy_dev, bool set)
 {
-	bool is_3phase = false;
-
-	is_3phase = csiphy_dev->csiphy_info[offset].csiphy_3phase;
-
-	if (is_3phase)
-		__cam_csiphy_poll_3phase_pattern_status(csiphy_dev);
-	else
-		__cam_csiphy_poll_2phase_pattern_status(csiphy_dev);
+	int i = 0;
+	void __iomem *csiphybase = NULL;
+	uint32_t base_offset = 0;
+	uint32_t read_back_value;
+	uint32_t lane_offset = 0;
+	uint32_t offset_betwn_lane = 0;
 
-	return;
+	csiphybase = csiphy_dev->soc_info.reg_map[0].mem_base;
+	base_offset =
+		csiphy_dev->ctrl_reg->csiphy_bist_reg->set_status_update_3ph_base_offset;
+	offset_betwn_lane =
+		csiphy_dev->ctrl_reg->csiphy_reg.size_offset_betn_lanes;
+	/* Set checker bit to read the correct status1 value */
+	for (i = 0; i < CAM_CSIPHY_MAX_CPHY_LANES; i++) {
+		lane_offset = base_offset + (i * offset_betwn_lane);
+		read_back_value = cam_io_r(csiphybase + lane_offset);
+		set ? (read_back_value |= PREAMBLE_PATTERN_SET_CHECKER) :
+			(read_back_value &= ~PREAMBLE_PATTERN_SET_CHECKER);
+		cam_io_w_mb(read_back_value, csiphybase + lane_offset);
+	}
 }
 
-static void csiphy_work_queue_ops(struct work_struct *work)
+static void __cam_csiphy_get_preamble_status(
+	struct csiphy_device *csiphy_dev, int offset)
 {
-	struct csiphy_work_queue *wq = NULL;
-	struct csiphy_device *csiphy_dev = NULL;
-	int32_t offset = -1;
+	bool is_3phase = false;
 
-	wq = container_of(work, struct csiphy_work_queue, work);
-	if (wq) {
-		csiphy_dev = wq->csiphy_dev;
-		offset = wq->acquire_idx;
+	is_3phase = csiphy_dev->csiphy_info[offset].csiphy_3phase;
 
-		__cam_csiphy_poll_preamble_status(csiphy_dev, offset);
+	if (is_3phase) {
+		__cam_csiphy_3ph_status_checker_ops(csiphy_dev, true);
+		__cam_csiphy_get_3phase_pattern_status(csiphy_dev);
+		__cam_csiphy_3ph_status_checker_ops(csiphy_dev, false);
+	} else {
+		__cam_csiphy_2ph_status_checker_ops(csiphy_dev, true);
+		__cam_csiphy_get_2phase_pattern_status(csiphy_dev);
+		__cam_csiphy_2ph_status_checker_ops(csiphy_dev, false);
 	}
-
-	kfree(wq);
+	return;
 }
 
 int32_t cam_csiphy_core_cfg(void *phy_dev,
@@ -1919,6 +2029,9 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 			cam_csiphy_prgm_cmn_data(csiphy_dev, true);
 		}
 
+		if (csiphy_dev->preamble_enable)
+			__cam_csiphy_get_preamble_status(csiphy_dev, offset);
+
 		rc = cam_csiphy_disable_hw(csiphy_dev);
 		if (rc < 0)
 			CAM_ERR(CAM_CSIPHY, "Failed in csiphy release");
@@ -2025,7 +2138,6 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 	}
 	case CAM_START_DEV: {
 		struct cam_start_stop_dev_cmd config;
-		struct csiphy_work_queue *wq;
 		int32_t offset;
 		int clk_vote_level = -1;
 
@@ -2205,19 +2317,6 @@ int32_t cam_csiphy_core_cfg(void *phy_dev,
 			csiphy_dev->start_dev_count);
 		csiphy_dev->csiphy_state = CAM_CSIPHY_START;
 
-		if (csiphy_dev->preamble_enable) {
-			wq = kzalloc(sizeof(struct csiphy_work_queue),
-				GFP_ATOMIC);
-			if (wq) {
-				INIT_WORK((struct work_struct *)
-					&wq->work, csiphy_work_queue_ops);
-				wq->csiphy_dev = csiphy_dev;
-				wq->acquire_idx = offset;
-				queue_work(csiphy_dev->work_queue,
-					&wq->work);
-			}
-		}
-
 		CAM_INFO(CAM_CSIPHY,
 			"CAM_START_PHYDEV: CSIPHY_IDX: %d, Device_slot: %d, cp_mode: %d, Datarate: %llu, Settletime: %llu",
 			csiphy_dev->soc_info.index, offset,

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c

@@ -313,16 +313,6 @@ static int cam_csiphy_component_bind(struct device *dev,
 	snprintf(wq_name, 32, "%s%d%s", "csiphy",
 		new_csiphy_dev->soc_info.index, "_wq");
 
-	new_csiphy_dev->work_queue = alloc_workqueue("wq_name",
-		WQ_UNBOUND | WQ_MEM_RECLAIM, 1);
-	if (!new_csiphy_dev->work_queue) {
-		CAM_ERR(CAM_CSIPHY,
-			"Error allocating workqueue for csiphy: %d",
-			new_csiphy_dev->soc_info.index);
-		rc = -ENOMEM;
-		goto cpas_unregister;
-	}
-
 	rc = cam_csiphy_register_baseaddress(new_csiphy_dev);
 	if (rc) {
 		CAM_ERR(CAM_CSIPHY, "Failed to register baseaddress, rc: %d", rc);
@@ -338,8 +328,6 @@ static int cam_csiphy_component_bind(struct device *dev,
 
 cpas_unregister:
 	cam_cpas_unregister_client(new_csiphy_dev->cpas_handle);
-	if (new_csiphy_dev->work_queue)
-		destroy_workqueue(new_csiphy_dev->work_queue);
 csiphy_unregister_subdev:
 	cam_unregister_subdev(&(new_csiphy_dev->v4l2_dev_str));
 csiphy_no_resource:

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h

@@ -67,6 +67,11 @@
 #define DPHY_LANE_3    BIT(6)
 #define DPHY_CLK_LN    BIT(7)
 
+/* PRBS Pattern Macros */
+#define PREAMBLE_PATTERN_SET_CHECKER    BIT(4)
+#define PREAMBLE_PATTERN_BIST_DONE      BIT(0)
+#define PREAMBLE_MAX_ERR_COUNT_ALLOWED  2
+
 enum cam_csiphy_state {
 	CAM_CSIPHY_INIT,
 	CAM_CSIPHY_ACQUIRE,
@@ -214,13 +219,20 @@ struct data_rate_settings_t {
 };
 
 struct bist_reg_settings_t {
-	uint32_t expected_status_val;
-	ssize_t num_data_settings;
+	uint32_t error_status_val_3ph;
+	uint32_t error_status_val_2ph;
+	uint32_t set_status_update_3ph_base_offset;
+	uint32_t set_status_update_2ph_base_offset;
+	uint32_t bist_status_3ph_base_offset;
+	uint32_t bist_status_2ph_base_offset;
+	uint32_t bist_sensor_data_3ph_status_base_offset;
+	uint32_t bist_counter_3ph_base_offset;
+	uint32_t bist_counter_2ph_base_offset;
+	uint32_t number_of_counters;
 	ssize_t num_status_reg;
-	ssize_t num_status_err_check_reg;
+	ssize_t num_data_settings;
 	struct csiphy_reg_t *bist_arry;
 	struct csiphy_reg_t *bist_status_arr;
-	struct csiphy_reg_t *bist_status_err_check_arr;
 };
 
 /**
@@ -319,7 +331,6 @@ struct csiphy_work_queue {
  * @en_lane_status_reg_dump    : Debugfs flag to enable cphy/dphy lane status dump
  * @en_full_phy_reg_dump       : Debugfs flag to enable the dump for all the Phy registers
  * @preamble_enable            : To enable preamble pattern
- * @work_queue                 : Work queue to offload the work
  */
 struct csiphy_device {
 	char                           device_name[CAM_CTX_DEV_NAME_MAX_LENGTH];
@@ -354,7 +365,6 @@ struct csiphy_device {
 	bool                           en_lane_status_reg_dump;
 	bool                           en_full_phy_reg_dump;
 	uint16_t                       preamble_enable;
-	struct workqueue_struct       *work_queue;
 };
 
 /**

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h

@@ -364,8 +364,8 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x0258, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0254, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x025C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0248, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x024C, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0248, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x024C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0240, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0260, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS},
 	},
@@ -403,8 +403,8 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x0658, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0654, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x065C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0648, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x064C, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0648, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x064C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0640, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0660, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS},
 	},
@@ -442,13 +442,12 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
 		{0x0A58, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A54, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A5C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0A48, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
-		{0x0A4C, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A48, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+		{0x0A4C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A40, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
 		{0x0A60, 0xA8, 0x64, CSIPHY_DEFAULT_PARAMS},
 	},
 };
-
 struct csiphy_reg_t bist_arr_2_1_0[] = {
 	/* 3Phase BIST CONFIGURATION REG SET */
 	{0x02D4, 0x64, 0x00, CSIPHY_3PH_REGS},
@@ -469,36 +468,31 @@ struct csiphy_reg_t bist_arr_2_1_0[] = {
 };
 
 struct csiphy_reg_t bist_status_arr_2_1_0[] = {
-	/* STATUS1 for the BIST checker output for 3phase */
+
 	{0x0344, 0x00, 0x00, CSIPHY_3PH_REGS},
 	{0x0744, 0x00, 0x00, CSIPHY_3PH_REGS},
 	{0x0B44, 0x00, 0x00, CSIPHY_3PH_REGS},
-	/* STATUS0 for BIST checker output for 2phase */
 	{0x00C0, 0x00, 0x00, CSIPHY_2PH_REGS},
 	{0x04C0, 0x00, 0x00, CSIPHY_2PH_REGS},
 	{0x08C0, 0x00, 0x00, CSIPHY_2PH_REGS},
 	{0x0CC0, 0x00, 0x00, CSIPHY_2PH_REGS},
 };
 
-struct csiphy_reg_t bist_status_err_check_arr_2_1_0[] = {
-	/* STATUS2_3 for the BIST word error detection */
-	{0x0348, 0x00, 0x00, CSIPHY_3PH_REGS},
-	{0x0748, 0x00, 0x00, CSIPHY_3PH_REGS},
-	{0x0B48, 0x00, 0x00, CSIPHY_3PH_REGS},
-	{0x034C, 0x00, 0x00, CSIPHY_3PH_REGS},
-	{0x074C, 0x00, 0x00, CSIPHY_3PH_REGS},
-	{0x0B4C, 0x00, 0x00, CSIPHY_3PH_REGS},
-	/* STATUS */
-};
-
 struct bist_reg_settings_t bist_setting_2_1_0 = {
-	.expected_status_val = 0xB,
+	.error_status_val_3ph = 0x10,
+	.error_status_val_2ph = 0x10,
+	.set_status_update_3ph_base_offset = 0x0240,
+	.set_status_update_2ph_base_offset = 0x0050,
+	.bist_status_3ph_base_offset = 0x0344,
+	.bist_status_2ph_base_offset = 0x00C0,
+	.bist_sensor_data_3ph_status_base_offset = 0x0340,
+	.bist_counter_3ph_base_offset = 0x0348,
+	.bist_counter_2ph_base_offset = 0x00C8,
+	.number_of_counters = 2,
 	.num_data_settings = ARRAY_SIZE(bist_arr_2_1_0),
 	.bist_arry = bist_arr_2_1_0,
 	.num_status_reg = ARRAY_SIZE(bist_status_arr_2_1_0),
 	.bist_status_arr = bist_status_arr_2_1_0,
-	.num_status_err_check_reg = ARRAY_SIZE(bist_status_err_check_arr_2_1_0),
-	.bist_status_err_check_arr = bist_status_err_check_arr_2_1_0,
 };
 
 struct data_rate_settings_t data_rate_delta_table_2_1_0 = {