Merge remote-tracking branch 'quic/display-kernel.lnx.5.10' into display-kernel.lnx.5.15
* quic/display-kernel.lnx.5.10: disp: msm: sde: avoid error during fal10_veto override enablement disp: msm: update copyright description disp: msm: sde: configure dest_scaler op_mode for two independent displays disp: msm: dp: updated copyright set for 4nm target Revert "disp: msm: sde: consider max of actual and default prefill lines" disp: msm: sde: Reset backlight scale when HWC is stopped disp: msm: dp: avoid duplicate read of link status disp: msm: dsi: update vreg_ctrl settings for cape disp: msm: fail commit if drm_gem_obj was found attached to a sec CB disp: msm: dp: updated register values for 4nm target disp: msm: sde: update framedata event handling disp: msm: dsi: Add new phy comaptible string for cape disp: msm: sde: software override for fal10 in cwb enable disp: msm: update cleanup during bind failure in msm_drm_component_init disp: msm: sde: dump user input_fence info on spec fence timeout disp: msm: sde: add null pointer check for encoder current master disp: msm: dsi: enable DMA start window scheduling for broadcast commands disp: msm: sde: avoid alignment checks for linear formats disp: msm: reset thread priority work on every new run disp: msm: sde: send power on event for cont. splash disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1" disp: msm: use vzalloc for large allocations disp: msm: sde: Add support to limit DSC size to 10k disp: msm: sde: add tx wait during DMS for sim panel disp: msm: dsi: add check for any queued DSI CMDs before clock force update disp: msm: sde: correct pp block allocation during dcwb dither programming disp: msm: sde: avoid setting of max vblank count disp: msm: sde: add cached lut flag in sde plane disp: msm: sde: avoid use after free in msm_lastclose disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter disp: msm: dsi: Support uncompressed rgb101010 format disp: msm: sde: update idle_pc_enabled flag for all encoders disp: msm: sde: flush esd work before disabling the encoder disp: msm: sde: allow qsync update along with modeset disp: msm: dp: avoid dp sw reset on disconnect path disp: msm: sde: consider max of actual and default prefill lines disp: msm: ensure vbif debugbus not in use is disabled disp: msm: sde: update cached encoder mask if required disp: msm: sde: while timing engine enabling poll for active region disp: msm: enable cache flag for dumb buffer disp: msm: sde: disable ot limit for cwb disp: msm: sde: avoid race condition at vm release disp: msm: dsi: set qsync min fps list length to zero disp: msm: sde: reset mixers in crtc when ctl datapath switches disp: msm: sde: update vm state atomic check for non-primary usecases disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3 Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This commit is contained in:
@@ -71,6 +71,8 @@ static int sde_crtc_mmrm_interrupt_handler(struct drm_crtc *crtc_drm,
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bool en, struct sde_irq_callback *idle_irq);
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static int sde_crtc_pm_event_handler(struct drm_crtc *crtc, bool en,
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struct sde_irq_callback *noirq);
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static int sde_crtc_frame_data_interrupt_handler(struct drm_crtc *crtc_drm,
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bool en, struct sde_irq_callback *idle_irq);
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static int _sde_crtc_set_noise_layer(struct sde_crtc *sde_crtc,
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struct sde_crtc_state *cstate,
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void __user *usr_ptr);
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@@ -89,6 +91,7 @@ static struct sde_crtc_custom_events custom_events[] = {
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{DRM_EVENT_LTM_OFF, sde_cp_ltm_off_event_handler},
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{DRM_EVENT_MMRM_CB, sde_crtc_mmrm_interrupt_handler},
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{DRM_EVENT_VM_RELEASE, sde_crtc_vm_release_handler},
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{DRM_EVENT_FRAME_DATA, sde_crtc_frame_data_interrupt_handler},
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};
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/* default input fence timeout, in ms */
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@@ -576,9 +579,10 @@ static const struct attribute_group *sde_crtc_attr_groups[] = {
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NULL,
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};
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static void sde_crtc_event_notify(struct drm_crtc *crtc, uint32_t type, uint32_t len, uint64_t val)
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static void sde_crtc_event_notify(struct drm_crtc *crtc, uint32_t type, void *payload, uint32_t len)
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{
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struct drm_event event;
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uint32_t *data = (uint32_t *)payload;
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if (!crtc) {
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SDE_ERROR("invalid crtc\n");
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@@ -587,10 +591,12 @@ static void sde_crtc_event_notify(struct drm_crtc *crtc, uint32_t type, uint32_t
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event.type = type;
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event.length = len;
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msm_mode_object_event_notify(&crtc->base, crtc->dev, &event, (u8 *)&val);
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msm_mode_object_event_notify(&crtc->base, crtc->dev, &event, (u8 *)payload);
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SDE_EVT32(DRMID(crtc), type, len, val >> 32, val & 0xFFFFFFFF);
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SDE_DEBUG("crtc:%d event(%d) value(%llu) notified\n", DRMID(crtc), type, val);
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SDE_EVT32(DRMID(crtc), type, len, *data,
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((uint64_t)payload) >> 32, ((uint64_t)payload) & 0xFFFFFFFF);
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SDE_DEBUG("crtc:%d event(%lu) ptr(%pK) value(%lu) notified\n",
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DRMID(crtc), type, payload, *data);
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}
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static void sde_crtc_destroy(struct drm_crtc *crtc)
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@@ -2495,6 +2501,7 @@ static int _sde_crtc_get_frame_data_buffer(struct drm_crtc *crtc, uint32_t fd)
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return -ENOMEM;
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sde_crtc->frame_data.buf[cur_buf] = buf;
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buf->fd = fd;
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buf->fb = drm_framebuffer_lookup(crtc->dev, NULL, fd);
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if (!buf->fb) {
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SDE_ERROR("unable to get fb");
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@@ -2568,8 +2575,8 @@ static void _sde_crtc_frame_data_notify(struct drm_crtc *crtc,
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buf.fd = sde_crtc->frame_data.buf[cur_buf]->fd;
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buf.offset = msm_gem->offset;
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sde_crtc_event_notify(crtc, DRM_EVENT_FRAME_DATA, sizeof(struct sde_drm_frame_data_buf),
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(uint64_t)(&buf));
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sde_crtc_event_notify(crtc, DRM_EVENT_FRAME_DATA, &buf,
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sizeof(struct sde_drm_frame_data_buf));
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sde_crtc->frame_data.idx = ++sde_crtc->frame_data.idx % sde_crtc->frame_data.cnt;
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}
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@@ -2960,6 +2967,10 @@ void sde_crtc_complete_commit(struct drm_crtc *crtc,
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struct drm_crtc_state *old_state)
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{
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struct sde_crtc *sde_crtc;
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struct sde_splash_display *splash_display = NULL;
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struct sde_kms *sde_kms;
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bool cont_splash_enabled = false;
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int i;
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u32 power_on = 1;
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if (!crtc || !crtc->state) {
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@@ -2970,8 +2981,17 @@ void sde_crtc_complete_commit(struct drm_crtc *crtc,
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sde_crtc = to_sde_crtc(crtc);
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SDE_EVT32_VERBOSE(DRMID(crtc));
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if (crtc->state->active_changed && crtc->state->active)
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sde_crtc_event_notify(crtc, DRM_EVENT_CRTC_POWER, sizeof(u32), power_on);
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sde_kms = _sde_crtc_get_kms(crtc);
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for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
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splash_display = &sde_kms->splash_data.splash_display[i];
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if (splash_display->cont_splash_enabled &&
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crtc == splash_display->encoder->crtc)
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cont_splash_enabled = true;
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}
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if ((crtc->state->active_changed || cont_splash_enabled) && crtc->state->active)
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sde_crtc_event_notify(crtc, DRM_EVENT_CRTC_POWER, &power_on, sizeof(u32));
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sde_core_perf_crtc_update(crtc, 0, false);
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}
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@@ -3713,6 +3733,9 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
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_sde_crtc_setup_is_ppsplit(crtc->state);
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_sde_crtc_setup_lm_bounds(crtc, crtc->state);
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_sde_crtc_clear_all_blend_stages(sde_crtc);
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} else if (sde_crtc->num_mixers && sde_crtc->reinit_crtc_mixers) {
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_sde_crtc_setup_mixers(crtc);
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sde_crtc->reinit_crtc_mixers = false;
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}
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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@@ -3738,13 +3761,12 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
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_sde_crtc_dest_scaler_setup(crtc);
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sde_cp_crtc_apply_noise(crtc, old_state);
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if (crtc->state->mode_changed || sde_kms->perf.catalog->uidle_cfg.dirty) {
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if (crtc->state->mode_changed || sde_kms->perf.catalog->uidle_cfg.dirty)
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sde_core_perf_crtc_update_uidle(crtc, true);
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} else if (!test_bit(SDE_CRTC_DIRTY_UIDLE, &sde_crtc->revalidate_mask) &&
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sde_kms->perf.uidle_enabled)
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sde_core_perf_uidle_setup_ctl(crtc, false);
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test_and_clear_bit(SDE_CRTC_DIRTY_UIDLE, &sde_crtc->revalidate_mask);
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/* update cached_encoder_mask if new conn is added or removed */
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if (crtc->state->connectors_changed)
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sde_crtc->cached_encoder_mask = crtc->state->encoder_mask;
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/*
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* Since CP properties use AXI buffer to program the
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@@ -4434,7 +4456,6 @@ void sde_crtc_reset_sw_state(struct drm_crtc *crtc)
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/* mark other properties which need to be dirty for next update */
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set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, &sde_crtc->revalidate_mask);
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set_bit(SDE_CRTC_DIRTY_UIDLE, &sde_crtc->revalidate_mask);
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if (cstate->num_ds_enabled)
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set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);
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}
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@@ -4479,7 +4500,7 @@ static void sde_crtc_mmrm_cb_notification(struct drm_crtc *crtc)
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kms->perf.clk_name);
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/* notify user space the reduced clk rate */
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sde_crtc_event_notify(crtc, DRM_EVENT_MMRM_CB, sizeof(unsigned long), requested_clk);
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sde_crtc_event_notify(crtc, DRM_EVENT_MMRM_CB, &requested_clk, sizeof(unsigned long));
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SDE_DEBUG("crtc[%d]: MMRM cb notified clk:%d\n",
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crtc->base.id, requested_clk);
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@@ -4553,7 +4574,7 @@ static void sde_crtc_handle_power_event(u32 event_type, void *arg)
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sde_crtc_reset_sw_state(crtc);
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sde_cp_crtc_suspend(crtc);
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power_on = 0;
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sde_crtc_event_notify(crtc, DRM_EVENT_SDE_POWER, sizeof(u32), power_on);
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sde_crtc_event_notify(crtc, DRM_EVENT_SDE_POWER, &power_on, sizeof(u32));
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break;
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case SDE_POWER_EVENT_MMRM_CALLBACK:
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sde_crtc_mmrm_cb_notification(crtc);
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@@ -4716,7 +4737,7 @@ static void sde_crtc_disable(struct drm_crtc *crtc)
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sde_cp_crtc_disable(crtc);
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power_on = 0;
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sde_crtc_event_notify(crtc, DRM_EVENT_CRTC_POWER, sizeof(u32), power_on);
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sde_crtc_event_notify(crtc, DRM_EVENT_CRTC_POWER, &power_on, sizeof(u32));
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mutex_unlock(&sde_crtc->crtc_lock);
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}
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@@ -4738,11 +4759,18 @@ static void sde_crtc_enable(struct drm_crtc *crtc,
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struct sde_crtc_state *cstate;
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struct msm_display_mode *msm_mode;
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enum sde_intf_mode intf_mode;
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struct sde_kms *kms;
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if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
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SDE_ERROR("invalid crtc\n");
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return;
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}
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kms = _sde_crtc_get_kms(crtc);
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if (!kms || !kms->catalog) {
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SDE_ERROR("invalid kms handle\n");
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return;
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}
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priv = crtc->dev->dev_private;
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cstate = to_sde_crtc_state(crtc->state);
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@@ -4767,7 +4795,8 @@ static void sde_crtc_enable(struct drm_crtc *crtc,
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intf_mode = sde_crtc_get_intf_mode(crtc, crtc->state);
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if ((intf_mode != INTF_MODE_WB_BLOCK) && (intf_mode != INTF_MODE_WB_LINE)) {
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/* max possible vsync_cnt(atomic_t) soft counter */
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drm_crtc_set_max_vblank_count(crtc, INT_MAX);
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if (kms->catalog->has_precise_vsync_ts)
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drm_crtc_set_max_vblank_count(crtc, INT_MAX);
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drm_crtc_vblank_on(crtc);
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}
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}
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@@ -5662,6 +5691,8 @@ static u32 sde_crtc_get_vblank_counter(struct drm_crtc *crtc)
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{
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struct drm_encoder *encoder;
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struct sde_crtc *sde_crtc;
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bool is_built_in;
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u32 vblank_cnt;
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if (!crtc)
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return 0;
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@@ -5672,7 +5703,14 @@ static u32 sde_crtc_get_vblank_counter(struct drm_crtc *crtc)
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if (sde_encoder_in_clone_mode(encoder))
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continue;
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return sde_encoder_get_frame_count(encoder);
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is_built_in = sde_encoder_is_built_in_display(encoder);
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vblank_cnt = sde_encoder_get_frame_count(encoder);
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SDE_EVT32(DRMID(crtc), DRMID(encoder), is_built_in, vblank_cnt);
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SDE_DEBUG("crtc:%d enc:%d is_built_in:%d vblank_cnt:%d\n",
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DRMID(crtc), DRMID(encoder), is_built_in, vblank_cnt);
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return vblank_cnt;
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}
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return 0;
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@@ -5954,7 +5992,7 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
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return;
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}
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info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
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info = vzalloc(sizeof(struct sde_kms_info));
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if (!info) {
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SDE_ERROR("failed to allocate info memory\n");
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return;
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@@ -6058,7 +6096,7 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
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msm_property_install_range(&sde_crtc->property_info, "frame_data",
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0x0, 0, ~0, 0, CRTC_PROP_FRAME_DATA_BUF);
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kfree(info);
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vfree(info);
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}
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static int _sde_crtc_get_output_fence(struct drm_crtc *crtc,
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@@ -7610,6 +7648,13 @@ static int sde_crtc_vm_release_handler(struct drm_crtc *crtc_drm,
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{
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return 0;
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}
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static int sde_crtc_frame_data_interrupt_handler(struct drm_crtc *crtc_drm,
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bool en, struct sde_irq_callback *irq)
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{
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return 0;
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}
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/**
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* sde_crtc_update_cont_splash_settings - update mixer settings
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* and initial clk during device bootup for cont_splash use case
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@@ -7769,5 +7814,7 @@ void sde_crtc_disable_cp_features(struct drm_crtc *crtc)
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void _sde_crtc_vm_release_notify(struct drm_crtc *crtc)
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{
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sde_crtc_event_notify(crtc, DRM_EVENT_VM_RELEASE, sizeof(uint32_t), 1);
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uint32_t val = 1;
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sde_crtc_event_notify(crtc, DRM_EVENT_VM_RELEASE, &val, sizeof(uint32_t));
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}
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