Merge remote-tracking branch 'quic/display-kernel.lnx.5.10' into display-kernel.lnx.5.15

* quic/display-kernel.lnx.5.10:
  disp: msm: sde: avoid error during fal10_veto override enablement
  disp: msm: update copyright description
  disp: msm: sde: configure dest_scaler op_mode for two independent displays
  disp: msm: dp: updated copyright set for 4nm target
  Revert "disp: msm: sde: consider max of actual and default prefill lines"
  disp: msm: sde: Reset backlight scale when HWC is stopped
  disp: msm: dp: avoid duplicate read of link status
  disp: msm: dsi: update vreg_ctrl settings for cape
  disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
  disp: msm: dp: updated register values for 4nm target
  disp: msm: sde: update framedata event handling
  disp: msm: dsi: Add new phy comaptible string for cape
  disp: msm: sde: software override for fal10 in cwb enable
  disp: msm: update cleanup during bind failure in msm_drm_component_init
  disp: msm: sde: dump user input_fence info on spec fence timeout
  disp: msm: sde: add null pointer check for encoder current master
  disp: msm: dsi: enable DMA start window scheduling for broadcast commands
  disp: msm: sde: avoid alignment checks for linear formats
  disp: msm: reset thread priority work on every new run
  disp: msm: sde: send power on event for cont. splash
  disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
  disp: msm: use vzalloc for large allocations
  disp: msm: sde: Add support to limit DSC size to 10k
  disp: msm: sde: add tx wait during DMS for sim panel
  disp: msm: dsi: add check for any queued DSI CMDs before clock force update
  disp: msm: sde: correct pp block allocation during dcwb dither programming
  disp: msm: sde: avoid setting of max vblank count
  disp: msm: sde: add cached lut flag in sde plane
  disp: msm: sde: avoid use after free in msm_lastclose
  disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
  disp: msm: dsi: Support uncompressed rgb101010 format
  disp: msm: sde: update idle_pc_enabled flag for all encoders
  disp: msm: sde: flush esd work before disabling the encoder
  disp: msm: sde: allow qsync update along with modeset
  disp: msm: dp: avoid dp sw reset on disconnect path
  disp: msm: sde: consider max of actual and default prefill lines
  disp: msm: ensure vbif debugbus not in use is disabled
  disp: msm: sde: update cached encoder mask if required
  disp: msm: sde: while timing engine enabling poll for active region
  disp: msm: enable cache flag for dumb buffer
  disp: msm: sde: disable ot limit for cwb
  disp: msm: sde: avoid race condition at vm release
  disp: msm: dsi: set qsync min fps list length to zero
  disp: msm: sde: reset mixers in crtc when ctl datapath switches
  disp: msm: sde: update vm state atomic check for non-primary usecases
  disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled

Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
这个提交包含在:
Narendra Muppalla
2022-02-07 10:52:13 -08:00
当前提交 daa511cb90
修改 39 个文件,包含 558 行新增176 行删除

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@@ -519,8 +519,10 @@ static int msm_drm_uninit(struct device *dev)
drm_irq_uninstall(ddev);
#endif
if (kms && kms->funcs)
if (kms && kms->funcs) {
kms->funcs->destroy(kms);
priv->kms = NULL;
}
if (priv->vram.paddr) {
unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
@@ -687,7 +689,6 @@ static int msm_drm_display_thread_create(struct msm_drm_private *priv, struct dr
{
int i, ret = 0;
kthread_init_work(&priv->thread_priority_work, msm_drm_display_thread_priority_worker);
for (i = 0; i < priv->num_crtcs; i++) {
/* initialize display thread */
priv->disp_thread[i].crtc_id = priv->crtcs[i]->base.id;
@@ -697,7 +698,10 @@ static int msm_drm_display_thread_create(struct msm_drm_private *priv, struct dr
kthread_run(kthread_worker_fn,
&priv->disp_thread[i].worker,
"crtc_commit:%d", priv->disp_thread[i].crtc_id);
kthread_init_work(&priv->thread_priority_work,
msm_drm_display_thread_priority_worker);
kthread_queue_work(&priv->disp_thread[i].worker, &priv->thread_priority_work);
kthread_flush_work(&priv->thread_priority_work);
if (IS_ERR(priv->disp_thread[i].thread)) {
dev_err(dev, "failed to create crtc_commit kthread\n");
@@ -719,7 +723,10 @@ static int msm_drm_display_thread_create(struct msm_drm_private *priv, struct dr
* frame_pending counters beyond 2. This can lead to commit
* failure at crtc commit level.
*/
kthread_init_work(&priv->thread_priority_work,
msm_drm_display_thread_priority_worker);
kthread_queue_work(&priv->event_thread[i].worker, &priv->thread_priority_work);
kthread_flush_work(&priv->thread_priority_work);
if (IS_ERR(priv->event_thread[i].thread)) {
dev_err(dev, "failed to create crtc_event kthread\n");
@@ -754,7 +761,9 @@ static int msm_drm_display_thread_create(struct msm_drm_private *priv, struct dr
kthread_init_worker(&priv->pp_event_worker);
priv->pp_event_thread = kthread_run(kthread_worker_fn,
&priv->pp_event_worker, "pp_event");
kthread_init_work(&priv->thread_priority_work, msm_drm_display_thread_priority_worker);
kthread_queue_work(&priv->pp_event_worker, &priv->thread_priority_work);
kthread_flush_work(&priv->thread_priority_work);
if (IS_ERR(priv->pp_event_thread)) {
dev_err(dev, "failed to create pp_event kthread\n");
@@ -908,8 +917,12 @@ static int msm_drm_component_init(struct device *dev)
/* Bind all our sub-components: */
ret = msm_component_bind_all(dev, ddev);
if (ret)
if (ret == -EPROBE_DEFER) {
destroy_workqueue(priv->wq);
return ret;
} else if (ret) {
goto bind_fail;
}
ret = msm_init_vram(ddev);
if (ret)
@@ -1104,12 +1117,14 @@ static void msm_postclose(struct drm_device *dev, struct drm_file *file)
static void msm_lastclose(struct drm_device *dev)
{
struct msm_drm_private *priv = dev->dev_private;
struct msm_kms *kms = priv->kms;
struct msm_kms *kms;
int i, rc;
if (!kms)
if (!priv || !priv->kms)
return;
kms = priv->kms;
/* check for splash status before triggering cleanup
* if we end up here with splash status ON i.e before first
* commit then ignore the last close call