msm: camera: cdm: Add support for different CDM hardware
Different CDM hardware have different capability and registers. With old register space, handling new features and operations would have been a complex task. This change takes care of old version of CDM and also changes the regspace to provide every register's access to CDM. This change further adds support for "arbitration" in case of multi-context CDMs. Exports reset functionality to clients, detection of CDM hang. Flushing the CDM requests and dumping the FIFO content for all contexts. It also adds submitting "debug_gen_irq" as BL_done IRQ is only an indication for availability of FIFO's. The AHB operations are completed can only be known if the added "debug_gen_irqs" gets executed and are received by the CDM. CRs-Fixed: 2594541 Change-Id: I9846b1c5320ba652c5d3b7d83d616d2dabc843e1 Signed-off-by: Abhilash Kumar <krabhi@codeaurora.org> Signed-off-by: Trishansh Bhardwaj <tbhardwa@codeaurora.org>
这个提交包含在：
Trishansh Bhardwaj
@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/delay.h>
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@@ -15,45 +15,35 @@
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#include "cam_cdm.h"
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#include "cam_soc_util.h"
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#include "cam_io_util.h"
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#include "cam_cdm_soc.h"
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#define CAM_CDM_OFFSET_FROM_REG(x, y) ((x)->offsets[y].offset)
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#define CAM_CDM_ATTR_FROM_REG(x, y) ((x)->offsets[y].attribute)
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bool cam_cdm_read_hw_reg(struct cam_hw_info *cdm_hw,
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enum cam_cdm_regs reg, uint32_t *value)
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uint32_t reg, uint32_t *value)
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{
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void __iomem *reg_addr;
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struct cam_cdm *cdm = (struct cam_cdm *)cdm_hw->core_info;
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void __iomem *base =
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cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].mem_base;
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resource_size_t mem_len =
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cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].size;
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CAM_DBG(CAM_CDM, "E: b=%pK blen=%d reg=%x off=%x", (void __iomem *)base,
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(int)mem_len, reg, (CAM_CDM_OFFSET_FROM_REG(cdm->offset_tbl,
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reg)));
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CAM_DBG(CAM_CDM, "E: b=%pK reg=%x off=%x", (void __iomem *)base,
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reg, (CAM_CDM_OFFSET_FROM_REG(cdm->offset_tbl, reg)));
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CAM_DBG(CAM_CDM, "E: b=%pK blen=%d off=%x", (void __iomem *)base,
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(int)mem_len, reg);
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if ((reg > cdm->offset_tbl->offset_max_size) ||
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(reg > cdm->offset_tbl->last_offset)) {
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CAM_ERR_RATE_LIMIT(CAM_CDM, "Invalid reg=%d\n", reg);
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reg_addr = (base + reg);
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if (reg_addr > (base + mem_len)) {
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CAM_ERR_RATE_LIMIT(CAM_CDM,
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"Invalid mapped region %d", reg);
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goto permission_error;
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} else {
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reg_addr = (base + (CAM_CDM_OFFSET_FROM_REG(
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cdm->offset_tbl, reg)));
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if (reg_addr > (base + mem_len)) {
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CAM_ERR_RATE_LIMIT(CAM_CDM,
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"Invalid mapped region %d", reg);
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goto permission_error;
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}
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*value = cam_io_r_mb(reg_addr);
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CAM_DBG(CAM_CDM, "X b=%pK reg=%x off=%x val=%x",
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(void __iomem *)base, reg,
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(CAM_CDM_OFFSET_FROM_REG(cdm->offset_tbl, reg)),
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*value);
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return false;
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}
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*value = cam_io_r_mb(reg_addr);
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CAM_DBG(CAM_CDM, "X b=%pK off=%x val=%x",
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(void __iomem *)base, reg,
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*value);
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return false;
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permission_error:
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*value = 0;
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return true;
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@@ -61,36 +51,27 @@ permission_error:
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}
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bool cam_cdm_write_hw_reg(struct cam_hw_info *cdm_hw,
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enum cam_cdm_regs reg, uint32_t value)
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uint32_t reg, uint32_t value)
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{
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void __iomem *reg_addr;
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struct cam_cdm *cdm = (struct cam_cdm *)cdm_hw->core_info;
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void __iomem *base =
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cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].mem_base;
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resource_size_t mem_len =
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cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].size;
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CAM_DBG(CAM_CDM, "E: b=%pK reg=%x off=%x val=%x", (void __iomem *)base,
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reg, (CAM_CDM_OFFSET_FROM_REG(cdm->offset_tbl, reg)), value);
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CAM_DBG(CAM_CDM, "E: b=%pK off=%x val=%x", (void __iomem *)base,
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reg, value);
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if ((reg > cdm->offset_tbl->offset_max_size) ||
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(reg > cdm->offset_tbl->last_offset)) {
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CAM_ERR_RATE_LIMIT(CAM_CDM, "CDM accessing invalid reg=%d\n",
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reg_addr = (base + reg);
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if (reg_addr > (base + mem_len)) {
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CAM_ERR_RATE_LIMIT(CAM_CDM,
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"Accessing invalid region:%d\n",
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reg);
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goto permission_error;
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} else {
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reg_addr = (base + CAM_CDM_OFFSET_FROM_REG(
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cdm->offset_tbl, reg));
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if (reg_addr > (base + mem_len)) {
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CAM_ERR_RATE_LIMIT(CAM_CDM,
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"Accessing invalid region %d:%d\n",
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reg, (CAM_CDM_OFFSET_FROM_REG(
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cdm->offset_tbl, reg)));
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goto permission_error;
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}
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cam_io_w_mb(value, reg_addr);
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return false;
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}
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cam_io_w_mb(value, reg_addr);
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return false;
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permission_error:
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return true;
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@@ -99,7 +80,7 @@ permission_error:
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int cam_cdm_soc_load_dt_private(struct platform_device *pdev,
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struct cam_cdm_private_dt_data *ptr)
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{
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int i, rc = -EINVAL;
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int i, rc = -EINVAL, num_fifo_entries = 0;
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ptr->dt_num_supported_clients = of_property_count_strings(
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pdev->dev.of_node,
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@@ -111,7 +92,7 @@ int cam_cdm_soc_load_dt_private(struct platform_device *pdev,
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CAM_ERR(CAM_CDM, "Invalid count of client names count=%d",
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ptr->dt_num_supported_clients);
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rc = -EINVAL;
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return rc;
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goto end;
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}
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if (ptr->dt_num_supported_clients < 0) {
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CAM_DBG(CAM_CDM, "No cdm client names found");
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@@ -127,10 +108,43 @@ int cam_cdm_soc_load_dt_private(struct platform_device *pdev,
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ptr->dt_cdm_client_name[i]);
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if (rc < 0) {
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CAM_ERR(CAM_CDM, "Reading cdm-client-names failed");
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break;
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goto end;
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}
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}
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ptr->config_fifo = of_property_read_bool(pdev->dev.of_node,
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"config-fifo");
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if (ptr->config_fifo) {
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num_fifo_entries = of_property_count_u32_elems(
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pdev->dev.of_node,
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"fifo-depths");
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if (num_fifo_entries != CAM_CDM_NUM_BL_FIFO) {
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CAM_ERR(CAM_CDM,
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"Wrong number of configurable FIFOs %d",
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num_fifo_entries);
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rc = -EINVAL;
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goto end;
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}
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for (i = 0; i < num_fifo_entries; i++) {
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rc = of_property_read_u32_index(pdev->dev.of_node,
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"fifo-depths", i, &ptr->fifo_depth[i]);
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if (rc < 0) {
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CAM_ERR(CAM_CDM,
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"Unable to read fifo-depth rc %d",
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rc);
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goto end;
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}
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CAM_DBG(CAM_CDM, "FIFO%d depth is %d",
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i, ptr->fifo_depth[i]);
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}
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} else {
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for (i = 0; i < CAM_CDM_BL_FIFO_MAX; i++) {
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ptr->fifo_depth[i] = CAM_CDM_BL_FIFO_LENGTH_MAX_DEFAULT;
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CAM_DBG(CAM_CDM, "FIFO%d depth is %d",
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i, ptr->fifo_depth[i]);
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}
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}
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end:
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return rc;
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}
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@@ -140,6 +154,7 @@ int cam_hw_cdm_soc_get_dt_properties(struct cam_hw_info *cdm_hw,
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int rc;
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struct cam_hw_soc_info *soc_ptr;
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const struct of_device_id *id;
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struct cam_cdm *cdm_core = cdm_hw->core_info;
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if (!cdm_hw || (cdm_hw->soc_info.soc_private)
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|| !(cdm_hw->soc_info.pdev))
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@@ -150,38 +165,44 @@ int cam_hw_cdm_soc_get_dt_properties(struct cam_hw_info *cdm_hw,
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rc = cam_soc_util_get_dt_properties(soc_ptr);
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if (rc != 0) {
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CAM_ERR(CAM_CDM, "Failed to retrieve the CDM dt properties");
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} else {
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soc_ptr->soc_private = kzalloc(
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sizeof(struct cam_cdm_private_dt_data),
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GFP_KERNEL);
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if (!soc_ptr->soc_private)
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return -ENOMEM;
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rc = cam_cdm_soc_load_dt_private(soc_ptr->pdev,
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soc_ptr->soc_private);
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if (rc != 0) {
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CAM_ERR(CAM_CDM, "Failed to load CDM dt private data");
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goto error;
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}
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id = of_match_node(table, soc_ptr->pdev->dev.of_node);
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if ((!id) || !(id->data)) {
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CAM_ERR(CAM_CDM, "Failed to retrieve the CDM id table");
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goto error;
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}
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CAM_DBG(CAM_CDM, "CDM Hw Id compatible =%s", id->compatible);
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((struct cam_cdm *)cdm_hw->core_info)->offset_tbl =
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(struct cam_cdm_reg_offset_table *)id->data;
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strlcpy(((struct cam_cdm *)cdm_hw->core_info)->name,
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id->compatible,
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sizeof(((struct cam_cdm *)cdm_hw->core_info)->name));
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goto end;
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}
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return rc;
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soc_ptr->soc_private = kzalloc(
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sizeof(struct cam_cdm_private_dt_data),
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GFP_KERNEL);
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if (!soc_ptr->soc_private)
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return -ENOMEM;
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rc = cam_cdm_soc_load_dt_private(soc_ptr->pdev,
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soc_ptr->soc_private);
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if (rc != 0) {
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CAM_ERR(CAM_CDM, "Failed to load CDM dt private data");
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goto error;
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}
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id = of_match_node(table, soc_ptr->pdev->dev.of_node);
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if ((!id) || !(id->data)) {
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CAM_ERR(CAM_CDM, "Failed to retrieve the CDM id table");
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goto error;
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}
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cdm_core->offsets =
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(struct cam_cdm_hw_reg_offset *)id->data;
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CAM_DBG(CAM_CDM, "name %s", cdm_core->name);
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snprintf(cdm_core->name, sizeof(cdm_core->name) + 1, "%s%d",
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id->compatible, soc_ptr->index);
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CAM_DBG(CAM_CDM, "name %s", cdm_core->name);
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goto end;
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error:
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rc = -EINVAL;
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kfree(soc_ptr->soc_private);
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soc_ptr->soc_private = NULL;
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end:
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return rc;
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}
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