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disp: msm: sde: clear wb mode and cached cwb encoder mask

The issue scenario is as follows
1. A CWB commit has run and it has disabled. Composer kill is
   done.
2. If Composer starts again or another client has open DRM
   the previous cwb state is intact.
3. When userspace is trying to query wb modes, primary modes
   which are attached to wb as part of cwb commit is exposed.

This leads to commit failures if userspace is trying to trigger wb
on the same CRTC of what primary has run cwb before. This change
properly clears wb mode and the cached encoder mask to avoid commit
failures.

Change-Id: I4ca8bd2b52a980630b7fb1319bf67b718ebb2ac2
Signed-off-by: Mahadevan <[email protected]>
Mahadevan 2 年之前
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d8db76b3ff
共有 2 個文件被更改,包括 7 次插入2 次删除
  1. 2 1
      msm/sde/sde_crtc.c
  2. 5 1
      msm/sde/sde_encoder_phys_wb.c

+ 2 - 1
msm/sde/sde_crtc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
  * Copyright (C) 2013 Red Hat
  * Author: Rob Clark <[email protected]>
@@ -5373,6 +5373,7 @@ static void sde_crtc_disable(struct drm_crtc *crtc)
 			crtc->state->enable, sde_crtc->cached_encoder_mask);
 	sde_crtc->enabled = false;
 	sde_crtc->cached_encoder_mask = 0;
+	cstate->cached_cwb_enc_mask = 0;
 
 	/* Try to disable uidle */
 	sde_core_perf_crtc_update_uidle(crtc, false);

+ 5 - 1
msm/sde/sde_encoder_phys_wb.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -2073,6 +2073,7 @@ static void _sde_encoder_phys_wb_reset_state(struct sde_encoder_phys *phys_enc)
 {
 	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);
 	struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(phys_enc->parent);
+	struct sde_wb_device *wb_dev = wb_enc->wb_dev;
 	struct sde_crtc *sde_crtc;
 
 	phys_enc->enable_state = SDE_ENC_DISABLED;
@@ -2093,6 +2094,9 @@ static void _sde_encoder_phys_wb_reset_state(struct sde_encoder_phys *phys_enc)
 	phys_enc->hw_cdm = NULL;
 	phys_enc->hw_ctl = NULL;
 	phys_enc->in_clone_mode = false;
+	kfree(wb_dev->modes);
+	wb_dev->modes = NULL;
+	wb_dev->count_modes = 0;
 	atomic_set(&phys_enc->pending_kickoff_cnt, 0);
 	atomic_set(&phys_enc->pending_retire_fence_cnt, 0);
 	atomic_set(&phys_enc->pending_ctl_start_cnt, 0);