samsung-sm8650/android_kernel_samsung_sm8650-modules
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msm: camera: cci: Increase queue size for burst write mode

Bläddra i källkod 
Currently for i2c burst write half the depth of the queue
is utilized which can cause delay in the overall operation
when data size is large that needs to be operated.
Also currently execute command is being programmed after
every 4 bytes/1 word. CCI hw can execute 12 bytes/3 words
together, so align the execute word with 12bytes/3 words
to reduce the processing for CCI hw and better performance.

CRs-Fixed: 2856297
Change-Id: I77e3ae8f6454037a7a100ae6b911ac37e19aa8b7
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
This commit is contained in:
Jigarkumar Zala
2020-11-08 11:20:04 -08:00
förälder e7f96de4c3
incheckning d82b260384
2 ändrade filer med 18 tillägg och 8 borttagningar
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22
drivers/cam_sensor_module/cam_cci/cam_cci_core.c
Visa fil

@@ -427,9 +427,12 @@ static void cam_cci_process_half_q(struct cci_device *cci_dev,
void __iomem *base = soc_info->reg_map[0].mem_base; void __iomem *base = soc_info->reg_map[0].mem_base;
uint32_t reg_val = 1 << ((master * 2) + queue); uint32_t reg_val = 1 << ((master * 2) + queue);
CAM_DBG(CAM_CCI, "ENTER");
spin_lock_irqsave(&cci_dev->cci_master_info[master].lock_q[queue], spin_lock_irqsave(&cci_dev->cci_master_info[master].lock_q[queue],
flags); flags);
if (atomic_read(&cci_dev->cci_master_info[master].q_free[queue]) == 0) { if (atomic_read(&cci_dev->cci_master_info[master].q_free[queue]) == 0) {
CAM_DBG(CAM_CCI, "queue: %d is free", queue);
cam_cci_load_report_cmd(cci_dev, master, queue); cam_cci_load_report_cmd(cci_dev, master, queue);
atomic_set(&cci_dev->cci_master_info[master].q_free[queue], 1); atomic_set(&cci_dev->cci_master_info[master].q_free[queue], 1);
cam_io_w_mb(reg_val, base + cam_io_w_mb(reg_val, base +
@@ -446,7 +449,7 @@ static int32_t cam_cci_process_full_q(struct cci_device *cci_dev,
int32_t rc = 0; int32_t rc = 0;
unsigned long flags; unsigned long flags;
CAM_DBG(CAM_CCI, "ENTER");
spin_lock_irqsave(&cci_dev->cci_master_info[master].lock_q[queue], spin_lock_irqsave(&cci_dev->cci_master_info[master].lock_q[queue],
flags); flags);
if (atomic_read(&cci_dev->cci_master_info[master].q_free[queue]) == 1) { if (atomic_read(&cci_dev->cci_master_info[master].q_free[queue]) == 1) {
@@ -455,6 +458,7 @@ static int32_t cam_cci_process_full_q(struct cci_device *cci_dev,
1); 1);
spin_unlock_irqrestore( spin_unlock_irqrestore(
&cci_dev->cci_master_info[master].lock_q[queue], flags); &cci_dev->cci_master_info[master].lock_q[queue], flags);
CAM_DBG(CAM_CCI, "Queue: %d is set to 1", queue);
rc = cam_cci_wait(cci_dev, master, queue); rc = cam_cci_wait(cci_dev, master, queue);
if (rc < 0) { if (rc < 0) {
CAM_ERR(CAM_CCI, CAM_ERR(CAM_CCI,
@@ -465,6 +469,7 @@ static int32_t cam_cci_process_full_q(struct cci_device *cci_dev,
} else { } else {
spin_unlock_irqrestore( spin_unlock_irqrestore(
&cci_dev->cci_master_info[master].lock_q[queue], flags); &cci_dev->cci_master_info[master].lock_q[queue], flags);
CAM_DBG(CAM_CCI, "Queue: %d is set to 0", queue);
rc = cam_cci_wait_report_cmd(cci_dev, master, queue); rc = cam_cci_wait_report_cmd(cci_dev, master, queue);
if (rc < 0) { if (rc < 0) {
CAM_ERR(CAM_CCI, CAM_ERR(CAM_CCI,
@@ -474,6 +479,8 @@ static int32_t cam_cci_process_full_q(struct cci_device *cci_dev,
} }
} }
CAM_DBG(CAM_CCI, "EXIT");
return rc; return rc;
} }
@@ -751,10 +758,11 @@ static int32_t cam_cci_data_queue(struct cci_device *cci_dev,
max_queue_size = max_queue_size =
cci_dev->cci_i2c_queue_info[master][queue].max_queue_size; cci_dev->cci_i2c_queue_info[master][queue].max_queue_size;
if (c_ctrl->cmd == MSM_CCI_I2C_WRITE_SEQ) if ((c_ctrl->cmd == MSM_CCI_I2C_WRITE_SEQ) ||
(c_ctrl->cmd == MSM_CCI_I2C_WRITE_BURST))
queue_size = max_queue_size; queue_size = max_queue_size;
else else
queue_size = max_queue_size/2; queue_size = max_queue_size / 2;
reg_addr = i2c_cmd->reg_addr; reg_addr = i2c_cmd->reg_addr;
if (sync_en == MSM_SYNC_ENABLE && cci_dev->valid_sync && if (sync_en == MSM_SYNC_ENABLE && cci_dev->valid_sync &&
@@ -781,7 +789,7 @@ static int32_t cam_cci_data_queue(struct cci_device *cci_dev,
i2c_cmd, &pack); i2c_cmd, &pack);
if (len <= 0) { if (len <= 0) {
CAM_ERR(CAM_CCI, CAM_ERR(CAM_CCI,
"Calculate comamnd len failed, len:%d", len); "Calculate command len failed, len:%d", len);
return -EINVAL; return -EINVAL;
} }
@@ -906,10 +914,12 @@ static int32_t cam_cci_data_queue(struct cci_device *cci_dev,
master * 0x200 + queue * 0x100); master * 0x200 + queue * 0x100);
read_val += 1; read_val += 1;
cam_io_w_mb(read_val, base +
CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR + reg_offset);
} }
cam_io_w_mb(read_val, base +
CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR + reg_offset);
if ((delay > 0) && (delay < CCI_MAX_DELAY) && if ((delay > 0) && (delay < CCI_MAX_DELAY) &&
en_seq_write == 0) { en_seq_write == 0) {
cmd = (uint32_t)((delay * cci_dev->cycles_per_us) / cmd = (uint32_t)((delay * cci_dev->cycles_per_us) /

4
drivers/cam_sensor_module/cam_cci/cam_cci_dev.c
Visa fil

@@ -73,8 +73,8 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
irq_status0 = cam_io_r_mb(base + CCI_IRQ_STATUS_0_ADDR); irq_status0 = cam_io_r_mb(base + CCI_IRQ_STATUS_0_ADDR);
irq_status1 = cam_io_r_mb(base + CCI_IRQ_STATUS_1_ADDR); irq_status1 = cam_io_r_mb(base + CCI_IRQ_STATUS_1_ADDR);
CAM_DBG(CAM_CCI, CAM_INFO(CAM_CCI,
"BASE: %pK, irq0:%x irq1:%x", "BASE: %p, irq0:%x irq1:%x",
base, irq_status0, irq_status1); base, irq_status0, irq_status1);
if (irq_status0 & CCI_IRQ_STATUS_0_RST_DONE_ACK_BMSK) { if (irq_status0 & CCI_IRQ_STATUS_0_RST_DONE_ACK_BMSK) {