fw-api: Add HW header files for WCN6450

Add the HW header files for WCN6450 and cleanup the header files,
1. Remove comments.
2. Add appropriate copyright header.
3. Remove references to HW sensitive IP (structs, macros and etc).

Change-Id: I9c80242a8b9fb4937685174d8892997e3e632982
CRs-Fixed: 3417793

hw/wcn6450/v1/HALcomdef.h

@@ -0,0 +1,53 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef HAL_COMDEF_H
+#define HAL_COMDEF_H
+
+#ifndef _ARM_ASM_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "com_dtypes.h"
+
+#ifndef _BOOL32_DEFINED
+typedef  unsigned long int  bool32;
+#define _BOOL32_DEFINED
+#endif
+
+#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
+
+  #define inp(port)         (*((volatile byte *) (port)))
+  #define inpw(port)        (*((volatile word *) (port)))
+  #define inpdw(port)       (*((volatile dword *)(port)))
+
+  #define outp(port, val)   (*((volatile byte *) (port)) = ((byte) (val)))
+  #define outpw(port, val)  (*((volatile word *) (port)) = ((word) (val)))
+  #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+

hw/wcn6450/v1/HALhwio.h

@@ -0,0 +1,424 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef HAL_HWIO_H
+#define HAL_HWIO_H
+
+#include "HALcomdef.h"
+
+#define SEQ_WCSS_WCMN_OFFSET     SEQ_WCSS_TOP_CMN_OFFSET
+#define SEQ_WCSS_PMM_OFFSET      SEQ_WCSS_PMM_TOP_OFFSET
+
+#define HWIO_BASE_PTR(base) base##_BASE_PTR
+
+#ifdef __ARMCC_VERSION
+  #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
+#else
+  #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
+#endif
+
+#define HWIO_ADDR(hwiosym)                               __msmhwio_addr(hwiosym)
+#define HWIO_ADDRI(hwiosym, index)                       __msmhwio_addri(hwiosym, index)
+#define HWIO_ADDRI2(hwiosym, index1, index2)             __msmhwio_addri2(hwiosym, index1, index2)
+#define HWIO_ADDRI3(hwiosym, index1, index2, index3)     __msmhwio_addri3(hwiosym, index1, index2, index3)
+
+#define HWIO_ADDRX(base, hwiosym)                           __msmhwio_addrx(base, hwiosym)
+#define HWIO_ADDRXI(base, hwiosym, index)                   __msmhwio_addrxi(base, hwiosym, index)
+#define HWIO_ADDRXI2(base, hwiosym, index1, index2)         __msmhwio_addrxi2(base, hwiosym, index1, index2)
+#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_PHYS(hwiosym)                               __msmhwio_phys(hwiosym)
+#define HWIO_PHYSI(hwiosym, index)                       __msmhwio_physi(hwiosym, index)
+#define HWIO_PHYSI2(hwiosym, index1, index2)             __msmhwio_physi2(hwiosym, index1, index2)
+#define HWIO_PHYSI3(hwiosym, index1, index2, index3)     __msmhwio_physi3(hwiosym, index1, index2, index3)
+
+#define HWIO_PHYSX(base, hwiosym)                           __msmhwio_physx(base, hwiosym)
+#define HWIO_PHYSXI(base, hwiosym, index)                   __msmhwio_physxi(base, hwiosym, index)
+#define HWIO_PHYSXI2(base, hwiosym, index1, index2)         __msmhwio_physxi2(base, hwiosym, index1, index2)
+#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_OFFS(hwiosym)                               __msmhwio_offs(hwiosym)
+#define HWIO_OFFSI(hwiosym, index)                       __msmhwio_offsi(hwiosym, index)
+#define HWIO_OFFSI2(hwiosym, index1, index2)             __msmhwio_offsi2(hwiosym, index1, index2)
+#define HWIO_OFFSI3(hwiosym, index1, index2, index3)     __msmhwio_offsi3(hwiosym, index1, index2, index3)
+
+#define HWIO_IN(hwiosym)                                         __msmhwio_in(hwiosym)
+#define HWIO_INI(hwiosym, index)                                 __msmhwio_ini(hwiosym, index)
+#define HWIO_INI2(hwiosym, index1, index2)                       __msmhwio_ini2(hwiosym, index1, index2)
+#define HWIO_INI3(hwiosym, index1, index2, index3)               __msmhwio_ini3(hwiosym, index1, index2, index3)
+
+#define HWIO_INM(hwiosym, mask)                                  __msmhwio_inm(hwiosym, mask)
+#define HWIO_INMI(hwiosym, index, mask)                          __msmhwio_inmi(hwiosym, index, mask)
+#define HWIO_INMI2(hwiosym, index1, index2, mask)                __msmhwio_inmi2(hwiosym, index1, index2, mask)
+#define HWIO_INMI3(hwiosym, index1, index2, index3, mask)        __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INF(io, field)                                      (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI(io, index, field)                              (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI2(io, index1, index2, field)                    (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI3(io, index1, index2, index3, field)            (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_INX(base, hwiosym)                                  __msmhwio_inx(base, hwiosym)
+#define HWIO_INXI(base, hwiosym, index)                          __msmhwio_inxi(base, hwiosym, index)
+#define HWIO_INXI2(base, hwiosym, index1, index2)                __msmhwio_inxi2(base, hwiosym, index1, index2)
+#define HWIO_INXI3(base, hwiosym, index1, index2, index3)        __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_INXM(base, hwiosym, mask)                           __msmhwio_inxm(base, hwiosym, mask)
+#define HWIO_INXMI(base, hwiosym, index, mask)                   __msmhwio_inxmi(base, hwiosym, index, mask)
+#define HWIO_INXMI2(base, hwiosym, index1, index2, mask)         __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
+#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INXF(base, io, field)                               (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI(base, io, index, field)                       (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI2(base, io, index1, index2, field)             (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI3(base, io, index1, index2, index3, field)     (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_OUT(hwiosym, val)                                   __msmhwio_out(hwiosym, val)
+#define HWIO_OUTI(hwiosym, index, val)                           __msmhwio_outi(hwiosym, index, val)
+#define HWIO_OUTI2(hwiosym, index1, index2, val)                 __msmhwio_outi2(hwiosym, index1, index2, val)
+#define HWIO_OUTI3(hwiosym, index1, index2, index3, val)         __msmhwio_outi3(hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTM(hwiosym, mask, val)                            __msmhwio_outm(hwiosym, mask, val)
+#define HWIO_OUTMI(hwiosym, index, mask, val)                    __msmhwio_outmi(hwiosym, index, mask, val)
+#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val)          __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
+#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val)  __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTF(io, field, val)                                HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI(io, index, field, val)                        HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI2(io, index1, index2, field, val)              HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI3(io, index1, index2, index3, field, val)      HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTV(io, field, val)                                HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI(io, index, field, val)                        HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI2(io, index1, index2, field, val)              HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI3(io, index1, index2, index3, field, val)      HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTX(base, hwiosym, val)                                   __msmhwio_outx(base, hwiosym, val)
+#define HWIO_OUTXI(base, hwiosym, index, val)                           __msmhwio_outxi(base, hwiosym, index, val)
+#define HWIO_OUTXI2(base, hwiosym, index1, index2, val)                 __msmhwio_outxi2(base, hwiosym, index1, index2, val)
+#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val)         __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTXM(base, hwiosym, mask, val)                            __msmhwio_outxm(base, hwiosym, mask, val)
+#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2)  __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
+#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
+#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
+#define HWIO_OUTXMI(base, hwiosym, index, mask, val)                    __msmhwio_outxmi(base, hwiosym, index, mask, val)
+#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val)          __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
+#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val)  __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OPT_OUTM2(hwiosym, mask1, mask2, val1, val2)       { \
+                       A_UINT32 reg; \
+                       reg = HWIO_IN(hwiosym); \
+                       reg = (reg & ~mask1) | (val1 & mask1); \
+                       reg = (reg & ~mask2) | (val2 & mask2); \
+                       HWIO_OUT(hwiosym, reg); \
+                    }
+
+#define HWIO_OPT_OUTM3(hwiosym, mask1, mask2, mask3, val1, val2, val3)       { \
+                       A_UINT32 reg; \
+                       reg = HWIO_IN(hwiosym); \
+                       reg = (reg & ~mask1) | (val1 & mask1); \
+                       reg = (reg & ~mask2) | (val2 & mask2); \
+                       reg = (reg & ~mask3) | (val3 & mask3); \
+                       HWIO_OUT(hwiosym, reg); \
+                    }
+
+#define HWIO_OPT_OUTM4(hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)       { \
+                       A_UINT32 reg; \
+                       reg = HWIO_IN(hwiosym); \
+                       reg = (reg & ~mask1) | (val1 & mask1); \
+                       reg = (reg & ~mask2) | (val2 & mask2); \
+                       reg = (reg & ~mask3) | (val3 & mask3); \
+                       reg = (reg & ~mask4) | (val4 & mask4); \
+                       HWIO_OUT(hwiosym, reg); \
+                    }
+
+#define HWIO_OPT_OUTM5(hwiosym, mask1, mask2, mask3, mask4, mask5, val1, val2, val3, val4, val5)       { \
+                       A_UINT32 reg; \
+                       reg = HWIO_IN(hwiosym); \
+                       reg = (reg & ~mask1) | (val1 & mask1); \
+                       reg = (reg & ~mask2) | (val2 & mask2); \
+                       reg = (reg & ~mask3) | (val3 & mask3); \
+                       reg = (reg & ~mask4) | (val4 & mask4); \
+                       reg = (reg & ~mask5) | (val5 & mask5); \
+                       HWIO_OUT(hwiosym, reg); \
+                    }
+
+#define HWIO_OPT_OUTM6(hwiosym, mask1, mask2, mask3, mask4, mask5, mask6, val1, val2, val3, val4, val5, val6)       { \
+                       A_UINT32 reg; \
+                       reg = HWIO_IN(hwiosym); \
+                       reg = (reg & ~mask1) | (val1 & mask1); \
+                       reg = (reg & ~mask2) | (val2 & mask2); \
+                       reg = (reg & ~mask3) | (val3 & mask3); \
+                       reg = (reg & ~mask4) | (val4 & mask4); \
+                       reg = (reg & ~mask5) | (val5 & mask5); \
+                       reg = (reg & ~mask6) | (val6 & mask6); \
+                       HWIO_OUT(hwiosym, reg); \
+                    }
+
+#define HWIO_OPT_OUT2F(io, field1, field2, val1, val2)                                    HWIO_OPT_OUTM2(io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
+#define HWIO_OPT_OUT3F(io, field1, field2, field3, val1, val2, val3)                      HWIO_OPT_OUTM3(io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
+#define HWIO_OPT_OUT4F(io, field1, field2, field3, field4, val1, val2, val3, val4)        HWIO_OPT_OUTM4(io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),  HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
+#define HWIO_OPT_OUT5F(io, field1, field2, field3, field4, field5, val1, val2, val3, val4, val5)        HWIO_OPT_OUTM5(io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),  HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5) )
+#define HWIO_OPT_OUT6F(io, field1, field2, field3, field4, field5, field6, val1, val2, val3, val4, val5, val6)        HWIO_OPT_OUTM6(io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),  HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), HWIO_FMSK(io, field6), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5), (uint32)(val6) << HWIO_SHFT(io, field6) )
+
+#define HWIO_OPT_OUTXM2(base, hwiosym, mask1, mask2, val1, val2)       { \
+                       A_UINT32 reg; \
+                       reg = HWIO_INX(base, hwiosym); \
+                       reg = (reg & ~mask1) | (val1 & mask1); \
+                       reg = (reg & ~mask2) | (val2 & mask2); \
+                       HWIO_OUTX(base, hwiosym, reg); \
+                    }
+
+#define HWIO_OPT_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)       { \
+                       A_UINT32 reg; \
+                       reg = HWIO_INX(base, hwiosym); \
+                       reg = (reg & ~mask1) | (val1 & mask1); \
+                       reg = (reg & ~mask2) | (val2 & mask2); \
+                       reg = (reg & ~mask3) | (val3 & mask3); \
+                       HWIO_OUTX(base, hwiosym, reg); \
+                    }
+
+#define HWIO_OPT_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)       { \
+                       A_UINT32 reg; \
+                       reg = HWIO_INX(base, hwiosym); \
+                       reg = (reg & ~mask1) | (val1 & mask1); \
+                       reg = (reg & ~mask2) | (val2 & mask2); \
+                       reg = (reg & ~mask3) | (val3 & mask3); \
+                       reg = (reg & ~mask4) | (val4 & mask4); \
+                       HWIO_OUTX(base, hwiosym, reg); \
+                    }
+
+#define HWIO_OPT_OUTXM5(base, hwiosym, mask1, mask2, mask3, mask4, mask5, val1, val2, val3, val4, val5)       { \
+                       A_UINT32 reg; \
+                       reg = HWIO_INX(base, hwiosym); \
+                       reg = (reg & ~mask1) | (val1 & mask1); \
+                       reg = (reg & ~mask2) | (val2 & mask2); \
+                       reg = (reg & ~mask3) | (val3 & mask3); \
+                       reg = (reg & ~mask4) | (val4 & mask4); \
+                       reg = (reg & ~mask5) | (val5 & mask5); \
+                       HWIO_OUTX(base, hwiosym, reg); \
+                    }
+
+#define HWIO_OPT_OUTXM6(base, hwiosym, mask1, mask2, mask3, mask4, mask5, mask6, val1, val2, val3, val4, val5, val6)       { \
+                       A_UINT32 reg; \
+                       reg = HWIO_INX(base, hwiosym); \
+                       reg = (reg & ~mask1) | (val1 & mask1); \
+                       reg = (reg & ~mask2) | (val2 & mask2); \
+                       reg = (reg & ~mask3) | (val3 & mask3); \
+                       reg = (reg & ~mask4) | (val4 & mask4); \
+                       reg = (reg & ~mask5) | (val5 & mask5); \
+                       reg = (reg & ~mask6) | (val6 & mask6); \
+                       HWIO_OUTX(base, hwiosym, reg); \
+                    }
+
+#define HWIO_OPT_OUTX2F(base, io, field1, field2, val1, val2)                                    HWIO_OPT_OUTXM2(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
+#define HWIO_OPT_OUTX3F(base, io, field1, field2, field3, val1, val2, val3)                      HWIO_OPT_OUTXM3(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
+#define HWIO_OPT_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4)        HWIO_OPT_OUTXM4(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),  HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
+#define HWIO_OPT_OUTX5F(base, io, field1, field2, field3, field4, field5, val1, val2, val3, val4, val5)        HWIO_OPT_OUTXM5(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),  HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5) )
+#define HWIO_OPT_OUTX6F(base, io, field1, field2, field3, field4, field5, field6, val1, val2, val3, val4, val5, val6)        HWIO_OPT_OUTXM6(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),  HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), HWIO_FMSK(io, field6), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5), (uint32)(val6) << HWIO_SHFT(io, field6) )
+
+#define HWIO_OUTXF(base, io, field, val)                                HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTX2F(base, io, field1, field2, val1, val2)                                HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
+#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3)                                HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
+#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4)                                HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),  HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
+
+#define HWIO_OUTXFI(base, io, index, field, val)                        HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI2(base, io, index1, index2, field, val)              HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val)      HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTXV(base, io, field, val)                                HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI(base, io, index, field, val)                        HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI2(base, io, index1, index2, field, val)              HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val)      HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_RMSK(hwiosym)                               __msmhwio_rmsk(hwiosym)
+#define HWIO_RMSKI(hwiosym, index)                       __msmhwio_rmski(hwiosym, index)
+#define HWIO_RSHFT(hwiosym)                              __msmhwio_rshft(hwiosym)
+#define HWIO_SHFT(hwio_regsym, hwio_fldsym)              __msmhwio_shft(hwio_regsym, hwio_fldsym)
+#define HWIO_FMSK(hwio_regsym, hwio_fldsym)              __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
+#define HWIO_VAL(io, field, val)                         __msmhwio_val(io, field, val)
+#define HWIO_FVAL(io, field, val)                        (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+#define HWIO_FVALV(io, field, val)                       (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+
+#define HWIO_SHDW(hwiosym)                               __msmhwio_shdw(hwiosym)
+#define HWIO_SHDWI(hwiosym, index)                       __msmhwio_shdwi(hwiosym, index)
+
+#define __msmhwio_in(hwiosym)                                   HWIO_##hwiosym##_IN
+#define __msmhwio_ini(hwiosym, index)                           HWIO_##hwiosym##_INI(index)
+#define __msmhwio_ini2(hwiosym, index1, index2)                 HWIO_##hwiosym##_INI2(index1, index2)
+#define __msmhwio_ini3(hwiosym, index1, index2, index3)         HWIO_##hwiosym##_INI3(index1, index2, index3)
+#define __msmhwio_inm(hwiosym, mask)                            HWIO_##hwiosym##_INM(mask)
+#define __msmhwio_inmi(hwiosym, index, mask)                    HWIO_##hwiosym##_INMI(index, mask)
+#define __msmhwio_inmi2(hwiosym, index1, index2, mask)          HWIO_##hwiosym##_INMI2(index1, index2, mask)
+#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)  HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
+#define __msmhwio_out(hwiosym, val)                             HWIO_##hwiosym##_OUT(val)
+#define __msmhwio_outi(hwiosym, index, val)                     HWIO_##hwiosym##_OUTI(index,val)
+#define __msmhwio_outi2(hwiosym, index1, index2, val)           HWIO_##hwiosym##_OUTI2(index1, index2, val)
+#define __msmhwio_outi3(hwiosym, index1, index2, index3, val)   HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
+#define __msmhwio_outm(hwiosym, mask, val)                      HWIO_##hwiosym##_OUTM(mask, val)
+#define __msmhwio_outmi(hwiosym, index, mask, val)              HWIO_##hwiosym##_OUTMI(index, mask, val)
+#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val)        HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
+#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val)  HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
+#define __msmhwio_addr(hwiosym)                                 HWIO_##hwiosym##_ADDR
+#define __msmhwio_addri(hwiosym, index)                         HWIO_##hwiosym##_ADDR(index)
+#define __msmhwio_addri2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_ADDR(idx1, idx2)
+#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
+#define __msmhwio_phys(hwiosym)                                 HWIO_##hwiosym##_PHYS
+#define __msmhwio_physi(hwiosym, index)                         HWIO_##hwiosym##_PHYS(index)
+#define __msmhwio_physi2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_PHYS(idx1, idx2)
+#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
+#define __msmhwio_offs(hwiosym)                                 HWIO_##hwiosym##_OFFS
+#define __msmhwio_offsi(hwiosym, index)                         HWIO_##hwiosym##_OFFS(index)
+#define __msmhwio_offsi2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_OFFS(idx1, idx2)
+#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
+#define __msmhwio_rmsk(hwiosym)                                 HWIO_##hwiosym##_RMSK
+#define __msmhwio_rmski(hwiosym, index)                         HWIO_##hwiosym##_RMSK(index)
+#define __msmhwio_fmsk(hwiosym, hwiofldsym)                     HWIO_##hwiosym##_##hwiofldsym##_BMSK
+#define __msmhwio_rshft(hwiosym)                                HWIO_##hwiosym##_SHFT
+#define __msmhwio_shft(hwiosym, hwiofldsym)                     HWIO_##hwiosym##_##hwiofldsym##_SHFT
+#define __msmhwio_shdw(hwiosym)                                 HWIO_##hwiosym##_shadow
+#define __msmhwio_shdwi(hwiosym, index)                         HWIO_##hwiosym##_SHDW(index)
+#define __msmhwio_val(hwiosym, hwiofld, hwioval)                HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
+
+#define __msmhwio_inx(base, hwiosym)                                  HWIO_##hwiosym##_IN(base)
+#define __msmhwio_inxi(base, hwiosym, index)                          HWIO_##hwiosym##_INI(base, index)
+#define __msmhwio_inxi2(base, hwiosym, index1, index2)                HWIO_##hwiosym##_INI2(base, index1, index2)
+#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3)        HWIO_##hwiosym##_INI3(base, index1, index2, index3)
+#define __msmhwio_inxm(base, hwiosym, mask)                           HWIO_##hwiosym##_INM(base, mask)
+#define __msmhwio_inxmi(base, hwiosym, index, mask)                   HWIO_##hwiosym##_INMI(base, index, mask)
+#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)         HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
+#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
+#define __msmhwio_outx(base, hwiosym, val)                            HWIO_##hwiosym##_OUT(base, val)
+#define __msmhwio_outxi(base, hwiosym, index, val)                    HWIO_##hwiosym##_OUTI(base, index,val)
+#define __msmhwio_outxi2(base, hwiosym, index1, index2, val)          HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
+#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)  HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
+#define __msmhwio_outxm(base, hwiosym, mask, val)                     HWIO_##hwiosym##_OUTM(base, mask, val)
+#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)  {	\
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                               }
+#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3,  val1, val2, val3) { \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask3, val3); \
+                                                                               }
+#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask3, val3); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask4, val4); \
+                                                                               }
+
+#define __msmhwio_outxmi(base, hwiosym, index, mask, val)             HWIO_##hwiosym##_OUTMI(base, index, mask, val)
+#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val)       HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
+#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
+#define __msmhwio_addrx(base, hwiosym)                                HWIO_##hwiosym##_ADDR(base)
+#define __msmhwio_addrxi(base, hwiosym, index)                        HWIO_##hwiosym##_ADDR(base, index)
+#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2)                  HWIO_##hwiosym##_ADDR(base, idx1, idx2)
+#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3)            HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
+#define __msmhwio_physx(base, hwiosym)                                HWIO_##hwiosym##_PHYS(base)
+#define __msmhwio_physxi(base, hwiosym, index)                        HWIO_##hwiosym##_PHYS(base, index)
+#define __msmhwio_physxi2(base, hwiosym, idx1, idx2)                  HWIO_##hwiosym##_PHYS(base, idx1, idx2)
+#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3)            HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
+
+#define HWIO_INTLOCK()
+#define HWIO_INTFREE()
+
+#define __inp(port)         (*((volatile uint8 *) (port)))
+#define __inpw(port)        (*((volatile uint16 *) (port)))
+#ifdef PLAT_MSL_REG_READ
+#ifdef __cplusplus
+extern "C" {
+#endif
+extern uint32 plat_register_read(uint32 addr);
+#ifdef __cplusplus
+}
+#endif
+
+#define __inpdw(port)    plat_register_read((uint32) (port))
+#else
+#define __inpdw(port)       (*((volatile uint32 *) (port)))
+#endif
+#define __outp(port, val)   (*((volatile uint8 *) (port)) = ((uint8) (val)))
+#define __outpw(port, val)  (*((volatile uint16 *) (port)) = ((uint16) (val)))
+#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
+
+#ifdef HAL_HWIO_EXTERNAL
+
+#undef  __inp
+#undef  __inpw
+#undef  __inpdw
+#undef  __outp
+#undef  __outpw
+#undef  __outpdw
+
+#define  __inp(port)          __inp_extern(port)
+#define  __inpw(port)         __inpw_extern(port)
+#define  __inpdw(port)        __inpdw_extern(port)
+#define  __outp(port, val)    __outp_extern(port, val)
+#define  __outpw(port, val)   __outpw_extern(port, val)
+#define  __outpdw(port, val)  __outpdw_extern(port, val)
+
+extern uint8   __inp_extern      ( uint32 nAddr );
+extern uint16  __inpw_extern     ( uint32 nAddr );
+extern uint32  __inpdw_extern    ( uint32 nAddr );
+extern void    __outp_extern     ( uint32 nAddr, uint8  nData );
+extern void    __outpw_extern    ( uint32 nAddr, uint16 nData );
+extern void    __outpdw_extern   ( uint32 nAddr, uint32 nData );
+
+#endif
+
+#define in_byte(addr)               (__inp(addr))
+#define in_byte_masked(addr, mask)  (__inp(addr) & (mask))
+#define out_byte(addr, val)         __outp(addr,val)
+#define out_byte_masked(io, mask, val, shadow)  \
+  HWIO_INTLOCK();    \
+  out_byte( io, shadow); \
+  shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
+  HWIO_INTFREE()
+#define out_byte_masked_ns(io, mask, val, current_reg_content)  \
+  out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
+                ((uint16)((val) & (mask)))) )
+
+#define in_word(addr)              (__inpw(addr))
+#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
+#define out_word(addr, val)        __outpw(addr,val)
+#define out_word_masked(io, mask, val, shadow)  \
+  HWIO_INTLOCK( ); \
+  shadow = (shadow & (uint16)(~(mask))) |  ((uint16)((val) & (mask))); \
+  out_word( io, shadow); \
+  HWIO_INTFREE( )
+#define out_word_masked_ns(io, mask, val, current_reg_content)  \
+  out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
+                ((uint16)((val) & (mask)))) )
+
+#define in_dword(addr)              (__inpdw(addr))
+#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
+#define out_dword(addr, val)        __outpdw(addr,val)
+#define out_dword_masked(io, mask, val, shadow)  \
+   HWIO_INTLOCK(); \
+   shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
+   out_dword( io, shadow); \
+   HWIO_INTFREE()
+#define out_dword_masked_ns(io, mask, val, current_reg_content) \
+  out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
+                 ((uint32)((val) & (mask)))) )
+
+#endif
+

hw/wcn6450/v1/buffer_addr_info.h

@@ -0,0 +1,52 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _BUFFER_ADDR_INFO_H_
+#define _BUFFER_ADDR_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
+
+struct buffer_addr_info {
+             uint32_t buffer_addr_31_0                : 32;
+             uint32_t buffer_addr_39_32               :  8,
+                      return_buffer_manager           :  3,
+                      sw_buffer_cookie                : 21;
+};
+
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET                   0x00000000
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB                      0
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK                     0xffffffff
+
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET                  0x00000004
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB                     0
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK                    0x000000ff
+
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET              0x00000004
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB                 8
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK                0x00000700
+
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET                   0x00000004
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB                      11
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK                     0xfffff800
+
+#endif

hw/wcn6450/v1/ce_src_desc.h

@@ -0,0 +1,97 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _CE_SRC_DESC_H_
+#define _CE_SRC_DESC_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_CE_SRC_DESC 4
+
+struct ce_src_desc {
+             uint32_t src_buffer_low                  : 32;
+             uint32_t src_buffer_high                 :  8,
+                      toeplitz_en                     :  1,
+                      src_swap                        :  1,
+                      dest_swap                       :  1,
+                      gather                          :  1,
+                      ce_res_0                        :  4,
+                      length                          : 16;
+             uint32_t fw_metadata                     : 16,
+                      ce_res_1                        : 16;
+             uint32_t ce_res_2                        : 20,
+                      ring_id                         :  8,
+                      looping_count                   :  4;
+};
+
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET                          0x00000000
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB                             0
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK                            0xffffffff
+
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET                         0x00000004
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB                            0
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK                           0x000000ff
+
+#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET                             0x00000004
+#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB                                8
+#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK                               0x00000100
+
+#define CE_SRC_DESC_1_SRC_SWAP_OFFSET                                0x00000004
+#define CE_SRC_DESC_1_SRC_SWAP_LSB                                   9
+#define CE_SRC_DESC_1_SRC_SWAP_MASK                                  0x00000200
+
+#define CE_SRC_DESC_1_DEST_SWAP_OFFSET                               0x00000004
+#define CE_SRC_DESC_1_DEST_SWAP_LSB                                  10
+#define CE_SRC_DESC_1_DEST_SWAP_MASK                                 0x00000400
+
+#define CE_SRC_DESC_1_GATHER_OFFSET                                  0x00000004
+#define CE_SRC_DESC_1_GATHER_LSB                                     11
+#define CE_SRC_DESC_1_GATHER_MASK                                    0x00000800
+
+#define CE_SRC_DESC_1_CE_RES_0_OFFSET                                0x00000004
+#define CE_SRC_DESC_1_CE_RES_0_LSB                                   12
+#define CE_SRC_DESC_1_CE_RES_0_MASK                                  0x0000f000
+
+#define CE_SRC_DESC_1_LENGTH_OFFSET                                  0x00000004
+#define CE_SRC_DESC_1_LENGTH_LSB                                     16
+#define CE_SRC_DESC_1_LENGTH_MASK                                    0xffff0000
+
+#define CE_SRC_DESC_2_FW_METADATA_OFFSET                             0x00000008
+#define CE_SRC_DESC_2_FW_METADATA_LSB                                0
+#define CE_SRC_DESC_2_FW_METADATA_MASK                               0x0000ffff
+
+#define CE_SRC_DESC_2_CE_RES_1_OFFSET                                0x00000008
+#define CE_SRC_DESC_2_CE_RES_1_LSB                                   16
+#define CE_SRC_DESC_2_CE_RES_1_MASK                                  0xffff0000
+
+#define CE_SRC_DESC_3_CE_RES_2_OFFSET                                0x0000000c
+#define CE_SRC_DESC_3_CE_RES_2_LSB                                   0
+#define CE_SRC_DESC_3_CE_RES_2_MASK                                  0x000fffff
+
+#define CE_SRC_DESC_3_RING_ID_OFFSET                                 0x0000000c
+#define CE_SRC_DESC_3_RING_ID_LSB                                    20
+#define CE_SRC_DESC_3_RING_ID_MASK                                   0x0ff00000
+
+#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET                           0x0000000c
+#define CE_SRC_DESC_3_LOOPING_COUNT_LSB                              28
+#define CE_SRC_DESC_3_LOOPING_COUNT_MASK                             0xf0000000
+
+#endif

hw/wcn6450/v1/ce_stat_desc.h

@@ -0,0 +1,97 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _CE_STAT_DESC_H_
+#define _CE_STAT_DESC_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_CE_STAT_DESC 4
+
+struct ce_stat_desc {
+             uint32_t ce_res_5                        :  8,
+                      toeplitz_en                     :  1,
+                      src_swap                        :  1,
+                      dest_swap                       :  1,
+                      gather                          :  1,
+                      ce_res_6                        :  4,
+                      length                          : 16;
+             uint32_t toeplitz_hash_0                 : 32;
+             uint32_t toeplitz_hash_1                 : 32;
+             uint32_t fw_metadata                     : 16,
+                      ce_res_7                        :  4,
+                      ring_id                         :  8,
+                      looping_count                   :  4;
+};
+
+#define CE_STAT_DESC_0_CE_RES_5_OFFSET                               0x00000000
+#define CE_STAT_DESC_0_CE_RES_5_LSB                                  0
+#define CE_STAT_DESC_0_CE_RES_5_MASK                                 0x000000ff
+
+#define CE_STAT_DESC_0_TOEPLITZ_EN_OFFSET                            0x00000000
+#define CE_STAT_DESC_0_TOEPLITZ_EN_LSB                               8
+#define CE_STAT_DESC_0_TOEPLITZ_EN_MASK                              0x00000100
+
+#define CE_STAT_DESC_0_SRC_SWAP_OFFSET                               0x00000000
+#define CE_STAT_DESC_0_SRC_SWAP_LSB                                  9
+#define CE_STAT_DESC_0_SRC_SWAP_MASK                                 0x00000200
+
+#define CE_STAT_DESC_0_DEST_SWAP_OFFSET                              0x00000000
+#define CE_STAT_DESC_0_DEST_SWAP_LSB                                 10
+#define CE_STAT_DESC_0_DEST_SWAP_MASK                                0x00000400
+
+#define CE_STAT_DESC_0_GATHER_OFFSET                                 0x00000000
+#define CE_STAT_DESC_0_GATHER_LSB                                    11
+#define CE_STAT_DESC_0_GATHER_MASK                                   0x00000800
+
+#define CE_STAT_DESC_0_CE_RES_6_OFFSET                               0x00000000
+#define CE_STAT_DESC_0_CE_RES_6_LSB                                  12
+#define CE_STAT_DESC_0_CE_RES_6_MASK                                 0x0000f000
+
+#define CE_STAT_DESC_0_LENGTH_OFFSET                                 0x00000000
+#define CE_STAT_DESC_0_LENGTH_LSB                                    16
+#define CE_STAT_DESC_0_LENGTH_MASK                                   0xffff0000
+
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_OFFSET                        0x00000004
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_LSB                           0
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_MASK                          0xffffffff
+
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_OFFSET                        0x00000008
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_LSB                           0
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_MASK                          0xffffffff
+
+#define CE_STAT_DESC_3_FW_METADATA_OFFSET                            0x0000000c
+#define CE_STAT_DESC_3_FW_METADATA_LSB                               0
+#define CE_STAT_DESC_3_FW_METADATA_MASK                              0x0000ffff
+
+#define CE_STAT_DESC_3_CE_RES_7_OFFSET                               0x0000000c
+#define CE_STAT_DESC_3_CE_RES_7_LSB                                  16
+#define CE_STAT_DESC_3_CE_RES_7_MASK                                 0x000f0000
+
+#define CE_STAT_DESC_3_RING_ID_OFFSET                                0x0000000c
+#define CE_STAT_DESC_3_RING_ID_LSB                                   20
+#define CE_STAT_DESC_3_RING_ID_MASK                                  0x0ff00000
+
+#define CE_STAT_DESC_3_LOOPING_COUNT_OFFSET                          0x0000000c
+#define CE_STAT_DESC_3_LOOPING_COUNT_LSB                             28
+#define CE_STAT_DESC_3_LOOPING_COUNT_MASK                            0xf0000000
+
+#endif

hw/wcn6450/v1/com_dtypes.h

@@ -0,0 +1,182 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef COM_DTYPES_H
+#define COM_DTYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef T_WINNT
+   #ifndef WIN32
+      #define WIN32
+   #endif
+   #include <stdlib.h>
+#endif
+
+#ifdef TRUE
+#undef TRUE
+#endif
+
+#ifdef FALSE
+#undef FALSE
+#endif
+
+#define TRUE   1
+#define FALSE  0
+
+#define  ON   1
+#define  OFF  0
+
+#ifndef NULL
+  #define NULL  0
+#endif
+
+#ifndef _ARM_ASM_
+#ifndef _BOOLEAN_DEFINED
+
+typedef  unsigned char      boolean;
+#define _BOOLEAN_DEFINED
+#endif
+
+#if defined(DALSTDDEF_H)
+#define _BOOLEAN_DEFINED
+#define _UINT32_DEFINED
+#define _UINT16_DEFINED
+#define _UINT8_DEFINED
+#define _INT32_DEFINED
+#define _INT16_DEFINED
+#define _INT8_DEFINED
+#define _UINT64_DEFINED
+#define _INT64_DEFINED
+#define _BYTE_DEFINED
+#endif
+
+#ifndef _UINT32_DEFINED
+
+typedef  unsigned long int  uint32;
+#define _UINT32_DEFINED
+#endif
+
+#ifndef _UINT16_DEFINED
+
+typedef  unsigned short     uint16;
+#define _UINT16_DEFINED
+#endif
+
+#ifndef _UINT8_DEFINED
+
+typedef  unsigned char      uint8;
+#define _UINT8_DEFINED
+#endif
+
+#ifndef _INT32_DEFINED
+
+typedef  signed long int    int32;
+#define _INT32_DEFINED
+#endif
+
+#ifndef _INT16_DEFINED
+
+typedef  signed short       int16;
+#define _INT16_DEFINED
+#endif
+
+#ifndef _INT8_DEFINED
+
+typedef  signed char        int8;
+#define _INT8_DEFINED
+#endif
+
+#ifndef _BYTE_DEFINED
+
+typedef  unsigned char      byte;
+#define  _BYTE_DEFINED
+#endif
+
+typedef  unsigned short     word;
+
+typedef  unsigned long      dword;
+
+typedef  unsigned char      uint1;
+
+typedef  unsigned short     uint2;
+
+typedef  unsigned long      uint4;
+
+typedef  signed char        int1;
+
+typedef  signed short       int2;
+
+typedef  long int           int4;
+
+typedef  signed long        sint31;
+
+typedef  signed short       sint15;
+
+typedef  signed char        sint7;
+
+typedef uint16 UWord16 ;
+typedef uint32 UWord32 ;
+typedef int32  Word32 ;
+typedef int16  Word16 ;
+typedef uint8  UWord8 ;
+typedef int8   Word8 ;
+typedef int32  Vect32 ;
+
+#if (! defined T_WINNT) && (! defined __GNUC__)
+
+  #ifndef _INT64_DEFINED
+
+    typedef long long     int64;
+    #define _INT64_DEFINED
+  #endif
+  #ifndef _UINT64_DEFINED
+
+    typedef  unsigned long long  uint64;
+    #define _UINT64_DEFINED
+  #endif
+#else
+
+  #if (defined __GNUC__)
+    #ifndef _INT64_DEFINED
+      typedef long long           int64;
+      #define _INT64_DEFINED
+    #endif
+    #ifndef _UINT64_DEFINED
+      typedef unsigned long long  uint64;
+      #define _UINT64_DEFINED
+    #endif
+  #else
+    typedef  __int64              int64;
+    #ifndef _UINT64_DEFINED
+      typedef  unsigned __int64   uint64;
+      #define _UINT64_DEFINED
+    #endif
+  #endif
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

hw/wcn6450/v1/he_sig_a_mu_dl_info.h

@@ -0,0 +1,137 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HE_SIG_A_MU_DL_INFO_H_
+#define _HE_SIG_A_MU_DL_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2
+
+struct he_sig_a_mu_dl_info {
+             uint32_t dl_ul_flag                      :  1,
+                      mcs_of_sig_b                    :  3,
+                      dcm_of_sig_b                    :  1,
+                      bss_color_id                    :  6,
+                      spatial_reuse                   :  4,
+                      transmit_bw                     :  3,
+                      num_sig_b_symbols               :  4,
+                      comp_mode_sig_b                 :  1,
+                      cp_ltf_size                     :  2,
+                      doppler_indication              :  1,
+                      reserved_0a                     :  6;
+             uint32_t txop_duration                   :  7,
+                      reserved_1a                     :  1,
+                      num_ltf_symbols                 :  3,
+                      ldpc_extra_symbol               :  1,
+                      stbc                            :  1,
+                      packet_extension_a_factor       :  2,
+                      packet_extension_pe_disambiguity:  1,
+                      crc                             :  4,
+                      tail                            :  6,
+                      reserved_1b                     :  6;
+};
+
+#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_OFFSET                      0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_LSB                         0
+#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_MASK                        0x00000001
+
+#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_OFFSET                    0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_LSB                       1
+#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_MASK                      0x0000000e
+
+#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_OFFSET                    0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_LSB                       4
+#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_MASK                      0x00000010
+
+#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_OFFSET                    0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_LSB                       5
+#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_MASK                      0x000007e0
+
+#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_OFFSET                   0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_LSB                      11
+#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_MASK                     0x00007800
+
+#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_OFFSET                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_LSB                        15
+#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_MASK                       0x00038000
+
+#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_OFFSET               0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_LSB                  18
+#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_MASK                 0x003c0000
+
+#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_OFFSET                 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_LSB                    22
+#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_MASK                   0x00400000
+
+#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_OFFSET                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_LSB                        23
+#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_MASK                       0x01800000
+
+#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_OFFSET              0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_LSB                 25
+#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_MASK                0x02000000
+
+#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_OFFSET                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_LSB                        26
+#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_MASK                       0xfc000000
+
+#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_OFFSET                   0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_LSB                      0
+#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_MASK                     0x0000007f
+
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_OFFSET                     0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_LSB                        7
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_MASK                       0x00000080
+
+#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_OFFSET                 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_LSB                    8
+#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_MASK                   0x00000700
+
+#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET               0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_LSB                  11
+#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_MASK                 0x00000800
+
+#define HE_SIG_A_MU_DL_INFO_1_STBC_OFFSET                            0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_STBC_LSB                               12
+#define HE_SIG_A_MU_DL_INFO_1_STBC_MASK                              0x00001000
+
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET       0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB          13
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK         0x00006000
+
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB   15
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK  0x00008000
+
+#define HE_SIG_A_MU_DL_INFO_1_CRC_OFFSET                             0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_CRC_LSB                                16
+#define HE_SIG_A_MU_DL_INFO_1_CRC_MASK                               0x000f0000
+
+#define HE_SIG_A_MU_DL_INFO_1_TAIL_OFFSET                            0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_TAIL_LSB                               20
+#define HE_SIG_A_MU_DL_INFO_1_TAIL_MASK                              0x03f00000
+
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_OFFSET                     0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_LSB                        26
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_MASK                       0xfc000000
+
+#endif

hw/wcn6450/v1/he_sig_a_mu_ul_info.h

@@ -0,0 +1,87 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HE_SIG_A_MU_UL_INFO_H_
+#define _HE_SIG_A_MU_UL_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
+
+struct he_sig_a_mu_ul_info {
+             uint32_t format_indication               :  1,
+                      bss_color_id                    :  6,
+                      spatial_reuse                   : 16,
+                      reserved_0a                     :  1,
+                      transmit_bw                     :  2,
+                      reserved_0b                     :  6;
+             uint32_t txop_duration                   :  7,
+                      reserved_1a                     :  9,
+                      crc                             :  4,
+                      tail                            :  6,
+                      reserved_1b                     :  6;
+};
+
+#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_OFFSET               0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_LSB                  0
+#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_MASK                 0x00000001
+
+#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_OFFSET                    0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_LSB                       1
+#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_MASK                      0x0000007e
+
+#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_OFFSET                   0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_LSB                      7
+#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_MASK                     0x007fff80
+
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_OFFSET                     0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_LSB                        23
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_MASK                       0x00800000
+
+#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_OFFSET                     0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_LSB                        24
+#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_MASK                       0x03000000
+
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_OFFSET                     0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_LSB                        26
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_MASK                       0xfc000000
+
+#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_OFFSET                   0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_LSB                      0
+#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_MASK                     0x0000007f
+
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_OFFSET                     0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_LSB                        7
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_MASK                       0x0000ff80
+
+#define HE_SIG_A_MU_UL_INFO_1_CRC_OFFSET                             0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_CRC_LSB                                16
+#define HE_SIG_A_MU_UL_INFO_1_CRC_MASK                               0x000f0000
+
+#define HE_SIG_A_MU_UL_INFO_1_TAIL_OFFSET                            0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_TAIL_LSB                               20
+#define HE_SIG_A_MU_UL_INFO_1_TAIL_MASK                              0x03f00000
+
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_OFFSET                     0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_LSB                        26
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_MASK                       0xfc000000
+
+#endif

hw/wcn6450/v1/he_sig_a_su_info.h

@@ -0,0 +1,162 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HE_SIG_A_SU_INFO_H_
+#define _HE_SIG_A_SU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2
+
+struct he_sig_a_su_info {
+             uint32_t format_indication               :  1,
+                      beam_change                     :  1,
+                      dl_ul_flag                      :  1,
+                      transmit_mcs                    :  4,
+                      dcm                             :  1,
+                      bss_color_id                    :  6,
+                      reserved_0a                     :  1,
+                      spatial_reuse                   :  4,
+                      transmit_bw                     :  2,
+                      cp_ltf_size                     :  2,
+                      nsts                            :  3,
+                      reserved_0b                     :  6;
+             uint32_t txop_duration                   :  7,
+                      coding                          :  1,
+                      ldpc_extra_symbol               :  1,
+                      stbc                            :  1,
+                      txbf                            :  1,
+                      packet_extension_a_factor       :  2,
+                      packet_extension_pe_disambiguity:  1,
+                      reserved_1a                     :  1,
+                      doppler_indication              :  1,
+                      crc                             :  4,
+                      tail                            :  6,
+                      dot11ax_su_extended             :  1,
+                      dot11ax_ext_ru_size             :  4,
+                      rx_ndp                          :  1;
+};
+
+#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_OFFSET                  0x00000000
+#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_LSB                     0
+#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_MASK                    0x00000001
+
+#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_OFFSET                        0x00000000
+#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_LSB                           1
+#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_MASK                          0x00000002
+
+#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_OFFSET                         0x00000000
+#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_LSB                            2
+#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_MASK                           0x00000004
+
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_OFFSET                       0x00000000
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_LSB                          3
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_MASK                         0x00000078
+
+#define HE_SIG_A_SU_INFO_0_DCM_OFFSET                                0x00000000
+#define HE_SIG_A_SU_INFO_0_DCM_LSB                                   7
+#define HE_SIG_A_SU_INFO_0_DCM_MASK                                  0x00000080
+
+#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_OFFSET                       0x00000000
+#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_LSB                          8
+#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_MASK                         0x00003f00
+
+#define HE_SIG_A_SU_INFO_0_RESERVED_0A_OFFSET                        0x00000000
+#define HE_SIG_A_SU_INFO_0_RESERVED_0A_LSB                           14
+#define HE_SIG_A_SU_INFO_0_RESERVED_0A_MASK                          0x00004000
+
+#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_OFFSET                      0x00000000
+#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_LSB                         15
+#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_MASK                        0x00078000
+
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_OFFSET                        0x00000000
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_LSB                           19
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_MASK                          0x00180000
+
+#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_OFFSET                        0x00000000
+#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_LSB                           21
+#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_MASK                          0x00600000
+
+#define HE_SIG_A_SU_INFO_0_NSTS_OFFSET                               0x00000000
+#define HE_SIG_A_SU_INFO_0_NSTS_LSB                                  23
+#define HE_SIG_A_SU_INFO_0_NSTS_MASK                                 0x03800000
+
+#define HE_SIG_A_SU_INFO_0_RESERVED_0B_OFFSET                        0x00000000
+#define HE_SIG_A_SU_INFO_0_RESERVED_0B_LSB                           26
+#define HE_SIG_A_SU_INFO_0_RESERVED_0B_MASK                          0xfc000000
+
+#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_OFFSET                      0x00000004
+#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_LSB                         0
+#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_MASK                        0x0000007f
+
+#define HE_SIG_A_SU_INFO_1_CODING_OFFSET                             0x00000004
+#define HE_SIG_A_SU_INFO_1_CODING_LSB                                7
+#define HE_SIG_A_SU_INFO_1_CODING_MASK                               0x00000080
+
+#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET                  0x00000004
+#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_LSB                     8
+#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_MASK                    0x00000100
+
+#define HE_SIG_A_SU_INFO_1_STBC_OFFSET                               0x00000004
+#define HE_SIG_A_SU_INFO_1_STBC_LSB                                  9
+#define HE_SIG_A_SU_INFO_1_STBC_MASK                                 0x00000200
+
+#define HE_SIG_A_SU_INFO_1_TXBF_OFFSET                               0x00000004
+#define HE_SIG_A_SU_INFO_1_TXBF_LSB                                  10
+#define HE_SIG_A_SU_INFO_1_TXBF_MASK                                 0x00000400
+
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET          0x00000004
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB             11
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK            0x00001800
+
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET   0x00000004
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB      13
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK     0x00002000
+
+#define HE_SIG_A_SU_INFO_1_RESERVED_1A_OFFSET                        0x00000004
+#define HE_SIG_A_SU_INFO_1_RESERVED_1A_LSB                           14
+#define HE_SIG_A_SU_INFO_1_RESERVED_1A_MASK                          0x00004000
+
+#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_OFFSET                 0x00000004
+#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_LSB                    15
+#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_MASK                   0x00008000
+
+#define HE_SIG_A_SU_INFO_1_CRC_OFFSET                                0x00000004
+#define HE_SIG_A_SU_INFO_1_CRC_LSB                                   16
+#define HE_SIG_A_SU_INFO_1_CRC_MASK                                  0x000f0000
+
+#define HE_SIG_A_SU_INFO_1_TAIL_OFFSET                               0x00000004
+#define HE_SIG_A_SU_INFO_1_TAIL_LSB                                  20
+#define HE_SIG_A_SU_INFO_1_TAIL_MASK                                 0x03f00000
+
+#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_OFFSET                0x00000004
+#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_LSB                   26
+#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_MASK                  0x04000000
+
+#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_OFFSET                0x00000004
+#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_LSB                   27
+#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_MASK                  0x78000000
+
+#define HE_SIG_A_SU_INFO_1_RX_NDP_OFFSET                             0x00000004
+#define HE_SIG_A_SU_INFO_1_RX_NDP_LSB                                31
+#define HE_SIG_A_SU_INFO_1_RX_NDP_MASK                               0x80000000
+
+#endif

hw/wcn6450/v1/he_sig_b1_mu_info.h

@@ -0,0 +1,42 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HE_SIG_B1_MU_INFO_H_
+#define _HE_SIG_B1_MU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
+
+struct he_sig_b1_mu_info {
+             uint32_t ru_allocation                   :  8,
+                      reserved_0                      : 24;
+};
+
+#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_OFFSET                     0x00000000
+#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_LSB                        0
+#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_MASK                       0x000000ff
+
+#define HE_SIG_B1_MU_INFO_0_RESERVED_0_OFFSET                        0x00000000
+#define HE_SIG_B1_MU_INFO_0_RESERVED_0_LSB                           8
+#define HE_SIG_B1_MU_INFO_0_RESERVED_0_MASK                          0xffffff00
+
+#endif

hw/wcn6450/v1/he_sig_b2_mu_info.h

@@ -0,0 +1,67 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HE_SIG_B2_MU_INFO_H_
+#define _HE_SIG_B2_MU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 1
+
+struct he_sig_b2_mu_info {
+             uint32_t sta_id                          : 11,
+                      sta_spatial_config              :  4,
+                      sta_mcs                         :  4,
+                      reserved_set_to_1               :  1,
+                      sta_coding                      :  1,
+                      reserved_0a                     :  8,
+                      nsts                            :  3;
+};
+
+#define HE_SIG_B2_MU_INFO_0_STA_ID_OFFSET                            0x00000000
+#define HE_SIG_B2_MU_INFO_0_STA_ID_LSB                               0
+#define HE_SIG_B2_MU_INFO_0_STA_ID_MASK                              0x000007ff
+
+#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_OFFSET                0x00000000
+#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_LSB                   11
+#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_MASK                  0x00007800
+
+#define HE_SIG_B2_MU_INFO_0_STA_MCS_OFFSET                           0x00000000
+#define HE_SIG_B2_MU_INFO_0_STA_MCS_LSB                              15
+#define HE_SIG_B2_MU_INFO_0_STA_MCS_MASK                             0x00078000
+
+#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_OFFSET                 0x00000000
+#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_LSB                    19
+#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_MASK                   0x00080000
+
+#define HE_SIG_B2_MU_INFO_0_STA_CODING_OFFSET                        0x00000000
+#define HE_SIG_B2_MU_INFO_0_STA_CODING_LSB                           20
+#define HE_SIG_B2_MU_INFO_0_STA_CODING_MASK                          0x00100000
+
+#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_OFFSET                       0x00000000
+#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_LSB                          21
+#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_MASK                         0x1fe00000
+
+#define HE_SIG_B2_MU_INFO_0_NSTS_OFFSET                              0x00000000
+#define HE_SIG_B2_MU_INFO_0_NSTS_LSB                                 29
+#define HE_SIG_B2_MU_INFO_0_NSTS_MASK                                0xe0000000
+
+#endif

hw/wcn6450/v1/he_sig_b2_ofdma_info.h

@@ -0,0 +1,67 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HE_SIG_B2_OFDMA_INFO_H_
+#define _HE_SIG_B2_OFDMA_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 1
+
+struct he_sig_b2_ofdma_info {
+             uint32_t sta_id                          : 11,
+                      nsts                            :  3,
+                      txbf                            :  1,
+                      sta_mcs                         :  4,
+                      sta_dcm                         :  1,
+                      sta_coding                      :  1,
+                      reserved_0                      : 11;
+};
+
+#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_OFFSET                         0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_LSB                            0
+#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_MASK                           0x000007ff
+
+#define HE_SIG_B2_OFDMA_INFO_0_NSTS_OFFSET                           0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_NSTS_LSB                              11
+#define HE_SIG_B2_OFDMA_INFO_0_NSTS_MASK                             0x00003800
+
+#define HE_SIG_B2_OFDMA_INFO_0_TXBF_OFFSET                           0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_TXBF_LSB                              14
+#define HE_SIG_B2_OFDMA_INFO_0_TXBF_MASK                             0x00004000
+
+#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_OFFSET                        0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_LSB                           15
+#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_MASK                          0x00078000
+
+#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_OFFSET                        0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_LSB                           19
+#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_MASK                          0x00080000
+
+#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_OFFSET                     0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_LSB                        20
+#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_MASK                       0x00100000
+
+#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_OFFSET                     0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_LSB                        21
+#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_MASK                       0xffe00000
+
+#endif

hw/wcn6450/v1/ht_sig_info.h

@@ -0,0 +1,107 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _HT_SIG_INFO_H_
+#define _HT_SIG_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_HT_SIG_INFO 2
+
+struct ht_sig_info {
+             uint32_t mcs                             :  7,
+                      cbw                             :  1,
+                      length                          : 16,
+                      reserved_0                      :  8;
+             uint32_t smoothing                       :  1,
+                      not_sounding                    :  1,
+                      ht_reserved                     :  1,
+                      aggregation                     :  1,
+                      stbc                            :  2,
+                      fec_coding                      :  1,
+                      short_gi                        :  1,
+                      num_ext_sp_str                  :  2,
+                      crc                             :  8,
+                      signal_tail                     :  6,
+                      reserved_1                      :  8;
+};
+
+#define HT_SIG_INFO_0_MCS_OFFSET                                     0x00000000
+#define HT_SIG_INFO_0_MCS_LSB                                        0
+#define HT_SIG_INFO_0_MCS_MASK                                       0x0000007f
+
+#define HT_SIG_INFO_0_CBW_OFFSET                                     0x00000000
+#define HT_SIG_INFO_0_CBW_LSB                                        7
+#define HT_SIG_INFO_0_CBW_MASK                                       0x00000080
+
+#define HT_SIG_INFO_0_LENGTH_OFFSET                                  0x00000000
+#define HT_SIG_INFO_0_LENGTH_LSB                                     8
+#define HT_SIG_INFO_0_LENGTH_MASK                                    0x00ffff00
+
+#define HT_SIG_INFO_0_RESERVED_0_OFFSET                              0x00000000
+#define HT_SIG_INFO_0_RESERVED_0_LSB                                 24
+#define HT_SIG_INFO_0_RESERVED_0_MASK                                0xff000000
+
+#define HT_SIG_INFO_1_SMOOTHING_OFFSET                               0x00000004
+#define HT_SIG_INFO_1_SMOOTHING_LSB                                  0
+#define HT_SIG_INFO_1_SMOOTHING_MASK                                 0x00000001
+
+#define HT_SIG_INFO_1_NOT_SOUNDING_OFFSET                            0x00000004
+#define HT_SIG_INFO_1_NOT_SOUNDING_LSB                               1
+#define HT_SIG_INFO_1_NOT_SOUNDING_MASK                              0x00000002
+
+#define HT_SIG_INFO_1_HT_RESERVED_OFFSET                             0x00000004
+#define HT_SIG_INFO_1_HT_RESERVED_LSB                                2
+#define HT_SIG_INFO_1_HT_RESERVED_MASK                               0x00000004
+
+#define HT_SIG_INFO_1_AGGREGATION_OFFSET                             0x00000004
+#define HT_SIG_INFO_1_AGGREGATION_LSB                                3
+#define HT_SIG_INFO_1_AGGREGATION_MASK                               0x00000008
+
+#define HT_SIG_INFO_1_STBC_OFFSET                                    0x00000004
+#define HT_SIG_INFO_1_STBC_LSB                                       4
+#define HT_SIG_INFO_1_STBC_MASK                                      0x00000030
+
+#define HT_SIG_INFO_1_FEC_CODING_OFFSET                              0x00000004
+#define HT_SIG_INFO_1_FEC_CODING_LSB                                 6
+#define HT_SIG_INFO_1_FEC_CODING_MASK                                0x00000040
+
+#define HT_SIG_INFO_1_SHORT_GI_OFFSET                                0x00000004
+#define HT_SIG_INFO_1_SHORT_GI_LSB                                   7
+#define HT_SIG_INFO_1_SHORT_GI_MASK                                  0x00000080
+
+#define HT_SIG_INFO_1_NUM_EXT_SP_STR_OFFSET                          0x00000004
+#define HT_SIG_INFO_1_NUM_EXT_SP_STR_LSB                             8
+#define HT_SIG_INFO_1_NUM_EXT_SP_STR_MASK                            0x00000300
+
+#define HT_SIG_INFO_1_CRC_OFFSET                                     0x00000004
+#define HT_SIG_INFO_1_CRC_LSB                                        10
+#define HT_SIG_INFO_1_CRC_MASK                                       0x0003fc00
+
+#define HT_SIG_INFO_1_SIGNAL_TAIL_OFFSET                             0x00000004
+#define HT_SIG_INFO_1_SIGNAL_TAIL_LSB                                18
+#define HT_SIG_INFO_1_SIGNAL_TAIL_MASK                               0x00fc0000
+
+#define HT_SIG_INFO_1_RESERVED_1_OFFSET                              0x00000004
+#define HT_SIG_INFO_1_RESERVED_1_LSB                                 24
+#define HT_SIG_INFO_1_RESERVED_1_MASK                                0xff000000
+
+#endif

hw/wcn6450/v1/hwio.h

@@ -0,0 +1,1322 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef __HWIO_H__
+#define __HWIO_H__
+
+#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE                                                         (HOST_SOC_WFSS_CE_REG_TOP_BASE      + 0x00000000)
+#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE_SIZE                                                    0x1000
+#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE_USED                                                    0x8c
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR                                                            (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x0)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_RMSK                                                            0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_BASE_ADDR_LOW_BMSK                                              0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_BASE_ADDR_LOW_SHFT                                                       0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR                                                           (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x4)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_RMSK                                                                 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_BASE_ADDR_HIGH_BMSK                                                  0xff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_BASE_ADDR_HIGH_SHFT                                                     0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR                                                              (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x8)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_RMSK                                                              0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_START_OFFSET_BMSK                                                 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_START_OFFSET_SHFT                                                         16
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_SIZE_BMSK                                                             0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_SIZE_SHFT                                                                  0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR                                                            (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0xc)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_RMSK                                                            0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_BASE_ADDR_LOW_BMSK                                              0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_BASE_ADDR_LOW_SHFT                                                       0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR                                                           (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x10)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_RMSK                                                                0x3ff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_DESC_SKIP_DWORD_BMSK                                                0x300
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_DESC_SKIP_DWORD_SHFT                                                    8
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_BASE_ADDR_HIGH_BMSK                                                  0xff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_BASE_ADDR_HIGH_SHFT                                                     0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR                                                              (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x14)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_RMSK                                                              0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_START_OFFSET_BMSK                                                 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_START_OFFSET_SHFT                                                         16
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_SIZE_BMSK                                                             0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_SIZE_SHFT                                                                  0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR                                                             (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x18)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_RMSK                                                              0x1ffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_TARGET_MSI_EN_BMSK                                                0x1000000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_TARGET_MSI_EN_SHFT                                                       24
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_FW_EN_BMSK                                                         0x800000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_FW_EN_SHFT                                                               23
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_DEST_BMSK                                                 0x400000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_DEST_SHFT                                                       22
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_SRC_BMSK                                                  0x200000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_SRC_SHFT                                                        21
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_PREFETCH_EN_BMSK                                                   0x100000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_PREFETCH_EN_SHFT                                                         20
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IDX_UPD_EN_BMSK                                                     0x80000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IDX_UPD_EN_SHFT                                                          19
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_BMSK                                          0x40000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_SHFT                                               18
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_BMSK                                          0x20000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SHFT                                               17
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_HOST_MSI_EN_BMSK                                                    0x10000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_HOST_MSI_EN_SHFT                                                         16
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_BMSK                                                 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_SHFT                                                      0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR                                                             (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x1c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_RMSK                                                                    0xf
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_DST_AXI_MAX_LEN_BMSK                                                    0xc
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_DST_AXI_MAX_LEN_SHFT                                                      2
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_SRC_AXI_MAX_LEN_BMSK                                                    0x3
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_SRC_AXI_MAX_LEN_SHFT                                                      0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR                                                               (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x20)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_RMSK                                                                      0xf
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_STATUS_BMSK                                                          0x8
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_STATUS_SHFT                                                            3
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_DST_FLUSH_BMSK                                                            0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_DST_FLUSH_SHFT                                                              2
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_SRC_FLUSH_BMSK                                                            0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_SRC_FLUSH_SHFT                                                              1
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_BMSK                                                                 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_SHFT                                                                   0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR                                                            (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x24)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_RMSK                                                                  0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_TIMER_BATCH_BMSK                                                  0x40
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_TIMER_BATCH_SHFT                                                     6
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_TIMER_BATCH_BMSK                                                  0x20
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_TIMER_BATCH_SHFT                                                     5
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_LOW_WATERMARK_BMSK                                           0x10
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_LOW_WATERMARK_SHFT                                              4
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_HIGH_WATERMARK_BMSK                                           0x8
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_HIGH_WATERMARK_SHFT                                             3
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_LOW_WATERMARK_BMSK                                            0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_LOW_WATERMARK_SHFT                                              2
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_HIGH_WATERMARK_BMSK                                           0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_HIGH_WATERMARK_SHFT                                             1
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_COPY_COMPLETE_BMSK                                                     0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_COPY_COMPLETE_SHFT                                                       0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR                                                            (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x28)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_RMSK                                                                  0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_TIMER_BATCH_BMSK                                                  0x40
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_TIMER_BATCH_SHFT                                                     6
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_TIMER_BATCH_BMSK                                                  0x20
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_TIMER_BATCH_SHFT                                                     5
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_LOW_WATERMARK_BMSK                                           0x10
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_LOW_WATERMARK_SHFT                                              4
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_HIGH_WATERMARK_BMSK                                           0x8
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_HIGH_WATERMARK_SHFT                                             3
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_LOW_WATERMARK_BMSK                                            0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_LOW_WATERMARK_SHFT                                              2
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_HIGH_WATERMARK_BMSK                                           0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_HIGH_WATERMARK_SHFT                                             1
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_COPY_COMPLETE_BMSK                                                     0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_COPY_COMPLETE_SHFT                                                       0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR                                                              (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x2c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_RMSK                                                                    0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_TIMER_BATCH_BMSK                                                    0x40
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_TIMER_BATCH_SHFT                                                       6
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_TIMER_BATCH_BMSK                                                    0x20
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_TIMER_BATCH_SHFT                                                       5
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_LOW_WATERMARK_BMSK                                             0x10
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_LOW_WATERMARK_SHFT                                                4
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_HIGH_WATERMARK_BMSK                                             0x8
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_HIGH_WATERMARK_SHFT                                               3
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_LOW_WATERMARK_BMSK                                              0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_LOW_WATERMARK_SHFT                                                2
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_HIGH_WATERMARK_BMSK                                             0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_HIGH_WATERMARK_SHFT                                               1
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_COPY_COMPLETE_BMSK                                                       0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_COPY_COMPLETE_SHFT                                                         0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR                                                              (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x30)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_RMSK                                                                    0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_TIMER_BATCH_BMSK                                                    0x40
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_TIMER_BATCH_SHFT                                                       6
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_TIMER_BATCH_BMSK                                                    0x20
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_TIMER_BATCH_SHFT                                                       5
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_LOW_WATERMARK_BMSK                                             0x10
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_LOW_WATERMARK_SHFT                                                4
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_HIGH_WATERMARK_BMSK                                             0x8
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_HIGH_WATERMARK_SHFT                                               3
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_LOW_WATERMARK_BMSK                                              0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_LOW_WATERMARK_SHFT                                                2
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_HIGH_WATERMARK_BMSK                                             0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_HIGH_WATERMARK_SHFT                                               1
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_COPY_COMPLETE_BMSK                                                       0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_COPY_COMPLETE_SHFT                                                         0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR                                                              (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x34)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_RMSK                                                                 0xfffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_PARSER_INT_BMSK                                                      0xfc000
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_PARSER_INT_SHFT                                                           14
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_RD_BMSK                                                0x2000
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_RD_SHFT                                                    13
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_WR_BMSK                                                0x1000
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_WR_SHFT                                                    12
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_RO_WR_BMSK                                                         0x800
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_RO_WR_SHFT                                                            11
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_TIMEOUT_ERR_BMSK                                                   0x400
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_TIMEOUT_ERR_SHFT                                                      10
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_ERR_BMSK                                                           0x200
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_ERR_SHFT                                                               9
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_LEN_ERR_BMSK                                                       0x100
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_LEN_ERR_SHFT                                                           8
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_MAX_LEN_VIO_BMSK                                                    0x80
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_MAX_LEN_VIO_SHFT                                                       7
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_OVERFLOW_BMSK                                                  0x40
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_OVERFLOW_SHFT                                                     6
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_OVERFLOW_BMSK                                                  0x20
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_OVERFLOW_SHFT                                                     5
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_LOW_WATERMARK_BMSK                                             0x10
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_LOW_WATERMARK_SHFT                                                4
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_HIGH_WATERMARK_BMSK                                             0x8
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_HIGH_WATERMARK_SHFT                                               3
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_LOW_WATERMARK_BMSK                                              0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_LOW_WATERMARK_SHFT                                                2
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_HIGH_WATERMARK_BMSK                                             0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_HIGH_WATERMARK_SHFT                                               1
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_COPY_COMPLETE_BMSK                                                       0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_COPY_COMPLETE_SHFT                                                         0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR                                                              (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x38)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_RMSK                                                                 0xfffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_PARSER_INT_BMSK                                                      0xfc000
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_PARSER_INT_SHFT                                                           14
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_RD_BMSK                                                0x2000
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_RD_SHFT                                                    13
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_WR_BMSK                                                0x1000
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_WR_SHFT                                                    12
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_RO_WR_BMSK                                                   0x800
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_RO_WR_SHFT                                                      11
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_TIMEOUT_ERR_BMSK                                                   0x400
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_TIMEOUT_ERR_SHFT                                                      10
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_BUS_ERR_BMSK                                                       0x200
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_BUS_ERR_SHFT                                                           9
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_LEN_ERR_BMSK                                                       0x100
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_LEN_ERR_SHFT                                                           8
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_MAX_LEN_VIO_BMSK                                                    0x80
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_MAX_LEN_VIO_SHFT                                                       7
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_OVERFLOW_BMSK                                                  0x40
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_OVERFLOW_SHFT                                                     6
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_OVERFLOW_BMSK                                                  0x20
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_OVERFLOW_SHFT                                                     5
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_LOW_WATERMARK_BMSK                                             0x10
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_LOW_WATERMARK_SHFT                                                4
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_HIGH_WATERMARK_BMSK                                             0x8
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_HIGH_WATERMARK_SHFT                                               3
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_LOW_WATERMARK_BMSK                                              0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_LOW_WATERMARK_SHFT                                                2
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_HIGH_WATERMARK_BMSK                                             0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_HIGH_WATERMARK_SHFT                                               1
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_COPY_COMPLETE_BMSK                                                       0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_COPY_COMPLETE_SHFT                                                         0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR                                                         (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x3c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_RMSK                                                             0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_SRC_WR_INDEX_BMSK                                                0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_SRC_WR_INDEX_SHFT                                                     0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR                                                         (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x40)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_RMSK                                                             0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_DST_WR_INDEX_BMSK                                                0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_DST_WR_INDEX_SHFT                                                     0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR                                                         (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x44)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_RMSK                                                             0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_CURRENT_SRRI_BMSK                                                0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_CURRENT_SRRI_SHFT                                                     0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR                                                         (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x48)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_RMSK                                                             0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_CURRENT_DRRI_BMSK                                                0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_CURRENT_DRRI_SHFT                                                     0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR                                                        (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x4c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_RMSK                                                        0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_BMSK                             0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_SHFT                                     16
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_BMSK                               0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_SHFT                                    0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR                                                        (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x50)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_RMSK                                                        0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_BMSK                            0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_SHFT                                    16
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_BMSK                               0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_SHFT                                    0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR                                                  (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x54)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_RMSK                                                         0x7
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_BMSK                                    0x4
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_SHFT                                      2
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_BMSK                                    0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_SHFT                                      1
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_PRIORITY_BMSK                                             0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_PRIORITY_SHFT                                               0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR                                                    (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x58)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_RMSK                                                    0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK                                       0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT                                                0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR                                                   (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x5c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_RMSK                                                         0xff
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK                                           0xff
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT                                              0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR                                                        (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x60)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_RMSK                                                        0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_MSI_DATA_BMSK                                               0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_MSI_DATA_SHFT                                                        0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR                                                      (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x64)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_RMSK                                                          0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_BMSK                                   0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_SHFT                                        0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR                                                  (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x68)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_RMSK                                                         0x3
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_BMSK                                       0x2
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_SHFT                                         1
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_BMSK                           0x1
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_SHFT                             0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR                                                          (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x6c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_RMSK                                                          0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_STATUS_BMSK                                                   0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_STATUS_SHFT                                                           16
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_LIMIT_BMSK                                                        0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_LIMIT_SHFT                                                             0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR                                                           (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x70)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_RMSK                                                           0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_VALUE_BMSK                                                     0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_VALUE_SHFT                                                              0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR                                         (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x74)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_RMSK                                         0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                       16
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                               15
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                          0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR                                        (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x78)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_RMSK                                        0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  16
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                      15
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR                                         (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x7c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_RMSK                                         0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                       16
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                               15
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                          0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR                                        (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x80)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_RMSK                                        0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  16
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                      15
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR                                                  (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x84)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_RMSK                                                  0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK                                     0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT                                              0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR                                                 (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x88)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_RMSK                                                       0xff
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK                                         0xff
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT                                            0
+
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR                                                      (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE      + 0x8c)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_RMSK                                                      0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_MSI_DATA_BMSK                                             0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_MSI_DATA_SHFT                                                      0
+
+#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE                                                         (HOST_SOC_WFSS_CE_REG_TOP_BASE      + 0x00001000)
+#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE_SIZE                                                    0x1000
+#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE_USED                                                    0x8c
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR                                                            (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x0)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_RMSK                                                            0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_BASE_ADDR_LOW_BMSK                                              0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_BASE_ADDR_LOW_SHFT                                                       0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR                                                           (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x4)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_RMSK                                                                 0xff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_BASE_ADDR_HIGH_BMSK                                                  0xff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_BASE_ADDR_HIGH_SHFT                                                     0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR                                                              (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x8)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_RMSK                                                              0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_START_OFFSET_BMSK                                                 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_START_OFFSET_SHFT                                                         16
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_SIZE_BMSK                                                             0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_SIZE_SHFT                                                                  0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR                                                            (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0xc)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_RMSK                                                            0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_BASE_ADDR_LOW_BMSK                                              0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_BASE_ADDR_LOW_SHFT                                                       0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR                                                           (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x10)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_RMSK                                                                0x3ff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_DESC_SKIP_DWORD_BMSK                                                0x300
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_DESC_SKIP_DWORD_SHFT                                                    8
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_BASE_ADDR_HIGH_BMSK                                                  0xff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_BASE_ADDR_HIGH_SHFT                                                     0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR                                                              (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x14)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_RMSK                                                              0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_START_OFFSET_BMSK                                                 0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_START_OFFSET_SHFT                                                         16
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_SIZE_BMSK                                                             0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_SIZE_SHFT                                                                  0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR                                                             (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x18)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_RMSK                                                              0x1ffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_TARGET_MSI_EN_BMSK                                                0x1000000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_TARGET_MSI_EN_SHFT                                                       24
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_FW_EN_BMSK                                                         0x800000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_FW_EN_SHFT                                                               23
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_DEST_BMSK                                                 0x400000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_DEST_SHFT                                                       22
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_SRC_BMSK                                                  0x200000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_SRC_SHFT                                                        21
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_PREFETCH_EN_BMSK                                                   0x100000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_PREFETCH_EN_SHFT                                                         20
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IDX_UPD_EN_BMSK                                                     0x80000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IDX_UPD_EN_SHFT                                                          19
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DST_RING_BYTE_SWAP_EN_BMSK                                          0x40000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DST_RING_BYTE_SWAP_EN_SHFT                                               18
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_BMSK                                          0x20000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SHFT                                               17
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_HOST_MSI_EN_BMSK                                                    0x10000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_HOST_MSI_EN_SHFT                                                         16
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DEST_MAX_LENGTH_BMSK                                                 0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DEST_MAX_LENGTH_SHFT                                                      0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR                                                             (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x1c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_RMSK                                                                    0xf
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_DST_AXI_MAX_LEN_BMSK                                                    0xc
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_DST_AXI_MAX_LEN_SHFT                                                      2
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_SRC_AXI_MAX_LEN_BMSK                                                    0x3
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_SRC_AXI_MAX_LEN_SHFT                                                      0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR                                                               (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x20)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_RMSK                                                                      0xf
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_STATUS_BMSK                                                          0x8
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_STATUS_SHFT                                                            3
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_DST_FLUSH_BMSK                                                            0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_DST_FLUSH_SHFT                                                              2
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_SRC_FLUSH_BMSK                                                            0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_SRC_FLUSH_SHFT                                                              1
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_BMSK                                                                 0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_SHFT                                                                   0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR                                                            (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x24)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_RMSK                                                                  0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_TIMER_BATCH_BMSK                                                  0x40
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_TIMER_BATCH_SHFT                                                     6
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_TIMER_BATCH_BMSK                                                  0x20
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_TIMER_BATCH_SHFT                                                     5
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_LOW_WATERMARK_BMSK                                           0x10
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_LOW_WATERMARK_SHFT                                              4
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_HIGH_WATERMARK_BMSK                                           0x8
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_HIGH_WATERMARK_SHFT                                             3
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_LOW_WATERMARK_BMSK                                            0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_LOW_WATERMARK_SHFT                                              2
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_HIGH_WATERMARK_BMSK                                           0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_HIGH_WATERMARK_SHFT                                             1
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_COPY_COMPLETE_BMSK                                                     0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_COPY_COMPLETE_SHFT                                                       0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR                                                            (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x28)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_RMSK                                                                  0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_TIMER_BATCH_BMSK                                                  0x40
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_TIMER_BATCH_SHFT                                                     6
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_TIMER_BATCH_BMSK                                                  0x20
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_TIMER_BATCH_SHFT                                                     5
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_LOW_WATERMARK_BMSK                                           0x10
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_LOW_WATERMARK_SHFT                                              4
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_HIGH_WATERMARK_BMSK                                           0x8
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_HIGH_WATERMARK_SHFT                                             3
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_LOW_WATERMARK_BMSK                                            0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_LOW_WATERMARK_SHFT                                              2
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_HIGH_WATERMARK_BMSK                                           0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_HIGH_WATERMARK_SHFT                                             1
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_COPY_COMPLETE_BMSK                                                     0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_COPY_COMPLETE_SHFT                                                       0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR                                                              (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x2c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_RMSK                                                                    0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_TIMER_BATCH_BMSK                                                    0x40
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_TIMER_BATCH_SHFT                                                       6
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_TIMER_BATCH_BMSK                                                    0x20
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_TIMER_BATCH_SHFT                                                       5
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_LOW_WATERMARK_BMSK                                             0x10
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_LOW_WATERMARK_SHFT                                                4
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_HIGH_WATERMARK_BMSK                                             0x8
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_HIGH_WATERMARK_SHFT                                               3
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_LOW_WATERMARK_BMSK                                              0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_LOW_WATERMARK_SHFT                                                2
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_HIGH_WATERMARK_BMSK                                             0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_HIGH_WATERMARK_SHFT                                               1
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_COPY_COMPLETE_BMSK                                                       0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_COPY_COMPLETE_SHFT                                                         0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR                                                              (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x30)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_RMSK                                                                    0x7f
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_TIMER_BATCH_BMSK                                                    0x40
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_TIMER_BATCH_SHFT                                                       6
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_TIMER_BATCH_BMSK                                                    0x20
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_TIMER_BATCH_SHFT                                                       5
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_LOW_WATERMARK_BMSK                                             0x10
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_LOW_WATERMARK_SHFT                                                4
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_HIGH_WATERMARK_BMSK                                             0x8
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_HIGH_WATERMARK_SHFT                                               3
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_LOW_WATERMARK_BMSK                                              0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_LOW_WATERMARK_SHFT                                                2
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_HIGH_WATERMARK_BMSK                                             0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_HIGH_WATERMARK_SHFT                                               1
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_COPY_COMPLETE_BMSK                                                       0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_COPY_COMPLETE_SHFT                                                         0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR                                                              (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x34)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_RMSK                                                                 0xfffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_PARSER_INT_BMSK                                                      0xfc000
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_PARSER_INT_SHFT                                                           14
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_RD_BMSK                                                0x2000
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_RD_SHFT                                                    13
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_WR_BMSK                                                0x1000
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_WR_SHFT                                                    12
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_RO_WR_BMSK                                                         0x800
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_RO_WR_SHFT                                                            11
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_TIMEOUT_ERR_BMSK                                                   0x400
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_TIMEOUT_ERR_SHFT                                                      10
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_ERR_BMSK                                                           0x200
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_ERR_SHFT                                                               9
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_LEN_ERR_BMSK                                                       0x100
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_LEN_ERR_SHFT                                                           8
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_MAX_LEN_VIO_BMSK                                                    0x80
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_MAX_LEN_VIO_SHFT                                                       7
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_OVERFLOW_BMSK                                                  0x40
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_OVERFLOW_SHFT                                                     6
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_OVERFLOW_BMSK                                                  0x20
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_OVERFLOW_SHFT                                                     5
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_LOW_WATERMARK_BMSK                                             0x10
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_LOW_WATERMARK_SHFT                                                4
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_HIGH_WATERMARK_BMSK                                             0x8
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_HIGH_WATERMARK_SHFT                                               3
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_LOW_WATERMARK_BMSK                                              0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_LOW_WATERMARK_SHFT                                                2
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_HIGH_WATERMARK_BMSK                                             0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_HIGH_WATERMARK_SHFT                                               1
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_COPY_COMPLETE_BMSK                                                       0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_COPY_COMPLETE_SHFT                                                         0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR                                                              (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x38)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_RMSK                                                                 0xfffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_PARSER_INT_BMSK                                                      0xfc000
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_PARSER_INT_SHFT                                                           14
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_RD_BMSK                                                0x2000
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_RD_SHFT                                                    13
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_WR_BMSK                                                0x1000
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_WR_SHFT                                                    12
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_RO_WR_BMSK                                                   0x800
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_RO_WR_SHFT                                                      11
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_TIMEOUT_ERR_BMSK                                                   0x400
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_TIMEOUT_ERR_SHFT                                                      10
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_BUS_ERR_BMSK                                                       0x200
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_BUS_ERR_SHFT                                                           9
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_LEN_ERR_BMSK                                                       0x100
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_LEN_ERR_SHFT                                                           8
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_MAX_LEN_VIO_BMSK                                                    0x80
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_MAX_LEN_VIO_SHFT                                                       7
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_OVERFLOW_BMSK                                                  0x40
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_OVERFLOW_SHFT                                                     6
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_OVERFLOW_BMSK                                                  0x20
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_OVERFLOW_SHFT                                                     5
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_LOW_WATERMARK_BMSK                                             0x10
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_LOW_WATERMARK_SHFT                                                4
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_HIGH_WATERMARK_BMSK                                             0x8
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_HIGH_WATERMARK_SHFT                                               3
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_LOW_WATERMARK_BMSK                                              0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_LOW_WATERMARK_SHFT                                                2
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_HIGH_WATERMARK_BMSK                                             0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_HIGH_WATERMARK_SHFT                                               1
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_COPY_COMPLETE_BMSK                                                       0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_COPY_COMPLETE_SHFT                                                         0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR                                                         (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x3c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_RMSK                                                             0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_SRC_WR_INDEX_BMSK                                                0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_SRC_WR_INDEX_SHFT                                                     0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR                                                         (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x40)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_RMSK                                                             0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_DST_WR_INDEX_BMSK                                                0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_DST_WR_INDEX_SHFT                                                     0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR                                                         (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x44)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_RMSK                                                             0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_CURRENT_SRRI_BMSK                                                0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_CURRENT_SRRI_SHFT                                                     0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR                                                         (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x48)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_RMSK                                                             0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_CURRENT_DRRI_BMSK                                                0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_CURRENT_DRRI_SHFT                                                     0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR                                                        (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x4c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_RMSK                                                        0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_BMSK                             0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_SHFT                                     16
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_BMSK                               0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_SHFT                                    0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR                                                        (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x50)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_RMSK                                                        0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_BMSK                            0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_SHFT                                    16
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_BMSK                               0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_SHFT                                    0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR                                                  (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x54)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_RMSK                                                         0x7
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_BMSK                                    0x4
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_SHFT                                      2
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_BMSK                                    0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_SHFT                                      1
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_PRIORITY_BMSK                                             0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_PRIORITY_SHFT                                               0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR                                                    (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x58)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_RMSK                                                    0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK                                       0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT                                                0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR                                                   (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x5c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_RMSK                                                         0xff
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK                                           0xff
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT                                              0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR                                                        (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x60)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_RMSK                                                        0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_MSI_DATA_BMSK                                               0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_MSI_DATA_SHFT                                                        0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR                                                      (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x64)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_RMSK                                                          0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_BMSK                                   0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_SHFT                                        0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR                                                  (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x68)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_RMSK                                                         0x3
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_BMSK                                       0x2
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_SHFT                                         1
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_BMSK                           0x1
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_SHFT                             0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR                                                          (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x6c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_RMSK                                                          0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_STATUS_BMSK                                                   0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_STATUS_SHFT                                                           16
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_LIMIT_BMSK                                                        0xffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_LIMIT_SHFT                                                             0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR                                                           (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x70)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_RMSK                                                           0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_VALUE_BMSK                                                     0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_VALUE_SHFT                                                              0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR                                         (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x74)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_RMSK                                         0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                       16
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                               15
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                          0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR                                        (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x78)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_RMSK                                        0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  16
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                      15
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR                                         (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x7c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_RMSK                                         0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK               0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT                       16
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK                           0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT                               15
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK                     0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT                          0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR                                        (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x80)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_RMSK                                        0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK          0xffff0000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT                  16
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK                  0x8000
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT                      15
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK               0x7fff
+#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT                    0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR                                                  (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x84)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_RMSK                                                  0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK                                     0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT                                              0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR                                                 (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x88)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_RMSK                                                       0xff
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK                                         0xff
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT                                            0
+
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR                                                      (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE      + 0x8c)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_RMSK                                                      0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_MSI_DATA_BMSK                                             0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_MSI_DATA_SHFT                                                      0
+
+#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE                                                  (HOST_SOC_WFSS_CE_REG_TOP_BASE      + 0x00010000)
+#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE_SIZE                                             0x1000
+#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE_USED                                             0x10
+
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR               (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE      + 0x0)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_RMSK                 0xfff000
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_BMSK            0xfff000
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_SHFT                  12
+
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR                       (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE      + 0x4)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_RMSK                       0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_VAL_BMSK                   0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_VAL_SHFT                            0
+
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR                      (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE      + 0x8)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_RMSK                            0xff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_VAL_BMSK                        0xff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_VAL_SHFT                           0
+
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR                    (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE      + 0xc)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_RMSK                    0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_VAL_BMSK                0xffffffff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_VAL_SHFT                         0
+
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR                   (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE      + 0x10)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_RMSK                         0xff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_IN                    \
+                in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_INM(m)            \
+                in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR, m)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_OUT(v)            \
+                out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR,v)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_OUTM(m,v) \
+                out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_IN)
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_VAL_BMSK                     0xff
+#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_VAL_SHFT                        0
+
+#endif

hw/wcn6450/v1/l_sig_a_info.h

@@ -0,0 +1,72 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _L_SIG_A_INFO_H_
+#define _L_SIG_A_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_L_SIG_A_INFO 1
+
+struct l_sig_a_info {
+             uint32_t rate                            :  4,
+                      lsig_reserved                   :  1,
+                      length                          : 12,
+                      parity                          :  1,
+                      tail                            :  6,
+                      pkt_type                        :  4,
+                      captured_implicit_sounding      :  1,
+                      reserved                        :  3;
+};
+
+#define L_SIG_A_INFO_0_RATE_OFFSET                                   0x00000000
+#define L_SIG_A_INFO_0_RATE_LSB                                      0
+#define L_SIG_A_INFO_0_RATE_MASK                                     0x0000000f
+
+#define L_SIG_A_INFO_0_LSIG_RESERVED_OFFSET                          0x00000000
+#define L_SIG_A_INFO_0_LSIG_RESERVED_LSB                             4
+#define L_SIG_A_INFO_0_LSIG_RESERVED_MASK                            0x00000010
+
+#define L_SIG_A_INFO_0_LENGTH_OFFSET                                 0x00000000
+#define L_SIG_A_INFO_0_LENGTH_LSB                                    5
+#define L_SIG_A_INFO_0_LENGTH_MASK                                   0x0001ffe0
+
+#define L_SIG_A_INFO_0_PARITY_OFFSET                                 0x00000000
+#define L_SIG_A_INFO_0_PARITY_LSB                                    17
+#define L_SIG_A_INFO_0_PARITY_MASK                                   0x00020000
+
+#define L_SIG_A_INFO_0_TAIL_OFFSET                                   0x00000000
+#define L_SIG_A_INFO_0_TAIL_LSB                                      18
+#define L_SIG_A_INFO_0_TAIL_MASK                                     0x00fc0000
+
+#define L_SIG_A_INFO_0_PKT_TYPE_OFFSET                               0x00000000
+#define L_SIG_A_INFO_0_PKT_TYPE_LSB                                  24
+#define L_SIG_A_INFO_0_PKT_TYPE_MASK                                 0x0f000000
+
+#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_OFFSET             0x00000000
+#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_LSB                28
+#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_MASK               0x10000000
+
+#define L_SIG_A_INFO_0_RESERVED_OFFSET                               0x00000000
+#define L_SIG_A_INFO_0_RESERVED_LSB                                  29
+#define L_SIG_A_INFO_0_RESERVED_MASK                                 0xe0000000
+
+#endif

hw/wcn6450/v1/l_sig_b_info.h

@@ -0,0 +1,47 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _L_SIG_B_INFO_H_
+#define _L_SIG_B_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_L_SIG_B_INFO 1
+
+struct l_sig_b_info {
+             uint32_t rate                            :  4,
+                      length                          : 12,
+                      reserved                        : 16;
+};
+
+#define L_SIG_B_INFO_0_RATE_OFFSET                                   0x00000000
+#define L_SIG_B_INFO_0_RATE_LSB                                      0
+#define L_SIG_B_INFO_0_RATE_MASK                                     0x0000000f
+
+#define L_SIG_B_INFO_0_LENGTH_OFFSET                                 0x00000000
+#define L_SIG_B_INFO_0_LENGTH_LSB                                    4
+#define L_SIG_B_INFO_0_LENGTH_MASK                                   0x0000fff0
+
+#define L_SIG_B_INFO_0_RESERVED_OFFSET                               0x00000000
+#define L_SIG_B_INFO_0_RESERVED_LSB                                  16
+#define L_SIG_B_INFO_0_RESERVED_MASK                                 0xffff0000
+
+#endif

hw/wcn6450/v1/macrx_abort_request_info.h

@@ -0,0 +1,42 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _MACRX_ABORT_REQUEST_INFO_H_
+#define _MACRX_ABORT_REQUEST_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1
+
+struct macrx_abort_request_info {
+             uint16_t macrx_abort_reason              :  8,
+                      reserved_0                      :  8;
+};
+
+#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_OFFSET         0x00000000
+#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_LSB            0
+#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_MASK           0x000000ff
+
+#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET                 0x00000000
+#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB                    8
+#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK                   0x0000ff00
+
+#endif

hw/wcn6450/v1/msmhwiobase.h

@@ -0,0 +1,27 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __MSMHWIOBASE_H__
+#define __MSMHWIOBASE_H__
+
+#define HOST_SOC_WFSS_CE_REG_TOP_BASE                                0x1b80000
+#define HOST_SOC_WFSS_CE_REG_TOP_BASE_SIZE                          0x0001c000
+#define HOST_SOC_WFSS_CE_REG_TOP_BASE_PHYS                          0x01b80000
+
+#endif

hw/wcn6450/v1/phyrx_abort_request_info.h

@@ -0,0 +1,57 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
+#define _PHYRX_ABORT_REQUEST_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
+
+struct phyrx_abort_request_info {
+             uint32_t phyrx_abort_reason              :  8,
+                      phy_enters_nap_state            :  1,
+                      phy_enters_defer_state          :  1,
+                      reserved_0                      :  6,
+                      receive_duration                : 16;
+};
+
+#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_OFFSET         0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_LSB            0
+#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_MASK           0x000000ff
+
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_OFFSET       0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_LSB          8
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_MASK         0x00000100
+
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_OFFSET     0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_LSB        9
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_MASK       0x00000200
+
+#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET                 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB                    10
+#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK                   0x0000fc00
+
+#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_OFFSET           0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_LSB              16
+#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_MASK             0xffff0000
+
+#endif

hw/wcn6450/v1/phyrx_common_user_info.h

@@ -0,0 +1,42 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_COMMON_USER_INFO_H_
+#define _PHYRX_COMMON_USER_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 1
+
+struct phyrx_common_user_info {
+             uint32_t receive_duration                : 16,
+                      reserved_0a                     : 16;
+};
+
+#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_OFFSET             0x00000000
+#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_LSB                0
+#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_MASK               0x0000ffff
+
+#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_OFFSET                  0x00000000
+#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_LSB                     16
+#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_MASK                    0xffff0000
+
+#endif

hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h

@@ -0,0 +1,119 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_HE_SIG_A_MU_DL_H_
+#define _PHYRX_HE_SIG_A_MU_DL_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_a_mu_dl_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2
+
+struct phyrx_he_sig_a_mu_dl {
+    struct            he_sig_a_mu_dl_info                       phyrx_he_sig_a_mu_dl_info_details;
+};
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000
+
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000
+
+#endif

hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h

@@ -0,0 +1,79 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_HE_SIG_A_MU_UL_H_
+#define _PHYRX_HE_SIG_A_MU_UL_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_a_mu_ul_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
+
+struct phyrx_he_sig_a_mu_ul {
+    struct            he_sig_a_mu_ul_info                       phyrx_he_sig_a_mu_ul_info_details;
+};
+
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
+
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80
+
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000
+
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000
+
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
+
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80
+
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000
+
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000
+
+#endif

hw/wcn6450/v1/phyrx_he_sig_a_su.h

@@ -0,0 +1,139 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_HE_SIG_A_SU_H_
+#define _PHYRX_HE_SIG_A_SU_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_a_su_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2
+
+struct phyrx_he_sig_a_su {
+    struct            he_sig_a_su_info                       phyrx_he_sig_a_su_info_details;
+};
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB   7
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK  0x00000080
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB  23
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000
+
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB  9
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB  10
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB   16
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK  0x000f0000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB  20
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x78000000
+
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 31
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x80000000
+
+#endif

hw/wcn6450/v1/phyrx_he_sig_b1_mu.h

@@ -0,0 +1,43 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_HE_SIG_B1_MU_H_
+#define _PHYRX_HE_SIG_B1_MU_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_b1_mu_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 1
+
+struct phyrx_he_sig_b1_mu {
+    struct            he_sig_b1_mu_info                       phyrx_he_sig_b1_mu_info_details;
+};
+
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff
+
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0xffffff00
+
+#endif

hw/wcn6450/v1/phyrx_he_sig_b2_mu.h

@@ -0,0 +1,63 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_HE_SIG_B2_MU_H_
+#define _PHYRX_HE_SIG_B2_MU_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_b2_mu_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 1
+
+struct phyrx_he_sig_b2_mu {
+    struct            he_sig_b2_mu_info                       phyrx_he_sig_b2_mu_info_details;
+};
+
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff
+
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800
+
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000
+
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000
+
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000
+
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x1fe00000
+
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 29
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0xe0000000
+
+#endif

hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h

@@ -0,0 +1,63 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_
+#define _PHYRX_HE_SIG_B2_OFDMA_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_b2_ofdma_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 1
+
+struct phyrx_he_sig_b2_ofdma {
+    struct            he_sig_b2_ofdma_info                       phyrx_he_sig_b2_ofdma_info_details;
+};
+
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff
+
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800
+
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000
+
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000
+
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000
+
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000
+
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0xffe00000
+
+#endif

hw/wcn6450/v1/phyrx_ht_sig.h

@@ -0,0 +1,95 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_HT_SIG_H_
+#define _PHYRX_HT_SIG_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "ht_sig_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_HT_SIG 2
+
+struct phyrx_ht_sig {
+    struct            ht_sig_info                       phyrx_ht_sig_info_details;
+};
+
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET          0x00000000
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB             0
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK            0x0000007f
+
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET          0x00000000
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB             7
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK            0x00000080
+
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET       0x00000000
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB          8
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK         0x00ffff00
+
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET   0x00000000
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB      24
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK     0xff000000
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET    0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB       0
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK      0x00000001
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB    1
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK   0x00000002
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET  0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB     2
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK    0x00000004
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET  0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB     3
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK    0x00000008
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET         0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB            4
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK           0x00000030
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET   0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB      6
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK     0x00000040
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET     0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB        7
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK       0x00000080
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB  8
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET          0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB             10
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK            0x0003fc00
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET  0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB     18
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK    0x00fc0000
+
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET   0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB      24
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK     0xff000000
+
+#endif

hw/wcn6450/v1/phyrx_l_sig_a.h

@@ -0,0 +1,67 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_L_SIG_A_H_
+#define _PHYRX_L_SIG_A_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "l_sig_a_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_L_SIG_A 1
+
+struct phyrx_l_sig_a {
+    struct            l_sig_a_info                       phyrx_l_sig_a_info_details;
+};
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET       0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB          0
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK         0x0000000f
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET     0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB        5
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK       0x0001ffe0
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET     0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB        17
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK       0x00020000
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET       0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB          18
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK         0x00fc0000
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET   0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB      24
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK     0x0f000000
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
+
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET   0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB      29
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK     0xe0000000
+
+#endif

hw/wcn6450/v1/phyrx_l_sig_b.h

@@ -0,0 +1,47 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_L_SIG_B_H_
+#define _PHYRX_L_SIG_B_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "l_sig_b_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_L_SIG_B 1
+
+struct phyrx_l_sig_b {
+    struct            l_sig_b_info                       phyrx_l_sig_b_info_details;
+};
+
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET       0x00000000
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB          0
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK         0x0000000f
+
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET     0x00000000
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB        4
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK       0x0000fff0
+
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET   0x00000000
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB      16
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK     0xffff0000
+
+#endif

hw/wcn6450/v1/phyrx_other_receive_info_ru_details.h

@@ -0,0 +1,47 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
+#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 3
+
+struct phyrx_other_receive_info_ru_details {
+             uint32_t ru_details_channel_0            : 32;
+             uint32_t ru_details_channel_1            : 32;
+             uint32_t spare                           : 32;
+};
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_OFFSET 0x00000000
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_MASK 0xffffffff
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_OFFSET 0x00000004
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_MASK 0xffffffff
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_OFFSET           0x00000008
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_LSB              0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_MASK             0xffffffff
+
+#endif

hw/wcn6450/v1/phyrx_pkt_end.h

@@ -0,0 +1,503 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_PKT_END_H_
+#define _PHYRX_PKT_END_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "phyrx_pkt_end_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_PKT_END 33
+
+struct phyrx_pkt_end {
+    struct            phyrx_pkt_end_info                       rx_pkt_end_details;
+};
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB   1
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK  0x00000002
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET  0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB     2
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK    0x00000004
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET    0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB       3
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK      0x00000008
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_LSB 4
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET        0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_LSB           6
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_MASK          0x00000fc0
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_LSB   12
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_MASK  0x00001000
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_LSB 13
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_OFFSET  0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_LSB     20
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_MASK    0x07f00000
+
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET        0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_LSB           27
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_MASK          0xf8000000
+
+#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
+#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0
+#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
+#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
+#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
+#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0
+#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
+#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
+#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff
+
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000
+
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff
+
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000
+
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000
+
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000
+
+#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024
+#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0
+#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff
+
+#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028
+#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0
+#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff
+
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff
+
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000
+
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000
+
+#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030
+#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
+#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff
+
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000
+
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000
+
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000
+
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000
+
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
+
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000
+
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000007c
+#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB   0
+#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK  0xffffffff
+
+#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x00000080
+#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB  0
+#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff
+
+#endif

hw/wcn6450/v1/phyrx_pkt_end_info.h

@@ -0,0 +1,524 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_PKT_END_INFO_H_
+#define _PHYRX_PKT_END_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_location_info.h"
+#include "rx_timing_offset_info.h"
+#include "receive_rssi_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33
+
+struct phyrx_pkt_end_info {
+             uint32_t __reserved_g_0001                :  1,
+                      location_info_valid             :  1,
+                      timing_info_valid               :  1,
+                      rssi_info_valid                 :  1,
+                      rx_frame_correction_needed      :  1,
+                      frameless_frame_received        :  1,
+                      reserved_0a                     :  6,
+                      dl_ofdma_info_valid             :  1,
+                      dl_ofdma_ru_start_index         :  7,
+                      dl_ofdma_ru_width               :  7,
+                      reserved_0b                     :  5;
+             uint32_t phy_timestamp_1_lower_32        : 32;
+             uint32_t phy_timestamp_1_upper_32        : 32;
+             uint32_t phy_timestamp_2_lower_32        : 32;
+             uint32_t phy_timestamp_2_upper_32        : 32;
+    struct            rx_location_info                       rx_location_info_details;
+    struct            rx_timing_offset_info                       rx_timing_offset_info_details;
+    struct            receive_rssi_info                       post_rssi_info_details;
+             uint32_t phy_sw_status_31_0              : 32;
+             uint32_t phy_sw_status_63_32             : 32;
+};
+
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET              0x00000000
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB                 1
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK                0x00000002
+
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET                0x00000000
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB                   2
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK                  0x00000004
+
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET                  0x00000000
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB                     3
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK                    0x00000008
+
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET       0x00000000
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB          4
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK         0x00000010
+
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET         0x00000000
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB            5
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK           0x00000020
+
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET                      0x00000000
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB                         6
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK                        0x00000fc0
+
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET              0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB                 12
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK                0x00001000
+
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET          0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB             13
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK            0x000fe000
+
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET                0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB                   20
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK                  0x07f00000
+
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET                      0x00000000
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB                         27
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK                        0xf8000000
+
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET         0x00000004
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB            0
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK           0xffffffff
+
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET         0x00000008
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB            0
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK           0xffffffff
+
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET         0x0000000c
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB            0
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK           0xffffffff
+
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET         0x00000010
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB            0
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK           0xffffffff
+
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff
+
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000
+
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff
+
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000
+
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000
+
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000
+
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff
+
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000
+
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff
+
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000
+
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000
+
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000
+
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000
+
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
+
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000
+
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET              0x0000007c
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB                 0
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK                0xffffffff
+
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET             0x00000080
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB                0
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK               0xffffffff
+
+#endif

hw/wcn6450/v1/phyrx_rssi_legacy.h

@@ -0,0 +1,628 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_RSSI_LEGACY_H_
+#define _PHYRX_RSSI_LEGACY_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "receive_rssi_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 37
+
+struct phyrx_rssi_legacy {
+             uint32_t reception_type                  :  4,
+                      rx_chain_mask_type              :  1,
+                      reserved_0                      :  1,
+                      receive_bandwidth               :  2,
+                      rx_chain_mask                   :  8,
+                      phy_ppdu_id                     : 16;
+             uint32_t sw_phy_meta_data                : 32;
+             uint32_t ppdu_start_timestamp            : 32;
+    struct            receive_rssi_info                       pre_rssi_info_details;
+    struct            receive_rssi_info                       preamble_rssi_info_details;
+             uint32_t pre_rssi_comb                   :  8,
+                      rssi_comb                       :  8,
+                      normalized_pre_rssi_comb        :  8,
+                      normalized_rssi_comb            :  8;
+             uint32_t rssi_comb_ppdu                  :  8,
+                      rssi_db_to_dbm_offset           :  8,
+                      rssi_for_spatial_reuse          :  8,
+                      rssi_for_trigger_resp           :  8;
+};
+
+#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_OFFSET                    0x00000000
+#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_LSB                       0
+#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_MASK                      0x0000000f
+
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_OFFSET                0x00000000
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_LSB                   4
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_MASK                  0x00000010
+
+#define PHYRX_RSSI_LEGACY_0_RESERVED_0_OFFSET                        0x00000000
+#define PHYRX_RSSI_LEGACY_0_RESERVED_0_LSB                           5
+#define PHYRX_RSSI_LEGACY_0_RESERVED_0_MASK                          0x00000020
+
+#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_OFFSET                 0x00000000
+#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_LSB                    6
+#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_MASK                   0x000000c0
+
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_OFFSET                     0x00000000
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_LSB                        8
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_MASK                       0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_OFFSET                       0x00000000
+#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_LSB                          16
+#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_MASK                         0xffff0000
+
+#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_OFFSET                  0x00000004
+#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_LSB                     0
+#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_MASK                    0xffffffff
+
+#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_OFFSET              0x00000008
+#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_LSB                 0
+#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_MASK                0xffffffff
+
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000010
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000010
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000010
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000010
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000014
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000014
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000014
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000014
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000018
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000018
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000018
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000018
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000001c
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000001c
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000001c
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000001c
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_OFFSET                    0x0000008c
+#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_LSB                       0
+#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_MASK                      0x000000ff
+
+#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_OFFSET                        0x0000008c
+#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_LSB                           8
+#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_MASK                          0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_OFFSET         0x0000008c
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_LSB            16
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_MASK           0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_OFFSET             0x0000008c
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_LSB                24
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_MASK               0xff000000
+
+#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_OFFSET                   0x00000090
+#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_LSB                      0
+#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_MASK                     0x000000ff
+
+#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_OFFSET            0x00000090
+#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_LSB               8
+#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_MASK              0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_OFFSET           0x00000090
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_LSB              16
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_MASK             0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_OFFSET            0x00000090
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_LSB               24
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_MASK              0xff000000
+
+#endif

hw/wcn6450/v1/phyrx_user_info.h

@@ -0,0 +1,95 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_USER_INFO_H_
+#define _PHYRX_USER_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "receive_user_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_USER_INFO 3
+
+struct phyrx_user_info {
+    struct            receive_user_info                       receive_user_info_details;
+};
+
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB  0
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB    16
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK   0x00ff0000
+
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET  0x00000000
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB     24
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK    0x0f000000
+
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET      0x00000000
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_LSB         28
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_MASK        0x10000000
+
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29
+#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000
+
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET  0x00000004
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB     0
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK    0x0000000f
+
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET       0x00000004
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_LSB          4
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_MASK         0x00000030
+
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 6
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000c0
+
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00
+
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_OFFSET 0x00000004
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_LSB 16
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_MASK 0x00ff0000
+
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_OFFSET 0x00000004
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_LSB 24
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_MASK 0x7f000000
+
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_LSB 31
+#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_MASK 0x80000000
+
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET      0x00000008
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_LSB         0
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_MASK        0x00000001
+
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_OFFSET  0x00000008
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_LSB     1
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_MASK    0x000000fe
+
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB  8
+#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0xffffff00
+
+#endif

hw/wcn6450/v1/phyrx_vht_sig_a.h

@@ -0,0 +1,103 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _PHYRX_VHT_SIG_A_H_
+#define _PHYRX_VHT_SIG_A_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "vht_sig_a_info.h"
+
+#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2
+
+struct phyrx_vht_sig_a {
+    struct            vht_sig_a_info                       phyrx_vht_sig_a_info_details;
+};
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET   0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB      3
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK     0x00000008
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB  4
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET  0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB     10
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK    0x003ffc00
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000
+
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET    0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB       4
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK      0x000000f0
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET    0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB       10
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK      0x0003fc00
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET   0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB      18
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK     0x00fc0000
+
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0xff000000
+
+#endif

hw/wcn6450/v1/receive_rssi_info.h

@@ -0,0 +1,352 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RECEIVE_RSSI_INFO_H_
+#define _RECEIVE_RSSI_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16
+
+struct receive_rssi_info {
+             uint32_t rssi_pri20_chain0               :  8,
+                      rssi_ext20_chain0               :  8,
+                      rssi_ext40_low20_chain0         :  8,
+                      rssi_ext40_high20_chain0        :  8;
+             uint32_t rssi_ext80_low20_chain0         :  8,
+                      rssi_ext80_low_high20_chain0    :  8,
+                      rssi_ext80_high_low20_chain0    :  8,
+                      rssi_ext80_high20_chain0        :  8;
+             uint32_t rssi_pri20_chain1               :  8,
+                      rssi_ext20_chain1               :  8,
+                      rssi_ext40_low20_chain1         :  8,
+                      rssi_ext40_high20_chain1        :  8;
+             uint32_t rssi_ext80_low20_chain1         :  8,
+                      rssi_ext80_low_high20_chain1    :  8,
+                      rssi_ext80_high_low20_chain1    :  8,
+                      rssi_ext80_high20_chain1        :  8;
+             uint32_t rssi_pri20_chain2               :  8,
+                      rssi_ext20_chain2               :  8,
+                      rssi_ext40_low20_chain2         :  8,
+                      rssi_ext40_high20_chain2        :  8;
+             uint32_t rssi_ext80_low20_chain2         :  8,
+                      rssi_ext80_low_high20_chain2    :  8,
+                      rssi_ext80_high_low20_chain2    :  8,
+                      rssi_ext80_high20_chain2        :  8;
+             uint32_t rssi_pri20_chain3               :  8,
+                      rssi_ext20_chain3               :  8,
+                      rssi_ext40_low20_chain3         :  8,
+                      rssi_ext40_high20_chain3        :  8;
+             uint32_t rssi_ext80_low20_chain3         :  8,
+                      rssi_ext80_low_high20_chain3    :  8,
+                      rssi_ext80_high_low20_chain3    :  8,
+                      rssi_ext80_high20_chain3        :  8;
+             uint32_t rssi_pri20_chain4               :  8,
+                      rssi_ext20_chain4               :  8,
+                      rssi_ext40_low20_chain4         :  8,
+                      rssi_ext40_high20_chain4        :  8;
+             uint32_t rssi_ext80_low20_chain4         :  8,
+                      rssi_ext80_low_high20_chain4    :  8,
+                      rssi_ext80_high_low20_chain4    :  8,
+                      rssi_ext80_high20_chain4        :  8;
+             uint32_t rssi_pri20_chain5               :  8,
+                      rssi_ext20_chain5               :  8,
+                      rssi_ext40_low20_chain5         :  8,
+                      rssi_ext40_high20_chain5        :  8;
+             uint32_t rssi_ext80_low20_chain5         :  8,
+                      rssi_ext80_low_high20_chain5    :  8,
+                      rssi_ext80_high_low20_chain5    :  8,
+                      rssi_ext80_high20_chain5        :  8;
+             uint32_t rssi_pri20_chain6               :  8,
+                      rssi_ext20_chain6               :  8,
+                      rssi_ext40_low20_chain6         :  8,
+                      rssi_ext40_high20_chain6        :  8;
+             uint32_t rssi_ext80_low20_chain6         :  8,
+                      rssi_ext80_low_high20_chain6    :  8,
+                      rssi_ext80_high_low20_chain6    :  8,
+                      rssi_ext80_high20_chain6        :  8;
+             uint32_t rssi_pri20_chain7               :  8,
+                      rssi_ext20_chain7               :  8,
+                      rssi_ext40_low20_chain7         :  8,
+                      rssi_ext40_high20_chain7        :  8;
+             uint32_t rssi_ext80_low20_chain7         :  8,
+                      rssi_ext80_low_high20_chain7    :  8,
+                      rssi_ext80_high_low20_chain7    :  8,
+                      rssi_ext80_high20_chain7        :  8;
+};
+
+#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_OFFSET                 0x00000000
+#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_LSB                    0
+#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_MASK                   0x000000ff
+
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_OFFSET                 0x00000000
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_LSB                    8
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_MASK                   0x0000ff00
+
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_OFFSET           0x00000000
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_LSB              16
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_MASK             0x00ff0000
+
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_OFFSET          0x00000000
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_LSB             24
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_MASK            0xff000000
+
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_OFFSET           0x00000004
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_LSB              0
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_MASK             0x000000ff
+
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET      0x00000004
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB         8
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK        0x0000ff00
+
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET      0x00000004
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB         16
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK        0x00ff0000
+
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_OFFSET          0x00000004
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_LSB             24
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_MASK            0xff000000
+
+#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_OFFSET                 0x00000008
+#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_LSB                    0
+#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_MASK                   0x000000ff
+
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_OFFSET                 0x00000008
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_LSB                    8
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_MASK                   0x0000ff00
+
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_OFFSET           0x00000008
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_LSB              16
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_MASK             0x00ff0000
+
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_OFFSET          0x00000008
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_LSB             24
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_MASK            0xff000000
+
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_OFFSET           0x0000000c
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_LSB              0
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_MASK             0x000000ff
+
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET      0x0000000c
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB         8
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK        0x0000ff00
+
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET      0x0000000c
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB         16
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK        0x00ff0000
+
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_OFFSET          0x0000000c
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_LSB             24
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_MASK            0xff000000
+
+#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_OFFSET                 0x00000010
+#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_LSB                    0
+#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_MASK                   0x000000ff
+
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_OFFSET                 0x00000010
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_LSB                    8
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_MASK                   0x0000ff00
+
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_OFFSET           0x00000010
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_LSB              16
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_MASK             0x00ff0000
+
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_OFFSET          0x00000010
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_LSB             24
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_MASK            0xff000000
+
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_OFFSET           0x00000014
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_LSB              0
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_MASK             0x000000ff
+
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET      0x00000014
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB         8
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK        0x0000ff00
+
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET      0x00000014
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB         16
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK        0x00ff0000
+
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_OFFSET          0x00000014
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_LSB             24
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_MASK            0xff000000
+
+#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_OFFSET                 0x00000018
+#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_LSB                    0
+#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_MASK                   0x000000ff
+
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_OFFSET                 0x00000018
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_LSB                    8
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_MASK                   0x0000ff00
+
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_OFFSET           0x00000018
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_LSB              16
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_MASK             0x00ff0000
+
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_OFFSET          0x00000018
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_LSB             24
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_MASK            0xff000000
+
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_OFFSET           0x0000001c
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_LSB              0
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_MASK             0x000000ff
+
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET      0x0000001c
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB         8
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK        0x0000ff00
+
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET      0x0000001c
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB         16
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK        0x00ff0000
+
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_OFFSET          0x0000001c
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_LSB             24
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_MASK            0xff000000
+
+#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_OFFSET                 0x00000020
+#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_LSB                    0
+#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_MASK                   0x000000ff
+
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_OFFSET                 0x00000020
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_LSB                    8
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_MASK                   0x0000ff00
+
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_OFFSET           0x00000020
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_LSB              16
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_MASK             0x00ff0000
+
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_OFFSET          0x00000020
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_LSB             24
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_MASK            0xff000000
+
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_OFFSET           0x00000024
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_LSB              0
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_MASK             0x000000ff
+
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET      0x00000024
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB         8
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK        0x0000ff00
+
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET      0x00000024
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB         16
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK        0x00ff0000
+
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_OFFSET          0x00000024
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_LSB             24
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_MASK            0xff000000
+
+#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_OFFSET                0x00000028
+#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_LSB                   0
+#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_MASK                  0x000000ff
+
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_OFFSET                0x00000028
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_LSB                   8
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_MASK                  0x0000ff00
+
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_OFFSET          0x00000028
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_LSB             16
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_MASK            0x00ff0000
+
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_OFFSET         0x00000028
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_LSB            24
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_MASK           0xff000000
+
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_OFFSET          0x0000002c
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_LSB             0
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_MASK            0x000000ff
+
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET     0x0000002c
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB        8
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK       0x0000ff00
+
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET     0x0000002c
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB        16
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK       0x00ff0000
+
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_OFFSET         0x0000002c
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_LSB            24
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_MASK           0xff000000
+
+#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_OFFSET                0x00000030
+#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_LSB                   0
+#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_MASK                  0x000000ff
+
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_OFFSET                0x00000030
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_LSB                   8
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_MASK                  0x0000ff00
+
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_OFFSET          0x00000030
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_LSB             16
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_MASK            0x00ff0000
+
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_OFFSET         0x00000030
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_LSB            24
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_MASK           0xff000000
+
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_OFFSET          0x00000034
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_LSB             0
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_MASK            0x000000ff
+
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET     0x00000034
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB        8
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK       0x0000ff00
+
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET     0x00000034
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB        16
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK       0x00ff0000
+
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_OFFSET         0x00000034
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_LSB            24
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_MASK           0xff000000
+
+#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_OFFSET                0x00000038
+#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_LSB                   0
+#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_MASK                  0x000000ff
+
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_OFFSET                0x00000038
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_LSB                   8
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_MASK                  0x0000ff00
+
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_OFFSET          0x00000038
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_LSB             16
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_MASK            0x00ff0000
+
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_OFFSET         0x00000038
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_LSB            24
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_MASK           0xff000000
+
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_OFFSET          0x0000003c
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_LSB             0
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_MASK            0x000000ff
+
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET     0x0000003c
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB        8
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK       0x0000ff00
+
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET     0x0000003c
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB        16
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK       0x00ff0000
+
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_OFFSET         0x0000003c
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_LSB            24
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_MASK           0xff000000
+
+#endif

hw/wcn6450/v1/receive_user_info.h

@@ -0,0 +1,107 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RECEIVE_USER_INFO_H_
+#define _RECEIVE_USER_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RECEIVE_USER_INFO 3
+
+struct receive_user_info {
+             uint32_t phy_ppdu_id                     : 16,
+                      user_rssi                       :  8,
+                      pkt_type                        :  4,
+                      stbc                            :  1,
+                      reception_type                  :  3;
+             uint32_t rate_mcs                        :  4,
+                      sgi                             :  2,
+                      receive_bandwidth               :  2,
+                      mimo_ss_bitmap                  :  8,
+                      ofdma_ru_allocation             :  8,
+                      ofdma_user_index                :  7,
+                      ofdma_content_channel           :  1;
+             uint32_t ldpc                            :  1,
+                      ru_width                        :  7,
+                      reserved_2a                     : 24;
+};
+
+#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_OFFSET                       0x00000000
+#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_LSB                          0
+#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_MASK                         0x0000ffff
+
+#define RECEIVE_USER_INFO_0_USER_RSSI_OFFSET                         0x00000000
+#define RECEIVE_USER_INFO_0_USER_RSSI_LSB                            16
+#define RECEIVE_USER_INFO_0_USER_RSSI_MASK                           0x00ff0000
+
+#define RECEIVE_USER_INFO_0_PKT_TYPE_OFFSET                          0x00000000
+#define RECEIVE_USER_INFO_0_PKT_TYPE_LSB                             24
+#define RECEIVE_USER_INFO_0_PKT_TYPE_MASK                            0x0f000000
+
+#define RECEIVE_USER_INFO_0_STBC_OFFSET                              0x00000000
+#define RECEIVE_USER_INFO_0_STBC_LSB                                 28
+#define RECEIVE_USER_INFO_0_STBC_MASK                                0x10000000
+
+#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_OFFSET                    0x00000000
+#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_LSB                       29
+#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_MASK                      0xe0000000
+
+#define RECEIVE_USER_INFO_1_RATE_MCS_OFFSET                          0x00000004
+#define RECEIVE_USER_INFO_1_RATE_MCS_LSB                             0
+#define RECEIVE_USER_INFO_1_RATE_MCS_MASK                            0x0000000f
+
+#define RECEIVE_USER_INFO_1_SGI_OFFSET                               0x00000004
+#define RECEIVE_USER_INFO_1_SGI_LSB                                  4
+#define RECEIVE_USER_INFO_1_SGI_MASK                                 0x00000030
+
+#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_OFFSET                 0x00000004
+#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_LSB                    6
+#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_MASK                   0x000000c0
+
+#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_OFFSET                    0x00000004
+#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_LSB                       8
+#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_MASK                      0x0000ff00
+
+#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_OFFSET               0x00000004
+#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_LSB                  16
+#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_MASK                 0x00ff0000
+
+#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_OFFSET                  0x00000004
+#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_LSB                     24
+#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_MASK                    0x7f000000
+
+#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_OFFSET             0x00000004
+#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_LSB                31
+#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_MASK               0x80000000
+
+#define RECEIVE_USER_INFO_2_LDPC_OFFSET                              0x00000008
+#define RECEIVE_USER_INFO_2_LDPC_LSB                                 0
+#define RECEIVE_USER_INFO_2_LDPC_MASK                                0x00000001
+
+#define RECEIVE_USER_INFO_2_RU_WIDTH_OFFSET                          0x00000008
+#define RECEIVE_USER_INFO_2_RU_WIDTH_LSB                             1
+#define RECEIVE_USER_INFO_2_RU_WIDTH_MASK                            0x000000fe
+
+#define RECEIVE_USER_INFO_2_RESERVED_2A_OFFSET                       0x00000008
+#define RECEIVE_USER_INFO_2_RESERVED_2A_LSB                          8
+#define RECEIVE_USER_INFO_2_RESERVED_2A_MASK                         0xffffff00
+
+#endif

hw/wcn6450/v1/reo_descriptor_threshold_reached_status.h

@@ -0,0 +1,200 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25
+
+struct reo_descriptor_threshold_reached_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t threshold_index                 :  2,
+                      reserved_2                      : 30;
+             uint32_t link_descriptor_counter0        : 24,
+                      reserved_3                      :  8;
+             uint32_t link_descriptor_counter1        : 24,
+                      reserved_4                      :  8;
+             uint32_t link_descriptor_counter2        : 24,
+                      reserved_5                      :  8;
+             uint32_t link_descriptor_counter_sum     : 26,
+                      reserved_6                      :  6;
+             uint32_t reserved_7                      : 32;
+             uint32_t reserved_8                      : 32;
+             uint32_t reserved_9a                     : 32;
+             uint32_t reserved_10a                    : 32;
+             uint32_t reserved_11a                    : 32;
+             uint32_t reserved_12a                    : 32;
+             uint32_t reserved_13a                    : 32;
+             uint32_t reserved_14a                    : 32;
+             uint32_t reserved_15a                    : 32;
+             uint32_t reserved_16a                    : 32;
+             uint32_t reserved_17a                    : 32;
+             uint32_t reserved_18a                    : 32;
+             uint32_t reserved_19a                    : 32;
+             uint32_t reserved_20a                    : 32;
+             uint32_t reserved_21a                    : 32;
+             uint32_t reserved_22a                    : 32;
+             uint32_t reserved_23a                    : 32;
+             uint32_t reserved_24a                    : 28,
+                      looping_count                   :  4;
+};
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET  0x00000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB     2
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK    0xfffffffc
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET  0x0000000c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB     24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK    0xff000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET  0x00000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB     24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK    0xff000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET  0x00000014
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB     24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK    0xff000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET  0x00000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB     26
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK    0xfc000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET  0x0000001c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB     0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK    0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET  0x00000020
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB     0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK    0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB  0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+#endif

hw/wcn6450/v1/reo_destination_ring.h

@@ -0,0 +1,301 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_DESTINATION_RING_H_
+#define _REO_DESTINATION_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "rx_msdu_desc_info.h"
+
+#define NUM_OF_DWORDS_REO_DESTINATION_RING 16
+
+struct reo_destination_ring {
+    struct            buffer_addr_info                       buf_or_link_desc_addr_info;
+    struct            rx_mpdu_desc_info                       rx_mpdu_desc_info_details;
+    struct            rx_msdu_desc_info                       rx_msdu_desc_info_details;
+             uint32_t rx_reo_queue_desc_addr_31_0     : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32    :  8,
+                      reo_dest_buffer_type            :  1,
+                      reo_push_reason                 :  2,
+                      reo_error_code                  :  5,
+                      receive_queue_number            : 16;
+             uint32_t soft_reorder_info_valid         :  1,
+                      reorder_opcode                  :  4,
+                      reorder_slot_index              :  8,
+                      mpdu_fragment_number            :  4,
+                      captured_msdu_data_size         :  4,
+                      sw_exception                    :  1,
+                      reserved_8a                     : 10;
+             uint32_t reo_destination_struct_signature: 32;
+             uint32_t reserved_10a                    : 32;
+             uint32_t reserved_11a                    : 32;
+             uint32_t reserved_12a                    : 32;
+             uint32_t reserved_13a                    : 32;
+             uint32_t reserved_14a                    : 32;
+             uint32_t reserved_15                     : 20,
+                      ring_id                         :  8,
+                      looping_count                   :  4;
+};
+
+#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
+
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
+
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000014
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000014
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB   30
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK  0x40000000
+
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB   31
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK  0x80000000
+
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET    0x00000018
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB       0
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK      0xffffffff
+
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET   0x0000001c
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB      0
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK     0x000000ff
+
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET           0x0000001c
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB              8
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK             0x00000100
+
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET                0x0000001c
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB                   9
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK                  0x00000600
+
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET                 0x0000001c
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB                    11
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK                   0x0000f800
+
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET           0x0000001c
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB              16
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK             0xffff0000
+
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET        0x00000020
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB           0
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK          0x00000001
+
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET                 0x00000020
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB                    1
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK                   0x0000001e
+
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET             0x00000020
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB                5
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK               0x00001fe0
+
+#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_OFFSET           0x00000020
+#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_LSB              13
+#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_MASK             0x0001e000
+
+#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_OFFSET        0x00000020
+#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_LSB           17
+#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_MASK          0x001e0000
+
+#define REO_DESTINATION_RING_8_SW_EXCEPTION_OFFSET                   0x00000020
+#define REO_DESTINATION_RING_8_SW_EXCEPTION_LSB                      21
+#define REO_DESTINATION_RING_8_SW_EXCEPTION_MASK                     0x00200000
+
+#define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET                    0x00000020
+#define REO_DESTINATION_RING_8_RESERVED_8A_LSB                       22
+#define REO_DESTINATION_RING_8_RESERVED_8A_MASK                      0xffc00000
+
+#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x00000024
+#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_LSB  0
+#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET                  0x00000028
+#define REO_DESTINATION_RING_10_RESERVED_10A_LSB                     0
+#define REO_DESTINATION_RING_10_RESERVED_10A_MASK                    0xffffffff
+
+#define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET                  0x0000002c
+#define REO_DESTINATION_RING_11_RESERVED_11A_LSB                     0
+#define REO_DESTINATION_RING_11_RESERVED_11A_MASK                    0xffffffff
+
+#define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET                  0x00000030
+#define REO_DESTINATION_RING_12_RESERVED_12A_LSB                     0
+#define REO_DESTINATION_RING_12_RESERVED_12A_MASK                    0xffffffff
+
+#define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET                  0x00000034
+#define REO_DESTINATION_RING_13_RESERVED_13A_LSB                     0
+#define REO_DESTINATION_RING_13_RESERVED_13A_MASK                    0xffffffff
+
+#define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET                  0x00000038
+#define REO_DESTINATION_RING_14_RESERVED_14A_LSB                     0
+#define REO_DESTINATION_RING_14_RESERVED_14A_MASK                    0xffffffff
+
+#define REO_DESTINATION_RING_15_RESERVED_15_OFFSET                   0x0000003c
+#define REO_DESTINATION_RING_15_RESERVED_15_LSB                      0
+#define REO_DESTINATION_RING_15_RESERVED_15_MASK                     0x000fffff
+
+#define REO_DESTINATION_RING_15_RING_ID_OFFSET                       0x0000003c
+#define REO_DESTINATION_RING_15_RING_ID_LSB                          20
+#define REO_DESTINATION_RING_15_RING_ID_MASK                         0x0ff00000
+
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET                 0x0000003c
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB                    28
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK                   0xf0000000
+
+#endif

hw/wcn6450/v1/reo_entrance_ring.h

@@ -0,0 +1,201 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_ENTRANCE_RING_H_
+#define _REO_ENTRANCE_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_mpdu_details.h"
+
+#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
+
+struct reo_entrance_ring {
+    struct            rx_mpdu_details                       reo_level_mpdu_frame_info;
+             uint32_t rx_reo_queue_desc_addr_31_0     : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32    :  8,
+                      rounded_mpdu_byte_count         : 14,
+                      reo_destination_indication      :  5,
+                      frameless_bar                   :  1,
+                      reserved_5a                     :  4;
+             uint32_t rxdma_push_reason               :  2,
+                      rxdma_error_code                :  5,
+                      mpdu_fragment_number            :  4,
+                      sw_exception                    :  1,
+                      sw_exception_mpdu_delink        :  1,
+                      sw_exception_destination_ring_valid:  1,
+                      sw_exception_destination_ring   :  5,
+                      reserved_6a                     : 13;
+             uint32_t phy_ppdu_id                     : 16,
+                      reserved_7a                     :  4,
+                      ring_id                         :  8,
+                      looping_count                   :  4;
+};
+
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
+
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
+
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET       0x00000010
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB          0
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK         0xffffffff
+
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET      0x00000014
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB         0
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK        0x000000ff
+
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET           0x00000014
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB              8
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK             0x003fff00
+
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET        0x00000014
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB           22
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK          0x07c00000
+
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET                     0x00000014
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB                        27
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK                       0x08000000
+
+#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET                       0x00000014
+#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB                          28
+#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK                         0xf0000000
+
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET                 0x00000018
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB                    0
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK                   0x00000003
+
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET                  0x00000018
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB                     2
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK                    0x0000007c
+
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET              0x00000018
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB                 7
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK                0x00000780
+
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_OFFSET                      0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_LSB                         11
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MASK                        0x00000800
+
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_OFFSET          0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_LSB             12
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_MASK            0x00001000
+
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_LSB  13
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000
+
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_OFFSET     0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_LSB        14
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_MASK       0x0007c000
+
+#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET                       0x00000018
+#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB                          19
+#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK                         0xfff80000
+
+#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_OFFSET                       0x0000001c
+#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_LSB                          0
+#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_MASK                         0x0000ffff
+
+#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET                       0x0000001c
+#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB                          16
+#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK                         0x000f0000
+
+#define REO_ENTRANCE_RING_7_RING_ID_OFFSET                           0x0000001c
+#define REO_ENTRANCE_RING_7_RING_ID_LSB                              20
+#define REO_ENTRANCE_RING_7_RING_ID_MASK                             0x0ff00000
+
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET                     0x0000001c
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB                        28
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK                       0xf0000000
+
+#endif

hw/wcn6450/v1/reo_flush_cache.h

@@ -0,0 +1,122 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_FLUSH_CACHE_H_
+#define _REO_FLUSH_CACHE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9
+
+struct reo_flush_cache {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t flush_addr_31_0                 : 32;
+             uint32_t flush_addr_39_32                :  8,
+                      forward_all_mpdus_in_queue      :  1,
+                      release_cache_block_index       :  1,
+                      cache_block_resource_index      :  2,
+                      flush_without_invalidate        :  1,
+                      block_cache_usage_after_flush   :  1,
+                      flush_entire_cache              :  1,
+                      reserved_2b                     : 17;
+             uint32_t reserved_3a                     : 32;
+             uint32_t reserved_4a                     : 32;
+             uint32_t reserved_5a                     : 32;
+             uint32_t reserved_6a                     : 32;
+             uint32_t reserved_7a                     : 32;
+             uint32_t reserved_8a                     : 32;
+};
+
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET           0x00000000
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB              0
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK             0x0000ffff
+
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET      0x00000000
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB         16
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK        0x00010000
+
+#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET              0x00000000
+#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_LSB                 17
+#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_MASK                0xfffe0000
+
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET                     0x00000004
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB                        0
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK                       0xffffffff
+
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET                    0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB                       0
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK                      0x000000ff
+
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET          0x00000008
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB             8
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK            0x00000100
+
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET           0x00000008
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB              9
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK             0x00000200
+
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET          0x00000008
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB             10
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK            0x00000c00
+
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET            0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB               12
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK              0x00001000
+
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET       0x00000008
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB          13
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK         0x00002000
+
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET                  0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB                     14
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK                    0x00004000
+
+#define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET                         0x00000008
+#define REO_FLUSH_CACHE_2_RESERVED_2B_LSB                            15
+#define REO_FLUSH_CACHE_2_RESERVED_2B_MASK                           0xffff8000
+
+#define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET                         0x0000000c
+#define REO_FLUSH_CACHE_3_RESERVED_3A_LSB                            0
+#define REO_FLUSH_CACHE_3_RESERVED_3A_MASK                           0xffffffff
+
+#define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET                         0x00000010
+#define REO_FLUSH_CACHE_4_RESERVED_4A_LSB                            0
+#define REO_FLUSH_CACHE_4_RESERVED_4A_MASK                           0xffffffff
+
+#define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET                         0x00000014
+#define REO_FLUSH_CACHE_5_RESERVED_5A_LSB                            0
+#define REO_FLUSH_CACHE_5_RESERVED_5A_MASK                           0xffffffff
+
+#define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET                         0x00000018
+#define REO_FLUSH_CACHE_6_RESERVED_6A_LSB                            0
+#define REO_FLUSH_CACHE_6_RESERVED_6A_MASK                           0xffffffff
+
+#define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET                         0x0000001c
+#define REO_FLUSH_CACHE_7_RESERVED_7A_LSB                            0
+#define REO_FLUSH_CACHE_7_RESERVED_7A_MASK                           0xffffffff
+
+#define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET                         0x00000020
+#define REO_FLUSH_CACHE_8_RESERVED_8A_LSB                            0
+#define REO_FLUSH_CACHE_8_RESERVED_8A_MASK                           0xffffffff
+
+#endif

hw/wcn6450/v1/reo_flush_cache_status.h

@@ -0,0 +1,215 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_FLUSH_CACHE_STATUS_H_
+#define _REO_FLUSH_CACHE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 25
+
+struct reo_flush_cache_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t error_detected                  :  1,
+                      block_error_details             :  2,
+                      reserved_2a                     :  5,
+                      cache_controller_flush_status_hit:  1,
+                      cache_controller_flush_status_desc_type:  3,
+                      cache_controller_flush_status_client_id:  4,
+                      cache_controller_flush_status_error:  2,
+                      cache_controller_flush_count    :  8,
+                      reserved_2b                     :  6;
+             uint32_t reserved_3a                     : 32;
+             uint32_t reserved_4a                     : 32;
+             uint32_t reserved_5a                     : 32;
+             uint32_t reserved_6a                     : 32;
+             uint32_t reserved_7a                     : 32;
+             uint32_t reserved_8a                     : 32;
+             uint32_t reserved_9a                     : 32;
+             uint32_t reserved_10a                    : 32;
+             uint32_t reserved_11a                    : 32;
+             uint32_t reserved_12a                    : 32;
+             uint32_t reserved_13a                    : 32;
+             uint32_t reserved_14a                    : 32;
+             uint32_t reserved_15a                    : 32;
+             uint32_t reserved_16a                    : 32;
+             uint32_t reserved_17a                    : 32;
+             uint32_t reserved_18a                    : 32;
+             uint32_t reserved_19a                    : 32;
+             uint32_t reserved_20a                    : 32;
+             uint32_t reserved_21a                    : 32;
+             uint32_t reserved_22a                    : 32;
+             uint32_t reserved_23a                    : 32;
+             uint32_t reserved_24a                    : 28,
+                      looping_count                   :  4;
+};
+
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET    0x00000000
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB       28
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK      0xf0000000
+
+#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET      0x00000004
+#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB         0
+#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK        0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_OFFSET               0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_LSB                  0
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_MASK                 0x00000001
+
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_OFFSET          0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_LSB             1
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_MASK            0x00000006
+
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_OFFSET                  0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_LSB                     3
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_MASK                    0x000000f8
+
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100
+
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00
+
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000
+
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000
+
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_LSB    18
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_MASK   0x03fc0000
+
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_OFFSET                  0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_LSB                     26
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_MASK                    0xfc000000
+
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_OFFSET                  0x0000000c
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_MASK                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_OFFSET                  0x00000010
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_MASK                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_OFFSET                  0x00000014
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_MASK                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_OFFSET                  0x00000018
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_MASK                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_OFFSET                  0x0000001c
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_MASK                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_OFFSET                  0x00000020
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_MASK                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_OFFSET                  0x00000024
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_LSB                     0
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_MASK                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_OFFSET                0x00000028
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_MASK                  0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_OFFSET                0x0000002c
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_MASK                  0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_OFFSET                0x00000030
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_MASK                  0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_OFFSET                0x00000034
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_MASK                  0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_OFFSET                0x00000038
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_MASK                  0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_OFFSET                0x0000003c
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_MASK                  0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_OFFSET                0x00000040
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_MASK                  0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_OFFSET                0x00000044
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_MASK                  0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_OFFSET                0x00000048
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_MASK                  0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_OFFSET                0x0000004c
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_MASK                  0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_OFFSET                0x00000050
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_MASK                  0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_OFFSET                0x00000054
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_MASK                  0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_OFFSET                0x00000058
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_MASK                  0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_OFFSET                0x0000005c
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_MASK                  0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_OFFSET                0x00000060
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_LSB                   0
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_MASK                  0x0fffffff
+
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_OFFSET               0x00000060
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_LSB                  28
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_MASK                 0xf0000000
+
+#endif

hw/wcn6450/v1/reo_flush_queue.h

@@ -0,0 +1,107 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_FLUSH_QUEUE_H_
+#define _REO_FLUSH_QUEUE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9
+
+struct reo_flush_queue {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t flush_desc_addr_31_0            : 32;
+             uint32_t flush_desc_addr_39_32           :  8,
+                      block_desc_addr_usage_after_flush:  1,
+                      block_resource_index            :  2,
+                      invalidate_queue_and_flush      :  1,
+                      reserved_2a                     : 20;
+             uint32_t reserved_3a                     : 32;
+             uint32_t reserved_4a                     : 32;
+             uint32_t reserved_5a                     : 32;
+             uint32_t reserved_6a                     : 32;
+             uint32_t reserved_7a                     : 32;
+             uint32_t reserved_8a                     : 32;
+};
+
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET           0x00000000
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB              0
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK             0x0000ffff
+
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET      0x00000000
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB         16
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK        0x00010000
+
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET              0x00000000
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB                 17
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK                0xfffe0000
+
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET                0x00000004
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB                   0
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET               0x00000008
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB                  0
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK                 0x000000ff
+
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET   0x00000008
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB      8
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK     0x00000100
+
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET                0x00000008
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB                   9
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK                  0x00000600
+
+#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_OFFSET          0x00000008
+#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_LSB             11
+#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_MASK            0x00000800
+
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET                         0x00000008
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB                            12
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK                           0xfffff000
+
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET                         0x0000000c
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB                            0
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK                           0xffffffff
+
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET                         0x00000010
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB                            0
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK                           0xffffffff
+
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET                         0x00000014
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB                            0
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK                           0xffffffff
+
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET                         0x00000018
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB                            0
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK                           0xffffffff
+
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET                         0x0000001c
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB                            0
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK                           0xffffffff
+
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET                         0x00000020
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB                            0
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK                           0xffffffff
+
+#endif

hw/wcn6450/v1/reo_flush_queue_status.h

@@ -0,0 +1,180 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_FLUSH_QUEUE_STATUS_H_
+#define _REO_FLUSH_QUEUE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 25
+
+struct reo_flush_queue_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t error_detected                  :  1,
+                      reserved_2a                     : 31;
+             uint32_t reserved_3a                     : 32;
+             uint32_t reserved_4a                     : 32;
+             uint32_t reserved_5a                     : 32;
+             uint32_t reserved_6a                     : 32;
+             uint32_t reserved_7a                     : 32;
+             uint32_t reserved_8a                     : 32;
+             uint32_t reserved_9a                     : 32;
+             uint32_t reserved_10a                    : 32;
+             uint32_t reserved_11a                    : 32;
+             uint32_t reserved_12a                    : 32;
+             uint32_t reserved_13a                    : 32;
+             uint32_t reserved_14a                    : 32;
+             uint32_t reserved_15a                    : 32;
+             uint32_t reserved_16a                    : 32;
+             uint32_t reserved_17a                    : 32;
+             uint32_t reserved_18a                    : 32;
+             uint32_t reserved_19a                    : 32;
+             uint32_t reserved_20a                    : 32;
+             uint32_t reserved_21a                    : 32;
+             uint32_t reserved_22a                    : 32;
+             uint32_t reserved_23a                    : 32;
+             uint32_t reserved_24a                    : 28,
+                      looping_count                   :  4;
+};
+
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET    0x00000000
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB       28
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK      0xf0000000
+
+#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET      0x00000004
+#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB         0
+#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK        0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_OFFSET               0x00000008
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_LSB                  0
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_MASK                 0x00000001
+
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_OFFSET                  0x00000008
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_LSB                     1
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_MASK                    0xfffffffe
+
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_OFFSET                  0x0000000c
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_MASK                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_OFFSET                  0x00000010
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_MASK                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_OFFSET                  0x00000014
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_MASK                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_OFFSET                  0x00000018
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_MASK                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_OFFSET                  0x0000001c
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_MASK                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_OFFSET                  0x00000020
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_MASK                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_OFFSET                  0x00000024
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_LSB                     0
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_MASK                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_OFFSET                0x00000028
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_OFFSET                0x0000002c
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_OFFSET                0x00000030
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_OFFSET                0x00000034
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_OFFSET                0x00000038
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_OFFSET                0x0000003c
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_OFFSET                0x00000040
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_OFFSET                0x00000044
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_OFFSET                0x00000048
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_OFFSET                0x0000004c
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_OFFSET                0x00000050
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_OFFSET                0x00000054
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_OFFSET                0x00000058
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_OFFSET                0x0000005c
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_MASK                  0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_OFFSET                0x00000060
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_LSB                   0
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_MASK                  0x0fffffff
+
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET               0x00000060
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_LSB                  28
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_MASK                 0xf0000000
+
+#endif

hw/wcn6450/v1/reo_flush_timeout_list.h

@@ -0,0 +1,97 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
+#define _REO_FLUSH_TIMEOUT_LIST_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9
+
+struct reo_flush_timeout_list {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t ac_timout_list                  :  2,
+                      reserved_1                      : 30;
+             uint32_t minimum_release_desc_count      : 16,
+                      minimum_forward_buf_count       : 16;
+             uint32_t reserved_3a                     : 32;
+             uint32_t reserved_4a                     : 32;
+             uint32_t reserved_5a                     : 32;
+             uint32_t reserved_6a                     : 32;
+             uint32_t reserved_7a                     : 32;
+             uint32_t reserved_8a                     : 32;
+};
+
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET    0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_LSB       0
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_MASK      0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB  16
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_OFFSET       0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_LSB          17
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_MASK         0xfffe0000
+
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_OFFSET               0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_LSB                  0
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_MASK                 0x00000003
+
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_OFFSET                   0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_LSB                      2
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_MASK                     0xfffffffc
+
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_OFFSET   0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_LSB      0
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_MASK     0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_OFFSET    0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_LSB       16
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_MASK      0xffff0000
+
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_OFFSET                  0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_MASK                    0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_OFFSET                  0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_MASK                    0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_OFFSET                  0x00000014
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_MASK                    0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_OFFSET                  0x00000018
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_MASK                    0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_OFFSET                  0x0000001c
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_MASK                    0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_OFFSET                  0x00000020
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_LSB                     0
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_MASK                    0xffffffff
+
+#endif

hw/wcn6450/v1/reo_flush_timeout_list_status.h

@@ -0,0 +1,190 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 25
+
+struct reo_flush_timeout_list_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t error_detected                  :  1,
+                      timout_list_empty               :  1,
+                      reserved_2a                     : 30;
+             uint32_t release_desc_count              : 16,
+                      forward_buf_count               : 16;
+             uint32_t reserved_4a                     : 32;
+             uint32_t reserved_5a                     : 32;
+             uint32_t reserved_6a                     : 32;
+             uint32_t reserved_7a                     : 32;
+             uint32_t reserved_8a                     : 32;
+             uint32_t reserved_9a                     : 32;
+             uint32_t reserved_10a                    : 32;
+             uint32_t reserved_11a                    : 32;
+             uint32_t reserved_12a                    : 32;
+             uint32_t reserved_13a                    : 32;
+             uint32_t reserved_14a                    : 32;
+             uint32_t reserved_15a                    : 32;
+             uint32_t reserved_16a                    : 32;
+             uint32_t reserved_17a                    : 32;
+             uint32_t reserved_18a                    : 32;
+             uint32_t reserved_19a                    : 32;
+             uint32_t reserved_20a                    : 32;
+             uint32_t reserved_21a                    : 32;
+             uint32_t reserved_22a                    : 32;
+             uint32_t reserved_23a                    : 32;
+             uint32_t reserved_24a                    : 28,
+                      looping_count                   :  4;
+};
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB  0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_OFFSET        0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_LSB           0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_MASK          0x00000001
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_OFFSET     0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_LSB        1
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_MASK       0x00000002
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_OFFSET           0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_LSB              2
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_MASK             0xfffffffc
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_OFFSET    0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_LSB       0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_MASK      0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_OFFSET     0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_LSB        16
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_MASK       0xffff0000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_OFFSET           0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_MASK             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_OFFSET           0x00000014
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_MASK             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_OFFSET           0x00000018
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_MASK             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_OFFSET           0x0000001c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_MASK             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_OFFSET           0x00000020
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_MASK             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_OFFSET           0x00000024
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_LSB              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_MASK             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_OFFSET         0x00000028
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_MASK           0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_OFFSET         0x0000002c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_MASK           0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_OFFSET         0x00000030
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_MASK           0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_OFFSET         0x00000034
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_MASK           0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_OFFSET         0x00000038
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_MASK           0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_OFFSET         0x0000003c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_MASK           0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_OFFSET         0x00000040
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_MASK           0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_OFFSET         0x00000044
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_MASK           0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_OFFSET         0x00000048
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_MASK           0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_OFFSET         0x0000004c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_MASK           0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_OFFSET         0x00000050
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_MASK           0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_OFFSET         0x00000054
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_MASK           0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_OFFSET         0x00000058
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_MASK           0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_OFFSET         0x0000005c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_MASK           0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_OFFSET         0x00000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_LSB            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_MASK           0x0fffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_OFFSET        0x00000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_LSB           28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_MASK          0xf0000000
+
+#endif

hw/wcn6450/v1/reo_get_queue_stats.h

@@ -0,0 +1,97 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_GET_QUEUE_STATS_H_
+#define _REO_GET_QUEUE_STATS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9
+
+struct reo_get_queue_stats {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t rx_reo_queue_desc_addr_31_0     : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32    :  8,
+                      clear_stats                     :  1,
+                      reserved_2a                     : 23;
+             uint32_t reserved_3a                     : 32;
+             uint32_t reserved_4a                     : 32;
+             uint32_t reserved_5a                     : 32;
+             uint32_t reserved_6a                     : 32;
+             uint32_t reserved_7a                     : 32;
+             uint32_t reserved_8a                     : 32;
+};
+
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET       0x00000000
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_LSB          0
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_MASK         0x0000ffff
+
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET  0x00000000
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB     16
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK    0x00010000
+
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_OFFSET          0x00000000
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_LSB             17
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_MASK            0xfffe0000
+
+#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET     0x00000004
+#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB        0
+#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK       0xffffffff
+
+#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET    0x00000008
+#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB       0
+#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK      0x000000ff
+
+#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_OFFSET                     0x00000008
+#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_LSB                        8
+#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_MASK                       0x00000100
+
+#define REO_GET_QUEUE_STATS_2_RESERVED_2A_OFFSET                     0x00000008
+#define REO_GET_QUEUE_STATS_2_RESERVED_2A_LSB                        9
+#define REO_GET_QUEUE_STATS_2_RESERVED_2A_MASK                       0xfffffe00
+
+#define REO_GET_QUEUE_STATS_3_RESERVED_3A_OFFSET                     0x0000000c
+#define REO_GET_QUEUE_STATS_3_RESERVED_3A_LSB                        0
+#define REO_GET_QUEUE_STATS_3_RESERVED_3A_MASK                       0xffffffff
+
+#define REO_GET_QUEUE_STATS_4_RESERVED_4A_OFFSET                     0x00000010
+#define REO_GET_QUEUE_STATS_4_RESERVED_4A_LSB                        0
+#define REO_GET_QUEUE_STATS_4_RESERVED_4A_MASK                       0xffffffff
+
+#define REO_GET_QUEUE_STATS_5_RESERVED_5A_OFFSET                     0x00000014
+#define REO_GET_QUEUE_STATS_5_RESERVED_5A_LSB                        0
+#define REO_GET_QUEUE_STATS_5_RESERVED_5A_MASK                       0xffffffff
+
+#define REO_GET_QUEUE_STATS_6_RESERVED_6A_OFFSET                     0x00000018
+#define REO_GET_QUEUE_STATS_6_RESERVED_6A_LSB                        0
+#define REO_GET_QUEUE_STATS_6_RESERVED_6A_MASK                       0xffffffff
+
+#define REO_GET_QUEUE_STATS_7_RESERVED_7A_OFFSET                     0x0000001c
+#define REO_GET_QUEUE_STATS_7_RESERVED_7A_LSB                        0
+#define REO_GET_QUEUE_STATS_7_RESERVED_7A_MASK                       0xffffffff
+
+#define REO_GET_QUEUE_STATS_8_RESERVED_8A_OFFSET                     0x00000020
+#define REO_GET_QUEUE_STATS_8_RESERVED_8A_LSB                        0
+#define REO_GET_QUEUE_STATS_8_RESERVED_8A_MASK                       0xffffffff
+
+#endif

hw/wcn6450/v1/reo_get_queue_stats_status.h

@@ -0,0 +1,220 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_GET_QUEUE_STATS_STATUS_H_
+#define _REO_GET_QUEUE_STATS_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 25
+
+struct reo_get_queue_stats_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t ssn                             : 12,
+                      current_index                   :  8,
+                      reserved_2                      : 12;
+             uint32_t pn_31_0                         : 32;
+             uint32_t pn_63_32                        : 32;
+             uint32_t pn_95_64                        : 32;
+             uint32_t pn_127_96                       : 32;
+             uint32_t last_rx_enqueue_timestamp       : 32;
+             uint32_t last_rx_dequeue_timestamp       : 32;
+             uint32_t rx_bitmap_31_0                  : 32;
+             uint32_t rx_bitmap_63_32                 : 32;
+             uint32_t rx_bitmap_95_64                 : 32;
+             uint32_t rx_bitmap_127_96                : 32;
+             uint32_t rx_bitmap_159_128               : 32;
+             uint32_t rx_bitmap_191_160               : 32;
+             uint32_t rx_bitmap_223_192               : 32;
+             uint32_t rx_bitmap_255_224               : 32;
+             uint32_t current_mpdu_count              :  7,
+                      current_msdu_count              : 25;
+             uint32_t reserved_18                     :  4,
+                      timeout_count                   :  6,
+                      forward_due_to_bar_count        :  6,
+                      duplicate_count                 : 16;
+             uint32_t frames_in_order_count           : 24,
+                      bar_received_count              :  8;
+             uint32_t mpdu_frames_processed_count     : 32;
+             uint32_t msdu_frames_processed_count     : 32;
+             uint32_t total_processed_byte_count      : 32;
+             uint32_t late_receive_mpdu_count         : 12,
+                      window_jump_2k                  :  4,
+                      hole_count                      : 16;
+             uint32_t reserved_24a                    : 28,
+                      looping_count                   :  4;
+};
+
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB   28
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK  0xf0000000
+
+#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET  0x00000004
+#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB     0
+#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK    0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_2_SSN_OFFSET                      0x00000008
+#define REO_GET_QUEUE_STATS_STATUS_2_SSN_LSB                         0
+#define REO_GET_QUEUE_STATS_STATUS_2_SSN_MASK                        0x00000fff
+
+#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_OFFSET            0x00000008
+#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_LSB               12
+#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_MASK              0x000ff000
+
+#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_OFFSET               0x00000008
+#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_LSB                  20
+#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_MASK                 0xfff00000
+
+#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_OFFSET                  0x0000000c
+#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_LSB                     0
+#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_MASK                    0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_OFFSET                 0x00000010
+#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_LSB                    0
+#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_MASK                   0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_OFFSET                 0x00000014
+#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_LSB                    0
+#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_MASK                   0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_OFFSET                0x00000018
+#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_LSB                   0
+#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_MASK                  0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000001c
+#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_LSB   0
+#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_MASK  0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000020
+#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_LSB   0
+#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_MASK  0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_OFFSET           0x00000024
+#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_LSB              0
+#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_MASK             0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_OFFSET         0x00000028
+#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_LSB            0
+#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_MASK           0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_OFFSET         0x0000002c
+#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_LSB            0
+#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_MASK           0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_OFFSET        0x00000030
+#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_LSB           0
+#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_MASK          0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_OFFSET       0x00000034
+#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_LSB          0
+#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_MASK         0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_OFFSET       0x00000038
+#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_LSB          0
+#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_MASK         0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_OFFSET       0x0000003c
+#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_LSB          0
+#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_MASK         0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_OFFSET       0x00000040
+#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_LSB          0
+#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_MASK         0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_OFFSET      0x00000044
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_LSB         0
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_MASK        0x0000007f
+
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_OFFSET      0x00000044
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_LSB         7
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_MASK        0xffffff80
+
+#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_OFFSET             0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_LSB                0
+#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_MASK               0x0000000f
+
+#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_OFFSET           0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_LSB              4
+#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_MASK             0x000003f0
+
+#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_LSB   10
+#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_MASK  0x0000fc00
+
+#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_OFFSET         0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_LSB            16
+#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_MASK           0xffff0000
+
+#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_OFFSET   0x0000004c
+#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_LSB      0
+#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_MASK     0x00ffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_OFFSET      0x0000004c
+#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_LSB         24
+#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_MASK        0xff000000
+
+#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000050
+#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000054
+#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000058
+#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000005c
+#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_LSB    0
+#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_MASK   0x00000fff
+
+#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_OFFSET          0x0000005c
+#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_LSB             12
+#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_MASK            0x0000f000
+
+#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_OFFSET              0x0000005c
+#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_LSB                 16
+#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_MASK                0xffff0000
+
+#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_OFFSET            0x00000060
+#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_LSB               0
+#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_MASK              0x0fffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_OFFSET           0x00000060
+#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_LSB              28
+#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_MASK             0xf0000000
+
+#endif

hw/wcn6450/v1/reo_unblock_cache.h

@@ -0,0 +1,97 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_UNBLOCK_CACHE_H_
+#define _REO_UNBLOCK_CACHE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9
+
+struct reo_unblock_cache {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t unblock_type                    :  1,
+                      cache_block_resource_index      :  2,
+                      reserved_1a                     : 29;
+             uint32_t reserved_2a                     : 32;
+             uint32_t reserved_3a                     : 32;
+             uint32_t reserved_4a                     : 32;
+             uint32_t reserved_5a                     : 32;
+             uint32_t reserved_6a                     : 32;
+             uint32_t reserved_7a                     : 32;
+             uint32_t reserved_8a                     : 32;
+};
+
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET         0x00000000
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB            0
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK           0x0000ffff
+
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET    0x00000000
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB       16
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK      0x00010000
+
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET            0x00000000
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_LSB               17
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_MASK              0xfffe0000
+
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_OFFSET                      0x00000004
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_LSB                         0
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_MASK                        0x00000001
+
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_OFFSET        0x00000004
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_LSB           1
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_MASK          0x00000006
+
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_OFFSET                       0x00000004
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_LSB                          3
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_MASK                         0xfffffff8
+
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_OFFSET                       0x00000008
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_LSB                          0
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_MASK                         0xffffffff
+
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_OFFSET                       0x0000000c
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_LSB                          0
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_MASK                         0xffffffff
+
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_OFFSET                       0x00000010
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_LSB                          0
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_MASK                         0xffffffff
+
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_OFFSET                       0x00000014
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_LSB                          0
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_MASK                         0xffffffff
+
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_OFFSET                       0x00000018
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_LSB                          0
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_MASK                         0xffffffff
+
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_OFFSET                       0x0000001c
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_LSB                          0
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_MASK                         0xffffffff
+
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_OFFSET                       0x00000020
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_LSB                          0
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_MASK                         0xffffffff
+
+#endif

hw/wcn6450/v1/reo_unblock_cache_status.h

@@ -0,0 +1,185 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
+#define _REO_UNBLOCK_CACHE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 25
+
+struct reo_unblock_cache_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t error_detected                  :  1,
+                      unblock_type                    :  1,
+                      reserved_2a                     : 30;
+             uint32_t reserved_3a                     : 32;
+             uint32_t reserved_4a                     : 32;
+             uint32_t reserved_5a                     : 32;
+             uint32_t reserved_6a                     : 32;
+             uint32_t reserved_7a                     : 32;
+             uint32_t reserved_8a                     : 32;
+             uint32_t reserved_9a                     : 32;
+             uint32_t reserved_10a                    : 32;
+             uint32_t reserved_11a                    : 32;
+             uint32_t reserved_12a                    : 32;
+             uint32_t reserved_13a                    : 32;
+             uint32_t reserved_14a                    : 32;
+             uint32_t reserved_15a                    : 32;
+             uint32_t reserved_16a                    : 32;
+             uint32_t reserved_17a                    : 32;
+             uint32_t reserved_18a                    : 32;
+             uint32_t reserved_19a                    : 32;
+             uint32_t reserved_20a                    : 32;
+             uint32_t reserved_21a                    : 32;
+             uint32_t reserved_22a                    : 32;
+             uint32_t reserved_23a                    : 32;
+             uint32_t reserved_24a                    : 28,
+                      looping_count                   :  4;
+};
+
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET  0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB     28
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK    0xf0000000
+
+#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET    0x00000004
+#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB       0
+#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK      0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_OFFSET             0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_LSB                0
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_MASK               0x00000001
+
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_OFFSET               0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_LSB                  1
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_MASK                 0x00000002
+
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_OFFSET                0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_LSB                   2
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_MASK                  0xfffffffc
+
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_OFFSET                0x0000000c
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_MASK                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_OFFSET                0x00000010
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_MASK                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_OFFSET                0x00000014
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_MASK                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_OFFSET                0x00000018
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_MASK                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_OFFSET                0x0000001c
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_MASK                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_OFFSET                0x00000020
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_MASK                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_OFFSET                0x00000024
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_LSB                   0
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_MASK                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_OFFSET              0x00000028
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_MASK                0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_OFFSET              0x0000002c
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_MASK                0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_OFFSET              0x00000030
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_MASK                0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_OFFSET              0x00000034
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_MASK                0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_OFFSET              0x00000038
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_MASK                0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_OFFSET              0x0000003c
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_MASK                0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_OFFSET              0x00000040
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_MASK                0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_OFFSET              0x00000044
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_MASK                0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_OFFSET              0x00000048
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_MASK                0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_OFFSET              0x0000004c
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_MASK                0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_OFFSET              0x00000050
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_MASK                0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_OFFSET              0x00000054
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_MASK                0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_OFFSET              0x00000058
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_MASK                0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_OFFSET              0x0000005c
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_MASK                0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_OFFSET              0x00000060
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_LSB                 0
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_MASK                0x0fffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_OFFSET             0x00000060
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_LSB                28
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_MASK               0xf0000000
+
+#endif

hw/wcn6450/v1/reo_update_rx_reo_queue.h

@@ -0,0 +1,317 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_H_
+#define _REO_UPDATE_RX_REO_QUEUE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9
+
+struct reo_update_rx_reo_queue {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t rx_reo_queue_desc_addr_31_0     : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32    :  8,
+                      update_receive_queue_number     :  1,
+                      update_vld                      :  1,
+                      update_associated_link_descriptor_counter:  1,
+                      update_disable_duplicate_detection:  1,
+                      update_soft_reorder_enable      :  1,
+                      update_ac                       :  1,
+                      update_bar                      :  1,
+                      update_rty                      :  1,
+                      update_chk_2k_mode              :  1,
+                      update_oor_mode                 :  1,
+                      update_ba_window_size           :  1,
+                      update_pn_check_needed          :  1,
+                      update_pn_shall_be_even         :  1,
+                      update_pn_shall_be_uneven       :  1,
+                      update_pn_handling_enable       :  1,
+                      update_pn_size                  :  1,
+                      update_ignore_ampdu_flag        :  1,
+                      update_svld                     :  1,
+                      update_ssn                      :  1,
+                      update_seq_2k_error_detected_flag:  1,
+                      update_pn_error_detected_flag   :  1,
+                      update_pn_valid                 :  1,
+                      update_pn                       :  1,
+                      clear_stat_counters             :  1;
+             uint32_t receive_queue_number            : 16,
+                      vld                             :  1,
+                      associated_link_descriptor_counter:  2,
+                      disable_duplicate_detection     :  1,
+                      soft_reorder_enable             :  1,
+                      ac                              :  2,
+                      bar                             :  1,
+                      rty                             :  1,
+                      chk_2k_mode                     :  1,
+                      oor_mode                        :  1,
+                      pn_check_needed                 :  1,
+                      pn_shall_be_even                :  1,
+                      pn_shall_be_uneven              :  1,
+                      pn_handling_enable              :  1,
+                      ignore_ampdu_flag               :  1;
+             uint32_t ba_window_size                  :  8,
+                      pn_size                         :  2,
+                      svld                            :  1,
+                      ssn                             : 12,
+                      seq_2k_error_detected_flag      :  1,
+                      pn_error_detected_flag          :  1,
+                      pn_valid                        :  1,
+                      flush_from_cache                :  1,
+                      reserved_4a                     :  5;
+             uint32_t pn_31_0                         : 32;
+             uint32_t pn_63_32                        : 32;
+             uint32_t pn_95_64                        : 32;
+             uint32_t pn_127_96                       : 32;
+};
+
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET   0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB      0
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK     0x0000ffff
+
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET      0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB         17
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK        0xfffe0000
+
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB    0
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK   0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB   0
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK  0x000000ff
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_LSB    8
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_MASK   0x00000100
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_OFFSET                  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_LSB                     9
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_MASK                    0x00000200
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_OFFSET  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_LSB     12
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_MASK    0x00001000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_OFFSET                   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_LSB                      13
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_MASK                     0x00002000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_OFFSET                  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_LSB                     14
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_MASK                    0x00004000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_OFFSET                  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_LSB                     15
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_MASK                    0x00008000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_OFFSET          0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_LSB             16
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_MASK            0x00010000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_OFFSET             0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_LSB                17
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_MASK               0x00020000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_OFFSET       0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_LSB          18
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_MASK         0x00040000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_OFFSET      0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_LSB         19
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_MASK        0x00080000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_OFFSET     0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_LSB        20
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_MASK       0x00100000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_LSB      21
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_MASK     0x00200000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_OFFSET   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_LSB      22
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_MASK     0x00400000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_OFFSET              0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_LSB                 23
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_MASK                0x00800000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_OFFSET    0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_LSB       24
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_MASK      0x01000000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_OFFSET                 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_LSB                    25
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_MASK                   0x02000000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_OFFSET                  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_LSB                     26
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_MASK                    0x04000000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_LSB  28
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_OFFSET             0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_LSB                29
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_MASK               0x20000000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_OFFSET                   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_LSB                      30
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_MASK                     0x40000000
+
+#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_OFFSET         0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_LSB            31
+#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_MASK           0x80000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_OFFSET        0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_MASK          0x0000ffff
+
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_OFFSET                         0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_LSB                            16
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_MASK                           0x00010000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_LSB    19
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_MASK   0x00080000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_OFFSET         0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_LSB            20
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_MASK           0x00100000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_OFFSET                          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_LSB                             21
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_MASK                            0x00600000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_OFFSET                         0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_LSB                            23
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_MASK                           0x00800000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_OFFSET                         0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_LSB                            24
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_MASK                           0x01000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_OFFSET                 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_LSB                    25
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_MASK                   0x02000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_OFFSET                    0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_LSB                       26
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_MASK                      0x04000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_OFFSET             0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_LSB                27
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_MASK               0x08000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_OFFSET            0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_LSB               28
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_MASK              0x10000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_OFFSET          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_LSB             29
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_MASK            0x20000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_OFFSET          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_LSB             30
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_MASK            0x40000000
+
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_OFFSET           0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_LSB              31
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_MASK             0x80000000
+
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_OFFSET              0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_LSB                 0
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_MASK                0x000000ff
+
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_OFFSET                     0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_LSB                        8
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_MASK                       0x00000300
+
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_OFFSET                        0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_LSB                           10
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_MASK                          0x00000400
+
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_OFFSET                         0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_LSB                            11
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_MASK                           0x007ff800
+
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET  0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_LSB     23
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_MASK    0x00800000
+
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_OFFSET      0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_LSB         24
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_MASK        0x01000000
+
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_OFFSET                    0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_LSB                       25
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_MASK                      0x02000000
+
+#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_OFFSET            0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_LSB               26
+#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_MASK              0x04000000
+
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_OFFSET                 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_LSB                    27
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_MASK                   0xf8000000
+
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_OFFSET                     0x00000014
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_LSB                        0
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_MASK                       0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_OFFSET                    0x00000018
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_LSB                       0
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_MASK                      0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_OFFSET                    0x0000001c
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_LSB                       0
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_MASK                      0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_OFFSET                   0x00000020
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_LSB                      0
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_MASK                     0xffffffff
+
+#endif

hw/wcn6450/v1/reo_update_rx_reo_queue_status.h

@@ -0,0 +1,175 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25
+
+struct reo_update_rx_reo_queue_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t reserved_2a                     : 32;
+             uint32_t reserved_3a                     : 32;
+             uint32_t reserved_4a                     : 32;
+             uint32_t reserved_5a                     : 32;
+             uint32_t reserved_6a                     : 32;
+             uint32_t reserved_7a                     : 32;
+             uint32_t reserved_8a                     : 32;
+             uint32_t reserved_9a                     : 32;
+             uint32_t reserved_10a                    : 32;
+             uint32_t reserved_11a                    : 32;
+             uint32_t reserved_12a                    : 32;
+             uint32_t reserved_13a                    : 32;
+             uint32_t reserved_14a                    : 32;
+             uint32_t reserved_15a                    : 32;
+             uint32_t reserved_16a                    : 32;
+             uint32_t reserved_17a                    : 32;
+             uint32_t reserved_18a                    : 32;
+             uint32_t reserved_19a                    : 32;
+             uint32_t reserved_20a                    : 32;
+             uint32_t reserved_21a                    : 32;
+             uint32_t reserved_22a                    : 32;
+             uint32_t reserved_23a                    : 32;
+             uint32_t reserved_24a                    : 28,
+                      looping_count                   :  4;
+};
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET          0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET          0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET          0x00000014
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET          0x00000018
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET          0x0000001c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET          0x00000020
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET          0x00000024
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET        0x00000028
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK          0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET        0x0000002c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK          0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET        0x00000030
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK          0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET        0x00000034
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK          0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET        0x00000038
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK          0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET        0x0000003c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK          0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET        0x00000040
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK          0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET        0x00000044
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK          0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET        0x00000048
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK          0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET        0x0000004c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK          0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET        0x00000050
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK          0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET        0x00000054
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK          0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET        0x00000058
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK          0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET        0x0000005c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK          0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET        0x00000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB           0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK          0x0fffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET       0x00000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB          28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK         0xf0000000
+
+#endif

hw/wcn6450/v1/rx_attention.h

@@ -0,0 +1,282 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_ATTENTION_H_
+#define _RX_ATTENTION_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_ATTENTION 3
+
+struct rx_attention {
+             uint32_t rxpcu_mpdu_filter_in_category   :  2,
+                      sw_frame_group_id               :  7,
+                      reserved_0                      :  7,
+                      phy_ppdu_id                     : 16;
+             uint32_t first_mpdu                      :  1,
+                      reserved_1a                     :  1,
+                      mcast_bcast                     :  1,
+                      ast_index_not_found             :  1,
+                      ast_index_timeout               :  1,
+                      power_mgmt                      :  1,
+                      non_qos                         :  1,
+                      null_data                       :  1,
+                      mgmt_type                       :  1,
+                      ctrl_type                       :  1,
+                      more_data                       :  1,
+                      eosp                            :  1,
+                      a_msdu_error                    :  1,
+                      fragment_flag                   :  1,
+                      order                           :  1,
+                      cce_match                       :  1,
+                      overflow_err                    :  1,
+                      msdu_length_err                 :  1,
+                      tcp_udp_chksum_fail             :  1,
+                      ip_chksum_fail                  :  1,
+                      sa_idx_invalid                  :  1,
+                      da_idx_invalid                  :  1,
+                      reserved_1b                     :  1,
+                      rx_in_tx_decrypt_byp            :  1,
+                      encrypt_required                :  1,
+                      directed                        :  1,
+                      buffer_fragment                 :  1,
+                      mpdu_length_err                 :  1,
+                      tkip_mic_err                    :  1,
+                      decrypt_err                     :  1,
+                      unencrypted_frame_err           :  1,
+                      fcs_err                         :  1;
+             uint32_t flow_idx_timeout                :  1,
+                      flow_idx_invalid                :  1,
+                      wifi_parser_error               :  1,
+                      amsdu_parser_error              :  1,
+                      sa_idx_timeout                  :  1,
+                      da_idx_timeout                  :  1,
+                      msdu_limit_error                :  1,
+                      da_is_valid                     :  1,
+                      da_is_mcbc                      :  1,
+                      sa_is_valid                     :  1,
+                      decrypt_status_code             :  3,
+                      rx_bitmap_not_updated           :  1,
+                      reserved_2                      : 17,
+                      msdu_done                       :  1;
+};
+
+#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET          0x00000000
+#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB             0
+#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK            0x00000003
+
+#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET                      0x00000000
+#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB                         2
+#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK                        0x000001fc
+
+#define RX_ATTENTION_0_RESERVED_0_OFFSET                             0x00000000
+#define RX_ATTENTION_0_RESERVED_0_LSB                                9
+#define RX_ATTENTION_0_RESERVED_0_MASK                               0x0000fe00
+
+#define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET                            0x00000000
+#define RX_ATTENTION_0_PHY_PPDU_ID_LSB                               16
+#define RX_ATTENTION_0_PHY_PPDU_ID_MASK                              0xffff0000
+
+#define RX_ATTENTION_1_FIRST_MPDU_OFFSET                             0x00000004
+#define RX_ATTENTION_1_FIRST_MPDU_LSB                                0
+#define RX_ATTENTION_1_FIRST_MPDU_MASK                               0x00000001
+
+#define RX_ATTENTION_1_RESERVED_1A_OFFSET                            0x00000004
+#define RX_ATTENTION_1_RESERVED_1A_LSB                               1
+#define RX_ATTENTION_1_RESERVED_1A_MASK                              0x00000002
+
+#define RX_ATTENTION_1_MCAST_BCAST_OFFSET                            0x00000004
+#define RX_ATTENTION_1_MCAST_BCAST_LSB                               2
+#define RX_ATTENTION_1_MCAST_BCAST_MASK                              0x00000004
+
+#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET                    0x00000004
+#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB                       3
+#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK                      0x00000008
+
+#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET                      0x00000004
+#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB                         4
+#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK                        0x00000010
+
+#define RX_ATTENTION_1_POWER_MGMT_OFFSET                             0x00000004
+#define RX_ATTENTION_1_POWER_MGMT_LSB                                5
+#define RX_ATTENTION_1_POWER_MGMT_MASK                               0x00000020
+
+#define RX_ATTENTION_1_NON_QOS_OFFSET                                0x00000004
+#define RX_ATTENTION_1_NON_QOS_LSB                                   6
+#define RX_ATTENTION_1_NON_QOS_MASK                                  0x00000040
+
+#define RX_ATTENTION_1_NULL_DATA_OFFSET                              0x00000004
+#define RX_ATTENTION_1_NULL_DATA_LSB                                 7
+#define RX_ATTENTION_1_NULL_DATA_MASK                                0x00000080
+
+#define RX_ATTENTION_1_MGMT_TYPE_OFFSET                              0x00000004
+#define RX_ATTENTION_1_MGMT_TYPE_LSB                                 8
+#define RX_ATTENTION_1_MGMT_TYPE_MASK                                0x00000100
+
+#define RX_ATTENTION_1_CTRL_TYPE_OFFSET                              0x00000004
+#define RX_ATTENTION_1_CTRL_TYPE_LSB                                 9
+#define RX_ATTENTION_1_CTRL_TYPE_MASK                                0x00000200
+
+#define RX_ATTENTION_1_MORE_DATA_OFFSET                              0x00000004
+#define RX_ATTENTION_1_MORE_DATA_LSB                                 10
+#define RX_ATTENTION_1_MORE_DATA_MASK                                0x00000400
+
+#define RX_ATTENTION_1_EOSP_OFFSET                                   0x00000004
+#define RX_ATTENTION_1_EOSP_LSB                                      11
+#define RX_ATTENTION_1_EOSP_MASK                                     0x00000800
+
+#define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET                           0x00000004
+#define RX_ATTENTION_1_A_MSDU_ERROR_LSB                              12
+#define RX_ATTENTION_1_A_MSDU_ERROR_MASK                             0x00001000
+
+#define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET                          0x00000004
+#define RX_ATTENTION_1_FRAGMENT_FLAG_LSB                             13
+#define RX_ATTENTION_1_FRAGMENT_FLAG_MASK                            0x00002000
+
+#define RX_ATTENTION_1_ORDER_OFFSET                                  0x00000004
+#define RX_ATTENTION_1_ORDER_LSB                                     14
+#define RX_ATTENTION_1_ORDER_MASK                                    0x00004000
+
+#define RX_ATTENTION_1_CCE_MATCH_OFFSET                              0x00000004
+#define RX_ATTENTION_1_CCE_MATCH_LSB                                 15
+#define RX_ATTENTION_1_CCE_MATCH_MASK                                0x00008000
+
+#define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET                           0x00000004
+#define RX_ATTENTION_1_OVERFLOW_ERR_LSB                              16
+#define RX_ATTENTION_1_OVERFLOW_ERR_MASK                             0x00010000
+
+#define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET                        0x00000004
+#define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB                           17
+#define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK                          0x00020000
+
+#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET                    0x00000004
+#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB                       18
+#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK                      0x00040000
+
+#define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET                         0x00000004
+#define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB                            19
+#define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK                           0x00080000
+
+#define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET                         0x00000004
+#define RX_ATTENTION_1_SA_IDX_INVALID_LSB                            20
+#define RX_ATTENTION_1_SA_IDX_INVALID_MASK                           0x00100000
+
+#define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET                         0x00000004
+#define RX_ATTENTION_1_DA_IDX_INVALID_LSB                            21
+#define RX_ATTENTION_1_DA_IDX_INVALID_MASK                           0x00200000
+
+#define RX_ATTENTION_1_RESERVED_1B_OFFSET                            0x00000004
+#define RX_ATTENTION_1_RESERVED_1B_LSB                               22
+#define RX_ATTENTION_1_RESERVED_1B_MASK                              0x00400000
+
+#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET                   0x00000004
+#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB                      23
+#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK                     0x00800000
+
+#define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET                       0x00000004
+#define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB                          24
+#define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK                         0x01000000
+
+#define RX_ATTENTION_1_DIRECTED_OFFSET                               0x00000004
+#define RX_ATTENTION_1_DIRECTED_LSB                                  25
+#define RX_ATTENTION_1_DIRECTED_MASK                                 0x02000000
+
+#define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET                        0x00000004
+#define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB                           26
+#define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK                          0x04000000
+
+#define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET                        0x00000004
+#define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB                           27
+#define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK                          0x08000000
+
+#define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET                           0x00000004
+#define RX_ATTENTION_1_TKIP_MIC_ERR_LSB                              28
+#define RX_ATTENTION_1_TKIP_MIC_ERR_MASK                             0x10000000
+
+#define RX_ATTENTION_1_DECRYPT_ERR_OFFSET                            0x00000004
+#define RX_ATTENTION_1_DECRYPT_ERR_LSB                               29
+#define RX_ATTENTION_1_DECRYPT_ERR_MASK                              0x20000000
+
+#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET                  0x00000004
+#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB                     30
+#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK                    0x40000000
+
+#define RX_ATTENTION_1_FCS_ERR_OFFSET                                0x00000004
+#define RX_ATTENTION_1_FCS_ERR_LSB                                   31
+#define RX_ATTENTION_1_FCS_ERR_MASK                                  0x80000000
+
+#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET                       0x00000008
+#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB                          0
+#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK                         0x00000001
+
+#define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET                       0x00000008
+#define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB                          1
+#define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK                         0x00000002
+
+#define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET                      0x00000008
+#define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB                         2
+#define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK                        0x00000004
+
+#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET                     0x00000008
+#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB                        3
+#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK                       0x00000008
+
+#define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET                         0x00000008
+#define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB                            4
+#define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK                           0x00000010
+
+#define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET                         0x00000008
+#define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB                            5
+#define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK                           0x00000020
+
+#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET                       0x00000008
+#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB                          6
+#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK                         0x00000040
+
+#define RX_ATTENTION_2_DA_IS_VALID_OFFSET                            0x00000008
+#define RX_ATTENTION_2_DA_IS_VALID_LSB                               7
+#define RX_ATTENTION_2_DA_IS_VALID_MASK                              0x00000080
+
+#define RX_ATTENTION_2_DA_IS_MCBC_OFFSET                             0x00000008
+#define RX_ATTENTION_2_DA_IS_MCBC_LSB                                8
+#define RX_ATTENTION_2_DA_IS_MCBC_MASK                               0x00000100
+
+#define RX_ATTENTION_2_SA_IS_VALID_OFFSET                            0x00000008
+#define RX_ATTENTION_2_SA_IS_VALID_LSB                               9
+#define RX_ATTENTION_2_SA_IS_VALID_MASK                              0x00000200
+
+#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET                    0x00000008
+#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB                       10
+#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK                      0x00001c00
+
+#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET                  0x00000008
+#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB                     13
+#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK                    0x00002000
+
+#define RX_ATTENTION_2_RESERVED_2_OFFSET                             0x00000008
+#define RX_ATTENTION_2_RESERVED_2_LSB                                14
+#define RX_ATTENTION_2_RESERVED_2_MASK                               0x7fffc000
+
+#define RX_ATTENTION_2_MSDU_DONE_OFFSET                              0x00000008
+#define RX_ATTENTION_2_MSDU_DONE_LSB                                 31
+#define RX_ATTENTION_2_MSDU_DONE_MASK                                0x80000000
+
+#endif

hw/wcn6450/v1/rx_flow_search_entry.h

@@ -0,0 +1,157 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_FLOW_SEARCH_ENTRY_H_
+#define _RX_FLOW_SEARCH_ENTRY_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16
+
+struct rx_flow_search_entry {
+             uint32_t src_ip_127_96                   : 32;
+             uint32_t src_ip_95_64                    : 32;
+             uint32_t src_ip_63_32                    : 32;
+             uint32_t src_ip_31_0                     : 32;
+             uint32_t dest_ip_127_96                  : 32;
+             uint32_t dest_ip_95_64                   : 32;
+             uint32_t dest_ip_63_32                   : 32;
+             uint32_t dest_ip_31_0                    : 32;
+             uint32_t src_port                        : 16,
+                      dest_port                       : 16;
+             uint32_t l4_protocol                     :  8,
+                      valid                           :  1,
+                      reserved_9                      : 15,
+                      reo_destination_indication      :  5,
+                      msdu_drop                       :  1,
+                      reo_destination_handler         :  2;
+             uint32_t metadata                        : 32;
+             uint32_t aggregation_count               :  7,
+                      lro_eligible                    :  1,
+                      msdu_count                      : 24;
+             uint32_t msdu_byte_count                 : 32;
+             uint32_t timestamp                       : 32;
+             uint32_t cumulative_l4_checksum          : 16,
+                      cumulative_ip_length            : 16;
+             uint32_t tcp_sequence_number             : 32;
+};
+
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_OFFSET                  0x00000000
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_LSB                     0
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_MASK                    0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_OFFSET                   0x00000004
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_LSB                      0
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_MASK                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_OFFSET                   0x00000008
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_LSB                      0
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_MASK                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_OFFSET                    0x0000000c
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_LSB                       0
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_MASK                      0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_OFFSET                 0x00000010
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_LSB                    0
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_MASK                   0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_OFFSET                  0x00000014
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_LSB                     0
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_MASK                    0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_OFFSET                  0x00000018
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_LSB                     0
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_MASK                    0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_OFFSET                   0x0000001c
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_LSB                      0
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_MASK                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_OFFSET                       0x00000020
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_LSB                          0
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_MASK                         0x0000ffff
+
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_OFFSET                      0x00000020
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_LSB                         16
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_MASK                        0xffff0000
+
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_OFFSET                    0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_LSB                       0
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_MASK                      0x000000ff
+
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_OFFSET                          0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_LSB                             8
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_MASK                            0x00000100
+
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_OFFSET                     0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_LSB                        9
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_MASK                       0x00fffe00
+
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_OFFSET     0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_LSB        24
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_MASK       0x1f000000
+
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_OFFSET                      0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_LSB                         29
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_MASK                        0x20000000
+
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_OFFSET        0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_LSB           30
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_MASK          0xc0000000
+
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_OFFSET                      0x00000028
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_LSB                         0
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_MASK                        0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_OFFSET             0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_LSB                0
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_MASK               0x0000007f
+
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_OFFSET                  0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_LSB                     7
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_MASK                    0x00000080
+
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_OFFSET                    0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_LSB                       8
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_MASK                      0xffffff00
+
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_OFFSET               0x00000030
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_LSB                  0
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_MASK                 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_OFFSET                     0x00000034
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_LSB                        0
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_MASK                       0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_OFFSET        0x00000038
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_LSB           0
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_MASK          0x0000ffff
+
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_OFFSET          0x00000038
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_LSB             16
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_MASK            0xffff0000
+
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_OFFSET           0x0000003c
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_LSB              0
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_MASK             0xffffffff
+
+#endif

hw/wcn6450/v1/rx_location_info.h

@@ -0,0 +1,207 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_LOCATION_INFO_H_
+#define _RX_LOCATION_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_LOCATION_INFO 9
+
+struct rx_location_info {
+             uint32_t rtt_fac_legacy                  : 16,
+                      rtt_fac_legacy_ext80            : 16;
+             uint32_t rtt_fac_vht                     : 16,
+                      rtt_fac_vht_ext80               : 16;
+             uint32_t rtt_fac_legacy_status           :  1,
+                      rtt_fac_legacy_ext80_status     :  1,
+                      rtt_fac_vht_status              :  1,
+                      rtt_fac_vht_ext80_status        :  1,
+                      rtt_fac_sifs                    : 12,
+                      rtt_fac_sifs_status             :  2,
+                      rtt_cfr_status                  :  1,
+                      rtt_cir_status                  :  1,
+                      rtt_channel_dump_size           : 11,
+                      rtt_hw_ifft_mode                :  1;
+             uint32_t rtt_btcf_status                 :  1,
+                      rtt_preamble_type               :  5,
+                      rtt_pkt_bw_leg                  :  2,
+                      rtt_pkt_bw_vht                  :  2,
+                      rtt_gi_type                     :  2,
+                      rtt_mcs_rate                    :  5,
+                      rtt_strongest_chain             :  3,
+                      rtt_strongest_chain_ext80       :  3,
+                      rtt_rx_chain_mask               :  8,
+                      reserved_3                      :  1;
+             uint32_t rx_start_ts                     : 32;
+             uint32_t rx_end_ts                       : 32;
+             uint32_t sfo_phase_pkt_start             : 12,
+                      sfo_phase_pkt_end               : 12,
+                      rtt_che_buffer_pointer_high8    :  8;
+             uint32_t rtt_che_buffer_pointer_low32    : 32;
+             uint32_t rtt_cfo_measurement             : 14,
+                      rtt_chan_spread                 :  8,
+                      rtt_timing_backoff_sel          :  2,
+                      reserved_8                      :  7,
+                      rx_location_info_valid          :  1;
+};
+
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_OFFSET                     0x00000000
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_LSB                        0
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_MASK                       0x0000ffff
+
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_OFFSET               0x00000000
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_LSB                  16
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_MASK                 0xffff0000
+
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_OFFSET                        0x00000004
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_LSB                           0
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_MASK                          0x0000ffff
+
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_OFFSET                  0x00000004
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_LSB                     16
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_MASK                    0xffff0000
+
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_OFFSET              0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_LSB                 0
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_MASK                0x00000001
+
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET        0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_LSB           1
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_MASK          0x00000002
+
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_OFFSET                 0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_LSB                    2
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_MASK                   0x00000004
+
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_OFFSET           0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_LSB              3
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_MASK             0x00000008
+
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_OFFSET                       0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_LSB                          4
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_MASK                         0x0000fff0
+
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_OFFSET                0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_LSB                   16
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_MASK                  0x00030000
+
+#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_OFFSET                     0x00000008
+#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_LSB                        18
+#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_MASK                       0x00040000
+
+#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_OFFSET                     0x00000008
+#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_LSB                        19
+#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_MASK                       0x00080000
+
+#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_OFFSET              0x00000008
+#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_LSB                 20
+#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_MASK                0x7ff00000
+
+#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_OFFSET                   0x00000008
+#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_LSB                      31
+#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_MASK                     0x80000000
+
+#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_OFFSET                    0x0000000c
+#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_LSB                       0
+#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_MASK                      0x00000001
+
+#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_OFFSET                  0x0000000c
+#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_LSB                     1
+#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_MASK                    0x0000003e
+
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_OFFSET                     0x0000000c
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_LSB                        6
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_MASK                       0x000000c0
+
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_OFFSET                     0x0000000c
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_LSB                        8
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_MASK                       0x00000300
+
+#define RX_LOCATION_INFO_3_RTT_GI_TYPE_OFFSET                        0x0000000c
+#define RX_LOCATION_INFO_3_RTT_GI_TYPE_LSB                           10
+#define RX_LOCATION_INFO_3_RTT_GI_TYPE_MASK                          0x00000c00
+
+#define RX_LOCATION_INFO_3_RTT_MCS_RATE_OFFSET                       0x0000000c
+#define RX_LOCATION_INFO_3_RTT_MCS_RATE_LSB                          12
+#define RX_LOCATION_INFO_3_RTT_MCS_RATE_MASK                         0x0001f000
+
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_OFFSET                0x0000000c
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_LSB                   17
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_MASK                  0x000e0000
+
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_OFFSET          0x0000000c
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_LSB             20
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_MASK            0x00700000
+
+#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_OFFSET                  0x0000000c
+#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_LSB                     23
+#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_MASK                    0x7f800000
+
+#define RX_LOCATION_INFO_3_RESERVED_3_OFFSET                         0x0000000c
+#define RX_LOCATION_INFO_3_RESERVED_3_LSB                            31
+#define RX_LOCATION_INFO_3_RESERVED_3_MASK                           0x80000000
+
+#define RX_LOCATION_INFO_4_RX_START_TS_OFFSET                        0x00000010
+#define RX_LOCATION_INFO_4_RX_START_TS_LSB                           0
+#define RX_LOCATION_INFO_4_RX_START_TS_MASK                          0xffffffff
+
+#define RX_LOCATION_INFO_5_RX_END_TS_OFFSET                          0x00000014
+#define RX_LOCATION_INFO_5_RX_END_TS_LSB                             0
+#define RX_LOCATION_INFO_5_RX_END_TS_MASK                            0xffffffff
+
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_OFFSET                0x00000018
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_LSB                   0
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_MASK                  0x00000fff
+
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_OFFSET                  0x00000018
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_LSB                     12
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_MASK                    0x00fff000
+
+#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET       0x00000018
+#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_LSB          24
+#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_MASK         0xff000000
+
+#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET       0x0000001c
+#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_LSB          0
+#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_MASK         0xffffffff
+
+#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_OFFSET                0x00000020
+#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_LSB                   0
+#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_MASK                  0x00003fff
+
+#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_OFFSET                    0x00000020
+#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_LSB                       14
+#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_MASK                      0x003fc000
+
+#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_OFFSET             0x00000020
+#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_LSB                22
+#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_MASK               0x00c00000
+
+#define RX_LOCATION_INFO_8_RESERVED_8_OFFSET                         0x00000020
+#define RX_LOCATION_INFO_8_RESERVED_8_LSB                            24
+#define RX_LOCATION_INFO_8_RESERVED_8_MASK                           0x7f000000
+
+#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_OFFSET             0x00000020
+#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_LSB                31
+#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_MASK               0x80000000
+
+#endif

hw/wcn6450/v1/rx_mpdu_desc_info.h

@@ -0,0 +1,107 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MPDU_DESC_INFO_H_
+#define _RX_MPDU_DESC_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2
+
+struct rx_mpdu_desc_info {
+             uint32_t msdu_count                      :  8,
+                      mpdu_sequence_number            : 12,
+                      fragment_flag                   :  1,
+                      mpdu_retry_bit                  :  1,
+                      ampdu_flag                      :  1,
+                      bar_frame                       :  1,
+                      pn_fields_contain_valid_info    :  1,
+                      sa_is_valid                     :  1,
+                      sa_idx_timeout                  :  1,
+                      da_is_valid                     :  1,
+                      da_is_mcbc                      :  1,
+                      da_idx_timeout                  :  1,
+                      raw_mpdu                        :  1,
+                      more_fragment_flag              :  1;
+             uint32_t peer_meta_data                  : 32;
+};
+
+#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET                        0x00000000
+#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB                           0
+#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK                          0x000000ff
+
+#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET              0x00000000
+#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB                 8
+#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK                0x000fff00
+
+#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET                     0x00000000
+#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_LSB                        20
+#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK                       0x00100000
+
+#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET                    0x00000000
+#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_LSB                       21
+#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK                      0x00200000
+
+#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET                        0x00000000
+#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_LSB                           22
+#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK                          0x00400000
+
+#define RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET                         0x00000000
+#define RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB                            23
+#define RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK                           0x00800000
+
+#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET      0x00000000
+#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_LSB         24
+#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_MASK        0x01000000
+
+#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_OFFSET                       0x00000000
+#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_LSB                          25
+#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_MASK                         0x02000000
+
+#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET                    0x00000000
+#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB                       26
+#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK                      0x04000000
+
+#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_OFFSET                       0x00000000
+#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_LSB                          27
+#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_MASK                         0x08000000
+
+#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_OFFSET                        0x00000000
+#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_LSB                           28
+#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_MASK                          0x10000000
+
+#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET                    0x00000000
+#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB                       29
+#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK                      0x20000000
+
+#define RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET                          0x00000000
+#define RX_MPDU_DESC_INFO_0_RAW_MPDU_LSB                             30
+#define RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK                            0x40000000
+
+#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_OFFSET                0x00000000
+#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_LSB                   31
+#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_MASK                  0x80000000
+
+#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET                    0x00000004
+#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB                       0
+#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK                      0xffffffff
+
+#endif

hw/wcn6450/v1/rx_mpdu_details.h

@@ -0,0 +1,113 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MPDU_DETAILS_H_
+#define _RX_MPDU_DETAILS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "rx_mpdu_desc_info.h"
+
+#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4
+
+struct rx_mpdu_details {
+    struct            buffer_addr_info                       msdu_link_desc_addr_info;
+    struct            rx_mpdu_desc_info                       rx_mpdu_desc_info_details;
+};
+
+#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB   0
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK  0x000000ff
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB   22
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK  0x00400000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB    23
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK   0x00800000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB  25
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB  27
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB   28
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK  0x10000000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET  0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB     30
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK    0x40000000
+
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
+
+#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#endif

hw/wcn6450/v1/rx_mpdu_end.h

@@ -0,0 +1,132 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MPDU_END_H_
+#define _RX_MPDU_END_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_MPDU_END 2
+
+struct rx_mpdu_end {
+             uint32_t rxpcu_mpdu_filter_in_category   :  2,
+                      sw_frame_group_id               :  7,
+                      reserved_0                      :  7,
+                      phy_ppdu_id                     : 16;
+             uint32_t reserved_1a                     : 11,
+                      unsup_ktype_short_frame         :  1,
+                      rx_in_tx_decrypt_byp            :  1,
+                      overflow_err                    :  1,
+                      mpdu_length_err                 :  1,
+                      tkip_mic_err                    :  1,
+                      decrypt_err                     :  1,
+                      unencrypted_frame_err           :  1,
+                      pn_fields_contain_valid_info    :  1,
+                      fcs_err                         :  1,
+                      msdu_length_err                 :  1,
+                      rxdma0_destination_ring         :  2,
+                      rxdma1_destination_ring         :  2,
+                      decrypt_status_code             :  3,
+                      rx_bitmap_not_updated           :  1,
+                      reserved_1b                     :  3;
+};
+
+#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET           0x00000000
+#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB              0
+#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK             0x00000003
+
+#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET                       0x00000000
+#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB                          2
+#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK                         0x000001fc
+
+#define RX_MPDU_END_0_RESERVED_0_OFFSET                              0x00000000
+#define RX_MPDU_END_0_RESERVED_0_LSB                                 9
+#define RX_MPDU_END_0_RESERVED_0_MASK                                0x0000fe00
+
+#define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET                             0x00000000
+#define RX_MPDU_END_0_PHY_PPDU_ID_LSB                                16
+#define RX_MPDU_END_0_PHY_PPDU_ID_MASK                               0xffff0000
+
+#define RX_MPDU_END_1_RESERVED_1A_OFFSET                             0x00000004
+#define RX_MPDU_END_1_RESERVED_1A_LSB                                0
+#define RX_MPDU_END_1_RESERVED_1A_MASK                               0x000007ff
+
+#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET                 0x00000004
+#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB                    11
+#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK                   0x00000800
+
+#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET                    0x00000004
+#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB                       12
+#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK                      0x00001000
+
+#define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET                            0x00000004
+#define RX_MPDU_END_1_OVERFLOW_ERR_LSB                               13
+#define RX_MPDU_END_1_OVERFLOW_ERR_MASK                              0x00002000
+
+#define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET                         0x00000004
+#define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB                            14
+#define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK                           0x00004000
+
+#define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET                            0x00000004
+#define RX_MPDU_END_1_TKIP_MIC_ERR_LSB                               15
+#define RX_MPDU_END_1_TKIP_MIC_ERR_MASK                              0x00008000
+
+#define RX_MPDU_END_1_DECRYPT_ERR_OFFSET                             0x00000004
+#define RX_MPDU_END_1_DECRYPT_ERR_LSB                                16
+#define RX_MPDU_END_1_DECRYPT_ERR_MASK                               0x00010000
+
+#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET                   0x00000004
+#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB                      17
+#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK                     0x00020000
+
+#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET            0x00000004
+#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB               18
+#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK              0x00040000
+
+#define RX_MPDU_END_1_FCS_ERR_OFFSET                                 0x00000004
+#define RX_MPDU_END_1_FCS_ERR_LSB                                    19
+#define RX_MPDU_END_1_FCS_ERR_MASK                                   0x00080000
+
+#define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET                         0x00000004
+#define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB                            20
+#define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK                           0x00100000
+
+#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET                 0x00000004
+#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB                    21
+#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK                   0x00600000
+
+#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET                 0x00000004
+#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB                    23
+#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK                   0x01800000
+
+#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET                     0x00000004
+#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB                        25
+#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK                       0x0e000000
+
+#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET                   0x00000004
+#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB                      28
+#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK                     0x10000000
+
+#define RX_MPDU_END_1_RESERVED_1B_OFFSET                             0x00000004
+#define RX_MPDU_END_1_RESERVED_1B_LSB                                29
+#define RX_MPDU_END_1_RESERVED_1B_MASK                               0xe0000000
+
+#endif

hw/wcn6450/v1/rx_mpdu_info.h

@@ -0,0 +1,537 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MPDU_INFO_H_
+#define _RX_MPDU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rxpt_classify_info.h"
+
+#define NUM_OF_DWORDS_RX_MPDU_INFO 23
+
+struct rx_mpdu_info {
+    struct            rxpt_classify_info                       rxpt_classify_info_details;
+             uint32_t rx_reo_queue_desc_addr_31_0     : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32    :  8,
+                      receive_queue_number            : 16,
+                      pre_delim_err_warning           :  1,
+                      first_delim_err                 :  1,
+                      reserved_2a                     :  6;
+             uint32_t pn_31_0                         : 32;
+             uint32_t pn_63_32                        : 32;
+             uint32_t pn_95_64                        : 32;
+             uint32_t pn_127_96                       : 32;
+             uint32_t epd_en                          :  1,
+                      all_frames_shall_be_encrypted   :  1,
+                      encrypt_type                    :  4,
+                      wep_key_width_for_variable_key  :  2,
+                      __reserved_g_0003                        :  2,
+                      bssid_hit                       :  1,
+                      bssid_number                    :  4,
+                      tid                             :  4,
+                      reserved_7a                     : 13;
+             uint32_t peer_meta_data                  : 32;
+             uint32_t rxpcu_mpdu_filter_in_category   :  2,
+                      sw_frame_group_id               :  7,
+                      ndp_frame                       :  1,
+                      phy_err                         :  1,
+                      phy_err_during_mpdu_header      :  1,
+                      protocol_version_err            :  1,
+                      ast_based_lookup_valid          :  1,
+                      reserved_9a                     :  2,
+                      phy_ppdu_id                     : 16;
+             uint32_t ast_index                       : 16,
+                      sw_peer_id                      : 16;
+             uint32_t mpdu_frame_control_valid        :  1,
+                      mpdu_duration_valid             :  1,
+                      mac_addr_ad1_valid              :  1,
+                      mac_addr_ad2_valid              :  1,
+                      mac_addr_ad3_valid              :  1,
+                      mac_addr_ad4_valid              :  1,
+                      mpdu_sequence_control_valid     :  1,
+                      mpdu_qos_control_valid          :  1,
+                      mpdu_ht_control_valid           :  1,
+                      frame_encryption_info_valid     :  1,
+                      mpdu_fragment_number            :  4,
+                      more_fragment_flag              :  1,
+                      reserved_11a                    :  1,
+                      fr_ds                           :  1,
+                      to_ds                           :  1,
+                      encrypted                       :  1,
+                      mpdu_retry                      :  1,
+                      mpdu_sequence_number            : 12;
+             uint32_t key_id_octet                    :  8,
+                      new_peer_entry                  :  1,
+                      decrypt_needed                  :  1,
+                      decap_type                      :  2,
+                      rx_insert_vlan_c_tag_padding    :  1,
+                      rx_insert_vlan_s_tag_padding    :  1,
+                      strip_vlan_c_tag_decap          :  1,
+                      strip_vlan_s_tag_decap          :  1,
+                      pre_delim_count                 : 12,
+                      ampdu_flag                      :  1,
+                      bar_frame                       :  1,
+                      raw_mpdu                        :  1,
+                      reserved_12                     :  1;
+             uint32_t mpdu_length                     : 14,
+                      first_mpdu                      :  1,
+                      mcast_bcast                     :  1,
+                      ast_index_not_found             :  1,
+                      ast_index_timeout               :  1,
+                      power_mgmt                      :  1,
+                      non_qos                         :  1,
+                      null_data                       :  1,
+                      mgmt_type                       :  1,
+                      ctrl_type                       :  1,
+                      more_data                       :  1,
+                      eosp                            :  1,
+                      fragment_flag                   :  1,
+                      order                           :  1,
+                      u_apsd_trigger                  :  1,
+                      encrypt_required                :  1,
+                      directed                        :  1,
+                      amsdu_present                   :  1,
+                      reserved_13                     :  1;
+             uint32_t mpdu_frame_control_field        : 16,
+                      mpdu_duration_field             : 16;
+             uint32_t mac_addr_ad1_31_0               : 32;
+             uint32_t mac_addr_ad1_47_32              : 16,
+                      mac_addr_ad2_15_0               : 16;
+             uint32_t mac_addr_ad2_47_16              : 32;
+             uint32_t mac_addr_ad3_31_0               : 32;
+             uint32_t mac_addr_ad3_47_32              : 16,
+                      mpdu_sequence_control_field     : 16;
+             uint32_t mac_addr_ad4_31_0               : 32;
+             uint32_t mac_addr_ad4_47_32              : 16,
+                      mpdu_qos_control_field          : 16;
+             uint32_t mpdu_ht_control_field           : 32;
+};
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000
+
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB    15
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK   0xffff8000
+
+#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET            0x00000004
+#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB               0
+#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK              0xffffffff
+
+#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET           0x00000008
+#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB              0
+#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK             0x000000ff
+
+#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_OFFSET                   0x00000008
+#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_LSB                      8
+#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_MASK                     0x00ffff00
+
+#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_OFFSET                  0x00000008
+#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_LSB                     24
+#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_MASK                    0x01000000
+
+#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_OFFSET                        0x00000008
+#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_LSB                           25
+#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_MASK                          0x02000000
+
+#define RX_MPDU_INFO_2_RESERVED_2A_OFFSET                            0x00000008
+#define RX_MPDU_INFO_2_RESERVED_2A_LSB                               26
+#define RX_MPDU_INFO_2_RESERVED_2A_MASK                              0xfc000000
+
+#define RX_MPDU_INFO_3_PN_31_0_OFFSET                                0x0000000c
+#define RX_MPDU_INFO_3_PN_31_0_LSB                                   0
+#define RX_MPDU_INFO_3_PN_31_0_MASK                                  0xffffffff
+
+#define RX_MPDU_INFO_4_PN_63_32_OFFSET                               0x00000010
+#define RX_MPDU_INFO_4_PN_63_32_LSB                                  0
+#define RX_MPDU_INFO_4_PN_63_32_MASK                                 0xffffffff
+
+#define RX_MPDU_INFO_5_PN_95_64_OFFSET                               0x00000014
+#define RX_MPDU_INFO_5_PN_95_64_LSB                                  0
+#define RX_MPDU_INFO_5_PN_95_64_MASK                                 0xffffffff
+
+#define RX_MPDU_INFO_6_PN_127_96_OFFSET                              0x00000018
+#define RX_MPDU_INFO_6_PN_127_96_LSB                                 0
+#define RX_MPDU_INFO_6_PN_127_96_MASK                                0xffffffff
+
+#define RX_MPDU_INFO_7_EPD_EN_OFFSET                                 0x0000001c
+#define RX_MPDU_INFO_7_EPD_EN_LSB                                    0
+#define RX_MPDU_INFO_7_EPD_EN_MASK                                   0x00000001
+
+#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET          0x0000001c
+#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB             1
+#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK            0x00000002
+
+#define RX_MPDU_INFO_7_ENCRYPT_TYPE_OFFSET                           0x0000001c
+#define RX_MPDU_INFO_7_ENCRYPT_TYPE_LSB                              2
+#define RX_MPDU_INFO_7_ENCRYPT_TYPE_MASK                             0x0000003c
+
+#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET         0x0000001c
+#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB            6
+#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK           0x000000c0
+
+#define RX_MPDU_INFO_7_BSSID_HIT_OFFSET                              0x0000001c
+#define RX_MPDU_INFO_7_BSSID_HIT_LSB                                 10
+#define RX_MPDU_INFO_7_BSSID_HIT_MASK                                0x00000400
+
+#define RX_MPDU_INFO_7_BSSID_NUMBER_OFFSET                           0x0000001c
+#define RX_MPDU_INFO_7_BSSID_NUMBER_LSB                              11
+#define RX_MPDU_INFO_7_BSSID_NUMBER_MASK                             0x00007800
+
+#define RX_MPDU_INFO_7_TID_OFFSET                                    0x0000001c
+#define RX_MPDU_INFO_7_TID_LSB                                       15
+#define RX_MPDU_INFO_7_TID_MASK                                      0x00078000
+
+#define RX_MPDU_INFO_7_RESERVED_7A_OFFSET                            0x0000001c
+#define RX_MPDU_INFO_7_RESERVED_7A_LSB                               19
+#define RX_MPDU_INFO_7_RESERVED_7A_MASK                              0xfff80000
+
+#define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET                         0x00000020
+#define RX_MPDU_INFO_8_PEER_META_DATA_LSB                            0
+#define RX_MPDU_INFO_8_PEER_META_DATA_MASK                           0xffffffff
+
+#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET          0x00000024
+#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB             0
+#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK            0x00000003
+
+#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET                      0x00000024
+#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB                         2
+#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK                        0x000001fc
+
+#define RX_MPDU_INFO_9_NDP_FRAME_OFFSET                              0x00000024
+#define RX_MPDU_INFO_9_NDP_FRAME_LSB                                 9
+#define RX_MPDU_INFO_9_NDP_FRAME_MASK                                0x00000200
+
+#define RX_MPDU_INFO_9_PHY_ERR_OFFSET                                0x00000024
+#define RX_MPDU_INFO_9_PHY_ERR_LSB                                   10
+#define RX_MPDU_INFO_9_PHY_ERR_MASK                                  0x00000400
+
+#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_OFFSET             0x00000024
+#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_LSB                11
+#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_MASK               0x00000800
+
+#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_OFFSET                   0x00000024
+#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_LSB                      12
+#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_MASK                     0x00001000
+
+#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_OFFSET                 0x00000024
+#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_LSB                    13
+#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_MASK                   0x00002000
+
+#define RX_MPDU_INFO_9_RESERVED_9A_OFFSET                            0x00000024
+#define RX_MPDU_INFO_9_RESERVED_9A_LSB                               14
+#define RX_MPDU_INFO_9_RESERVED_9A_MASK                              0x0000c000
+
+#define RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET                            0x00000024
+#define RX_MPDU_INFO_9_PHY_PPDU_ID_LSB                               16
+#define RX_MPDU_INFO_9_PHY_PPDU_ID_MASK                              0xffff0000
+
+#define RX_MPDU_INFO_10_AST_INDEX_OFFSET                             0x00000028
+#define RX_MPDU_INFO_10_AST_INDEX_LSB                                0
+#define RX_MPDU_INFO_10_AST_INDEX_MASK                               0x0000ffff
+
+#define RX_MPDU_INFO_10_SW_PEER_ID_OFFSET                            0x00000028
+#define RX_MPDU_INFO_10_SW_PEER_ID_LSB                               16
+#define RX_MPDU_INFO_10_SW_PEER_ID_MASK                              0xffff0000
+
+#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET              0x0000002c
+#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB                 0
+#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK                0x00000001
+
+#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_OFFSET                   0x0000002c
+#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_LSB                      1
+#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_MASK                     0x00000002
+
+#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET                    0x0000002c
+#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB                       2
+#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK                      0x00000004
+
+#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET                    0x0000002c
+#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB                       3
+#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK                      0x00000008
+
+#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET                    0x0000002c
+#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB                       4
+#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK                      0x00000010
+
+#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET                    0x0000002c
+#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB                       5
+#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK                      0x00000020
+
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET           0x0000002c
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB              6
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK             0x00000040
+
+#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET                0x0000002c
+#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB                   7
+#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK                  0x00000080
+
+#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_OFFSET                 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_LSB                    8
+#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_MASK                   0x00000100
+
+#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET           0x0000002c
+#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB              9
+#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK             0x00000200
+
+#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_OFFSET                  0x0000002c
+#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_LSB                     10
+#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_MASK                    0x00003c00
+
+#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_OFFSET                    0x0000002c
+#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_LSB                       14
+#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_MASK                      0x00004000
+
+#define RX_MPDU_INFO_11_RESERVED_11A_OFFSET                          0x0000002c
+#define RX_MPDU_INFO_11_RESERVED_11A_LSB                             15
+#define RX_MPDU_INFO_11_RESERVED_11A_MASK                            0x00008000
+
+#define RX_MPDU_INFO_11_FR_DS_OFFSET                                 0x0000002c
+#define RX_MPDU_INFO_11_FR_DS_LSB                                    16
+#define RX_MPDU_INFO_11_FR_DS_MASK                                   0x00010000
+
+#define RX_MPDU_INFO_11_TO_DS_OFFSET                                 0x0000002c
+#define RX_MPDU_INFO_11_TO_DS_LSB                                    17
+#define RX_MPDU_INFO_11_TO_DS_MASK                                   0x00020000
+
+#define RX_MPDU_INFO_11_ENCRYPTED_OFFSET                             0x0000002c
+#define RX_MPDU_INFO_11_ENCRYPTED_LSB                                18
+#define RX_MPDU_INFO_11_ENCRYPTED_MASK                               0x00040000
+
+#define RX_MPDU_INFO_11_MPDU_RETRY_OFFSET                            0x0000002c
+#define RX_MPDU_INFO_11_MPDU_RETRY_LSB                               19
+#define RX_MPDU_INFO_11_MPDU_RETRY_MASK                              0x00080000
+
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET                  0x0000002c
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB                     20
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK                    0xfff00000
+
+#define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET                          0x00000030
+#define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB                             0
+#define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK                            0x000000ff
+
+#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET                        0x00000030
+#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB                           8
+#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK                          0x00000100
+
+#define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET                        0x00000030
+#define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB                           9
+#define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK                          0x00000200
+
+#define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET                            0x00000030
+#define RX_MPDU_INFO_12_DECAP_TYPE_LSB                               10
+#define RX_MPDU_INFO_12_DECAP_TYPE_MASK                              0x00000c00
+
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET          0x00000030
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB             12
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK            0x00001000
+
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET          0x00000030
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB             13
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK            0x00002000
+
+#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET                0x00000030
+#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB                   14
+#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK                  0x00004000
+
+#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET                0x00000030
+#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB                   15
+#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK                  0x00008000
+
+#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET                       0x00000030
+#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB                          16
+#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK                         0x0fff0000
+
+#define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET                            0x00000030
+#define RX_MPDU_INFO_12_AMPDU_FLAG_LSB                               28
+#define RX_MPDU_INFO_12_AMPDU_FLAG_MASK                              0x10000000
+
+#define RX_MPDU_INFO_12_BAR_FRAME_OFFSET                             0x00000030
+#define RX_MPDU_INFO_12_BAR_FRAME_LSB                                29
+#define RX_MPDU_INFO_12_BAR_FRAME_MASK                               0x20000000
+
+#define RX_MPDU_INFO_12_RAW_MPDU_OFFSET                              0x00000030
+#define RX_MPDU_INFO_12_RAW_MPDU_LSB                                 30
+#define RX_MPDU_INFO_12_RAW_MPDU_MASK                                0x40000000
+
+#define RX_MPDU_INFO_12_RESERVED_12_OFFSET                           0x00000030
+#define RX_MPDU_INFO_12_RESERVED_12_LSB                              31
+#define RX_MPDU_INFO_12_RESERVED_12_MASK                             0x80000000
+
+#define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET                           0x00000034
+#define RX_MPDU_INFO_13_MPDU_LENGTH_LSB                              0
+#define RX_MPDU_INFO_13_MPDU_LENGTH_MASK                             0x00003fff
+
+#define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET                            0x00000034
+#define RX_MPDU_INFO_13_FIRST_MPDU_LSB                               14
+#define RX_MPDU_INFO_13_FIRST_MPDU_MASK                              0x00004000
+
+#define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET                           0x00000034
+#define RX_MPDU_INFO_13_MCAST_BCAST_LSB                              15
+#define RX_MPDU_INFO_13_MCAST_BCAST_MASK                             0x00008000
+
+#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET                   0x00000034
+#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB                      16
+#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK                     0x00010000
+
+#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET                     0x00000034
+#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB                        17
+#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK                       0x00020000
+
+#define RX_MPDU_INFO_13_POWER_MGMT_OFFSET                            0x00000034
+#define RX_MPDU_INFO_13_POWER_MGMT_LSB                               18
+#define RX_MPDU_INFO_13_POWER_MGMT_MASK                              0x00040000
+
+#define RX_MPDU_INFO_13_NON_QOS_OFFSET                               0x00000034
+#define RX_MPDU_INFO_13_NON_QOS_LSB                                  19
+#define RX_MPDU_INFO_13_NON_QOS_MASK                                 0x00080000
+
+#define RX_MPDU_INFO_13_NULL_DATA_OFFSET                             0x00000034
+#define RX_MPDU_INFO_13_NULL_DATA_LSB                                20
+#define RX_MPDU_INFO_13_NULL_DATA_MASK                               0x00100000
+
+#define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET                             0x00000034
+#define RX_MPDU_INFO_13_MGMT_TYPE_LSB                                21
+#define RX_MPDU_INFO_13_MGMT_TYPE_MASK                               0x00200000
+
+#define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET                             0x00000034
+#define RX_MPDU_INFO_13_CTRL_TYPE_LSB                                22
+#define RX_MPDU_INFO_13_CTRL_TYPE_MASK                               0x00400000
+
+#define RX_MPDU_INFO_13_MORE_DATA_OFFSET                             0x00000034
+#define RX_MPDU_INFO_13_MORE_DATA_LSB                                23
+#define RX_MPDU_INFO_13_MORE_DATA_MASK                               0x00800000
+
+#define RX_MPDU_INFO_13_EOSP_OFFSET                                  0x00000034
+#define RX_MPDU_INFO_13_EOSP_LSB                                     24
+#define RX_MPDU_INFO_13_EOSP_MASK                                    0x01000000
+
+#define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET                         0x00000034
+#define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB                            25
+#define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK                           0x02000000
+
+#define RX_MPDU_INFO_13_ORDER_OFFSET                                 0x00000034
+#define RX_MPDU_INFO_13_ORDER_LSB                                    26
+#define RX_MPDU_INFO_13_ORDER_MASK                                   0x04000000
+
+#define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET                        0x00000034
+#define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB                           27
+#define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK                          0x08000000
+
+#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET                      0x00000034
+#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB                         28
+#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK                        0x10000000
+
+#define RX_MPDU_INFO_13_DIRECTED_OFFSET                              0x00000034
+#define RX_MPDU_INFO_13_DIRECTED_LSB                                 29
+#define RX_MPDU_INFO_13_DIRECTED_MASK                                0x20000000
+
+#define RX_MPDU_INFO_13_AMSDU_PRESENT_OFFSET                         0x00000034
+#define RX_MPDU_INFO_13_AMSDU_PRESENT_LSB                            30
+#define RX_MPDU_INFO_13_AMSDU_PRESENT_MASK                           0x40000000
+
+#define RX_MPDU_INFO_13_RESERVED_13_OFFSET                           0x00000034
+#define RX_MPDU_INFO_13_RESERVED_13_LSB                              31
+#define RX_MPDU_INFO_13_RESERVED_13_MASK                             0x80000000
+
+#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET              0x00000038
+#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB                 0
+#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK                0x0000ffff
+
+#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET                   0x00000038
+#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB                      16
+#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK                     0xffff0000
+
+#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET                     0x0000003c
+#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB                        0
+#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK                       0xffffffff
+
+#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET                    0x00000040
+#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB                       0
+#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK                      0x0000ffff
+
+#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET                     0x00000040
+#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB                        16
+#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK                       0xffff0000
+
+#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET                    0x00000044
+#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB                       0
+#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK                      0xffffffff
+
+#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET                     0x00000048
+#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB                        0
+#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK                       0xffffffff
+
+#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET                    0x0000004c
+#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB                       0
+#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK                      0x0000ffff
+
+#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET           0x0000004c
+#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB              16
+#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK             0xffff0000
+
+#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET                     0x00000050
+#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB                        0
+#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK                       0xffffffff
+
+#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET                    0x00000054
+#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB                       0
+#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK                      0x0000ffff
+
+#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET                0x00000054
+#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB                   16
+#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK                  0xffff0000
+
+#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET                 0x00000058
+#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB                    0
+#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK                   0xffffffff
+
+#endif

hw/wcn6450/v1/rx_mpdu_link_ptr.h

@@ -0,0 +1,51 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MPDU_LINK_PTR_H_
+#define _RX_MPDU_LINK_PTR_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2
+
+struct rx_mpdu_link_ptr {
+    struct            buffer_addr_info                       mpdu_link_desc_addr_info;
+};
+
+#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#endif

hw/wcn6450/v1/rx_mpdu_start.h

@@ -0,0 +1,443 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MPDU_START_H_
+#define _RX_MPDU_START_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_mpdu_info.h"
+
+#define NUM_OF_DWORDS_RX_MPDU_START 23
+
+struct rx_mpdu_start {
+    struct            rx_mpdu_info                       rx_mpdu_info_details;
+};
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000
+
+#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
+#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00
+
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000
+
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET  0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB     25
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK    0x02000000
+
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET      0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB         26
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK        0xfc000000
+
+#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET          0x0000000c
+#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_LSB             0
+#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_MASK            0xffffffff
+
+#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET         0x00000010
+#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_LSB            0
+#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_MASK           0xffffffff
+
+#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET         0x00000014
+#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_LSB            0
+#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_MASK           0xffffffff
+
+#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET        0x00000018
+#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_LSB           0
+#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_MASK          0xffffffff
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET           0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_LSB              0
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_MASK             0x00000001
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET     0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB        2
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK       0x0000003c
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET        0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB           10
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK          0x00000400
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET     0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB        11
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK       0x00007800
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_OFFSET              0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_LSB                 15
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_MASK                0x00078000
+
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET      0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB         19
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK        0xfff80000
+
+#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET   0x00000020
+#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB      0
+#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK     0xffffffff
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB   2
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK  0x000001fc
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET        0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB           9
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK          0x00000200
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET          0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB             10
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK            0x00000400
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET      0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB         14
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK        0x0000c000
+
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET      0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB         16
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK        0xffff0000
+
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET       0x00000028
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB          0
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK         0x0000ffff
+
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET      0x00000028
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB         16
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK        0xffff0000
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET    0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB       15
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK      0x00008000
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET           0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_LSB              16
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_MASK             0x00010000
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET           0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_LSB              17
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_MASK             0x00020000
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET       0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB          18
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK         0x00040000
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET      0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB         19
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK        0x00080000
+
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET    0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB       0
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK      0x000000ff
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET  0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB     8
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK    0x00000100
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET  0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB     9
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK    0x00000200
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET      0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB         10
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK        0x00000c00
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB    16
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK   0x0fff0000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET      0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB         28
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK        0x10000000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET       0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB          29
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK         0x20000000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET        0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB           30
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK          0x40000000
+
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET     0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB        31
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK       0x80000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET     0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB        0
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK       0x00003fff
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET      0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB         14
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK        0x00004000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET     0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB        15
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK       0x00008000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB  17
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET      0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB         18
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK        0x00040000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET         0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_LSB            19
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_MASK           0x00080000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET       0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB          20
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK         0x00100000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET       0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB          21
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK         0x00200000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET       0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB          22
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK         0x00400000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET       0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB          23
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK         0x00800000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_OFFSET            0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_LSB               24
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_MASK              0x01000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET   0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB      25
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK     0x02000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_OFFSET           0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_LSB              26
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_MASK             0x04000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET  0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB     27
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK    0x08000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB   28
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK  0x10000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET        0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_LSB           29
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_MASK          0x20000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET   0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB      30
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK     0x40000000
+
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET     0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB        31
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK       0x80000000
+
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff
+
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c
+#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB  0
+#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff
+
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB  16
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000
+
+#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044
+#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0
+#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff
+
+#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048
+#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB  0
+#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff
+
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050
+#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB  0
+#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff
+
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058
+#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0
+#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff
+
+#endif

hw/wcn6450/v1/rx_msdu_desc_info.h

@@ -0,0 +1,127 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MSDU_DESC_INFO_H_
+#define _RX_MSDU_DESC_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 2
+
+struct rx_msdu_desc_info {
+             uint32_t first_msdu_in_mpdu_flag         :  1,
+                      last_msdu_in_mpdu_flag          :  1,
+                      msdu_continuation               :  1,
+                      msdu_length                     : 14,
+                      reo_destination_indication      :  5,
+                      msdu_drop                       :  1,
+                      sa_is_valid                     :  1,
+                      sa_idx_timeout                  :  1,
+                      da_is_valid                     :  1,
+                      da_is_mcbc                      :  1,
+                      da_idx_timeout                  :  1,
+                      l3_header_padding_msb           :  1,
+                      tcp_udp_chksum_fail             :  1,
+                      ip_chksum_fail                  :  1,
+                      raw_mpdu                        :  1;
+             uint32_t sa_idx_or_sw_peer_id_14_0       : 15,
+                      mpdu_ast_idx_or_sw_peer_id_14_0 : 15,
+                      fr_ds                           :  1,
+                      to_ds                           :  1;
+};
+
+#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET           0x00000000
+#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB              0
+#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK             0x00000001
+
+#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET            0x00000000
+#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB               1
+#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK              0x00000002
+
+#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET                 0x00000000
+#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB                    2
+#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK                   0x00000004
+
+#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET                       0x00000000
+#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB                          3
+#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK                         0x0001fff8
+
+#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET        0x00000000
+#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB           17
+#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK          0x003e0000
+
+#define RX_MSDU_DESC_INFO_0_MSDU_DROP_OFFSET                         0x00000000
+#define RX_MSDU_DESC_INFO_0_MSDU_DROP_LSB                            22
+#define RX_MSDU_DESC_INFO_0_MSDU_DROP_MASK                           0x00400000
+
+#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET                       0x00000000
+#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_LSB                          23
+#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK                         0x00800000
+
+#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET                    0x00000000
+#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB                       24
+#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK                      0x01000000
+
+#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET                       0x00000000
+#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_LSB                          25
+#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK                         0x02000000
+
+#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET                        0x00000000
+#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_LSB                           26
+#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK                          0x04000000
+
+#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET                    0x00000000
+#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB                       27
+#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK                      0x08000000
+
+#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_OFFSET             0x00000000
+#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_LSB                28
+#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_MASK               0x10000000
+
+#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_OFFSET               0x00000000
+#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_LSB                  29
+#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_MASK                 0x20000000
+
+#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_OFFSET                    0x00000000
+#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_LSB                       30
+#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_MASK                      0x40000000
+
+#define RX_MSDU_DESC_INFO_0_RAW_MPDU_OFFSET                          0x00000000
+#define RX_MSDU_DESC_INFO_0_RAW_MPDU_LSB                             31
+#define RX_MSDU_DESC_INFO_0_RAW_MPDU_MASK                            0x80000000
+
+#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET         0x00000004
+#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_LSB            0
+#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_MASK           0x00007fff
+
+#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET   0x00000004
+#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB      15
+#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK     0x3fff8000
+
+#define RX_MSDU_DESC_INFO_1_FR_DS_OFFSET                             0x00000004
+#define RX_MSDU_DESC_INFO_1_FR_DS_LSB                                30
+#define RX_MSDU_DESC_INFO_1_FR_DS_MASK                               0x40000000
+
+#define RX_MSDU_DESC_INFO_1_TO_DS_OFFSET                             0x00000004
+#define RX_MSDU_DESC_INFO_1_TO_DS_LSB                                31
+#define RX_MSDU_DESC_INFO_1_TO_DS_MASK                               0x80000000
+
+#endif

hw/wcn6450/v1/rx_msdu_details.h

@@ -0,0 +1,129 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MSDU_DETAILS_H_
+#define _RX_MSDU_DETAILS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "rx_msdu_desc_info.h"
+
+#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4
+
+struct rx_msdu_details {
+    struct            buffer_addr_info                       buffer_addr_info_details;
+    struct            rx_msdu_desc_info                       rx_msdu_desc_info_details;
+};
+
+#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB  3
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB    22
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK   0x00400000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB  23
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB  25
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB   26
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK  0x04000000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET  0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB     31
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK    0x80000000
+
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET     0x0000000c
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB        30
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK       0x40000000
+
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET     0x0000000c
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB        31
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK       0x80000000
+
+#endif

hw/wcn6450/v1/rx_msdu_end.h

@@ -0,0 +1,322 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MSDU_END_H_
+#define _RX_MSDU_END_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_MSDU_END 17
+
+struct rx_msdu_end {
+             uint32_t rxpcu_mpdu_filter_in_category   :  2,
+                      sw_frame_group_id               :  7,
+                      reserved_0                      :  7,
+                      phy_ppdu_id                     : 16;
+             uint32_t ip_hdr_chksum                   : 16,
+                      reported_mpdu_length            : 14,
+                      reserved_1a                     :  2;
+             uint32_t key_id_octet                    :  8,
+                      cce_super_rule                  :  6,
+                      cce_classify_not_done_truncate  :  1,
+                      cce_classify_not_done_cce_dis   :  1,
+                      cumulative_l3_checksum          : 16;
+             uint32_t rule_indication_31_0            : 32;
+             uint32_t rule_indication_63_32           : 32;
+             uint32_t da_offset                       :  6,
+                      sa_offset                       :  6,
+                      da_offset_valid                 :  1,
+                      sa_offset_valid                 :  1,
+                      reserved_5a                     :  2,
+                      l3_type                         : 16;
+             uint32_t ipv6_options_crc                : 32;
+             uint32_t tcp_seq_number                  : 32;
+             uint32_t tcp_ack_number                  : 32;
+             uint32_t tcp_flag                        :  9,
+                      lro_eligible                    :  1,
+                      reserved_9a                     :  6,
+                      window_size                     : 16;
+             uint32_t tcp_udp_chksum                  : 16,
+                      sa_idx_timeout                  :  1,
+                      da_idx_timeout                  :  1,
+                      msdu_limit_error                :  1,
+                      flow_idx_timeout                :  1,
+                      flow_idx_invalid                :  1,
+                      wifi_parser_error               :  1,
+                      amsdu_parser_error              :  1,
+                      sa_is_valid                     :  1,
+                      da_is_valid                     :  1,
+                      da_is_mcbc                      :  1,
+                      l3_header_padding               :  2,
+                      first_msdu                      :  1,
+                      last_msdu                       :  1,
+                      tcp_udp_chksum_fail             :  1,
+                      ip_chksum_fail                  :  1;
+             uint32_t sa_idx                          : 16,
+                      da_idx_or_sw_peer_id            : 16;
+             uint32_t msdu_drop                       :  1,
+                      reo_destination_indication      :  5,
+                      flow_idx                        : 20,
+                      reserved_12a                    :  6;
+             uint32_t fse_metadata                    : 32;
+             uint32_t cce_metadata                    : 16,
+                      sa_sw_peer_id                   : 16;
+             uint32_t aggregation_count               :  8,
+                      flow_aggregation_continuation   :  1,
+                      fisa_timeout                    :  1,
+                      reserved_15a                    : 22;
+             uint32_t cumulative_l4_checksum          : 16,
+                      cumulative_ip_length            : 16;
+};
+
+#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET           0x00000000
+#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB              0
+#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK             0x00000003
+
+#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET                       0x00000000
+#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB                          2
+#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK                         0x000001fc
+
+#define RX_MSDU_END_0_RESERVED_0_OFFSET                              0x00000000
+#define RX_MSDU_END_0_RESERVED_0_LSB                                 9
+#define RX_MSDU_END_0_RESERVED_0_MASK                                0x0000fe00
+
+#define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET                             0x00000000
+#define RX_MSDU_END_0_PHY_PPDU_ID_LSB                                16
+#define RX_MSDU_END_0_PHY_PPDU_ID_MASK                               0xffff0000
+
+#define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET                           0x00000004
+#define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB                              0
+#define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK                             0x0000ffff
+
+#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_OFFSET                    0x00000004
+#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_LSB                       16
+#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_MASK                      0x3fff0000
+
+#define RX_MSDU_END_1_RESERVED_1A_OFFSET                             0x00000004
+#define RX_MSDU_END_1_RESERVED_1A_LSB                                30
+#define RX_MSDU_END_1_RESERVED_1A_MASK                               0xc0000000
+
+#define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET                            0x00000008
+#define RX_MSDU_END_2_KEY_ID_OCTET_LSB                               0
+#define RX_MSDU_END_2_KEY_ID_OCTET_MASK                              0x000000ff
+
+#define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET                          0x00000008
+#define RX_MSDU_END_2_CCE_SUPER_RULE_LSB                             8
+#define RX_MSDU_END_2_CCE_SUPER_RULE_MASK                            0x00003f00
+
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET          0x00000008
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB             14
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK            0x00004000
+
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET           0x00000008
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB              15
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK             0x00008000
+
+#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_OFFSET                  0x00000008
+#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_LSB                     16
+#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_MASK                    0xffff0000
+
+#define RX_MSDU_END_3_RULE_INDICATION_31_0_OFFSET                    0x0000000c
+#define RX_MSDU_END_3_RULE_INDICATION_31_0_LSB                       0
+#define RX_MSDU_END_3_RULE_INDICATION_31_0_MASK                      0xffffffff
+
+#define RX_MSDU_END_4_RULE_INDICATION_63_32_OFFSET                   0x00000010
+#define RX_MSDU_END_4_RULE_INDICATION_63_32_LSB                      0
+#define RX_MSDU_END_4_RULE_INDICATION_63_32_MASK                     0xffffffff
+
+#define RX_MSDU_END_5_DA_OFFSET_OFFSET                               0x00000014
+#define RX_MSDU_END_5_DA_OFFSET_LSB                                  0
+#define RX_MSDU_END_5_DA_OFFSET_MASK                                 0x0000003f
+
+#define RX_MSDU_END_5_SA_OFFSET_OFFSET                               0x00000014
+#define RX_MSDU_END_5_SA_OFFSET_LSB                                  6
+#define RX_MSDU_END_5_SA_OFFSET_MASK                                 0x00000fc0
+
+#define RX_MSDU_END_5_DA_OFFSET_VALID_OFFSET                         0x00000014
+#define RX_MSDU_END_5_DA_OFFSET_VALID_LSB                            12
+#define RX_MSDU_END_5_DA_OFFSET_VALID_MASK                           0x00001000
+
+#define RX_MSDU_END_5_SA_OFFSET_VALID_OFFSET                         0x00000014
+#define RX_MSDU_END_5_SA_OFFSET_VALID_LSB                            13
+#define RX_MSDU_END_5_SA_OFFSET_VALID_MASK                           0x00002000
+
+#define RX_MSDU_END_5_RESERVED_5A_OFFSET                             0x00000014
+#define RX_MSDU_END_5_RESERVED_5A_LSB                                14
+#define RX_MSDU_END_5_RESERVED_5A_MASK                               0x0000c000
+
+#define RX_MSDU_END_5_L3_TYPE_OFFSET                                 0x00000014
+#define RX_MSDU_END_5_L3_TYPE_LSB                                    16
+#define RX_MSDU_END_5_L3_TYPE_MASK                                   0xffff0000
+
+#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET                        0x00000018
+#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB                           0
+#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK                          0xffffffff
+
+#define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET                          0x0000001c
+#define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB                             0
+#define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK                            0xffffffff
+
+#define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET                          0x00000020
+#define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB                             0
+#define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK                            0xffffffff
+
+#define RX_MSDU_END_9_TCP_FLAG_OFFSET                                0x00000024
+#define RX_MSDU_END_9_TCP_FLAG_LSB                                   0
+#define RX_MSDU_END_9_TCP_FLAG_MASK                                  0x000001ff
+
+#define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET                            0x00000024
+#define RX_MSDU_END_9_LRO_ELIGIBLE_LSB                               9
+#define RX_MSDU_END_9_LRO_ELIGIBLE_MASK                              0x00000200
+
+#define RX_MSDU_END_9_RESERVED_9A_OFFSET                             0x00000024
+#define RX_MSDU_END_9_RESERVED_9A_LSB                                10
+#define RX_MSDU_END_9_RESERVED_9A_MASK                               0x0000fc00
+
+#define RX_MSDU_END_9_WINDOW_SIZE_OFFSET                             0x00000024
+#define RX_MSDU_END_9_WINDOW_SIZE_LSB                                16
+#define RX_MSDU_END_9_WINDOW_SIZE_MASK                               0xffff0000
+
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET                         0x00000028
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB                            0
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK                           0x0000ffff
+
+#define RX_MSDU_END_10_SA_IDX_TIMEOUT_OFFSET                         0x00000028
+#define RX_MSDU_END_10_SA_IDX_TIMEOUT_LSB                            16
+#define RX_MSDU_END_10_SA_IDX_TIMEOUT_MASK                           0x00010000
+
+#define RX_MSDU_END_10_DA_IDX_TIMEOUT_OFFSET                         0x00000028
+#define RX_MSDU_END_10_DA_IDX_TIMEOUT_LSB                            17
+#define RX_MSDU_END_10_DA_IDX_TIMEOUT_MASK                           0x00020000
+
+#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_OFFSET                       0x00000028
+#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_LSB                          18
+#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_MASK                         0x00040000
+
+#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET                       0x00000028
+#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB                          19
+#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK                         0x00080000
+
+#define RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET                       0x00000028
+#define RX_MSDU_END_10_FLOW_IDX_INVALID_LSB                          20
+#define RX_MSDU_END_10_FLOW_IDX_INVALID_MASK                         0x00100000
+
+#define RX_MSDU_END_10_WIFI_PARSER_ERROR_OFFSET                      0x00000028
+#define RX_MSDU_END_10_WIFI_PARSER_ERROR_LSB                         21
+#define RX_MSDU_END_10_WIFI_PARSER_ERROR_MASK                        0x00200000
+
+#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_OFFSET                     0x00000028
+#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_LSB                        22
+#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_MASK                       0x00400000
+
+#define RX_MSDU_END_10_SA_IS_VALID_OFFSET                            0x00000028
+#define RX_MSDU_END_10_SA_IS_VALID_LSB                               23
+#define RX_MSDU_END_10_SA_IS_VALID_MASK                              0x00800000
+
+#define RX_MSDU_END_10_DA_IS_VALID_OFFSET                            0x00000028
+#define RX_MSDU_END_10_DA_IS_VALID_LSB                               24
+#define RX_MSDU_END_10_DA_IS_VALID_MASK                              0x01000000
+
+#define RX_MSDU_END_10_DA_IS_MCBC_OFFSET                             0x00000028
+#define RX_MSDU_END_10_DA_IS_MCBC_LSB                                25
+#define RX_MSDU_END_10_DA_IS_MCBC_MASK                               0x02000000
+
+#define RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET                      0x00000028
+#define RX_MSDU_END_10_L3_HEADER_PADDING_LSB                         26
+#define RX_MSDU_END_10_L3_HEADER_PADDING_MASK                        0x0c000000
+
+#define RX_MSDU_END_10_FIRST_MSDU_OFFSET                             0x00000028
+#define RX_MSDU_END_10_FIRST_MSDU_LSB                                28
+#define RX_MSDU_END_10_FIRST_MSDU_MASK                               0x10000000
+
+#define RX_MSDU_END_10_LAST_MSDU_OFFSET                              0x00000028
+#define RX_MSDU_END_10_LAST_MSDU_LSB                                 29
+#define RX_MSDU_END_10_LAST_MSDU_MASK                                0x20000000
+
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_OFFSET                    0x00000028
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_LSB                       30
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_MASK                      0x40000000
+
+#define RX_MSDU_END_10_IP_CHKSUM_FAIL_OFFSET                         0x00000028
+#define RX_MSDU_END_10_IP_CHKSUM_FAIL_LSB                            31
+#define RX_MSDU_END_10_IP_CHKSUM_FAIL_MASK                           0x80000000
+
+#define RX_MSDU_END_11_SA_IDX_OFFSET                                 0x0000002c
+#define RX_MSDU_END_11_SA_IDX_LSB                                    0
+#define RX_MSDU_END_11_SA_IDX_MASK                                   0x0000ffff
+
+#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET                   0x0000002c
+#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB                      16
+#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK                     0xffff0000
+
+#define RX_MSDU_END_12_MSDU_DROP_OFFSET                              0x00000030
+#define RX_MSDU_END_12_MSDU_DROP_LSB                                 0
+#define RX_MSDU_END_12_MSDU_DROP_MASK                                0x00000001
+
+#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET             0x00000030
+#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB                1
+#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK               0x0000003e
+
+#define RX_MSDU_END_12_FLOW_IDX_OFFSET                               0x00000030
+#define RX_MSDU_END_12_FLOW_IDX_LSB                                  6
+#define RX_MSDU_END_12_FLOW_IDX_MASK                                 0x03ffffc0
+
+#define RX_MSDU_END_12_RESERVED_12A_OFFSET                           0x00000030
+#define RX_MSDU_END_12_RESERVED_12A_LSB                              26
+#define RX_MSDU_END_12_RESERVED_12A_MASK                             0xfc000000
+
+#define RX_MSDU_END_13_FSE_METADATA_OFFSET                           0x00000034
+#define RX_MSDU_END_13_FSE_METADATA_LSB                              0
+#define RX_MSDU_END_13_FSE_METADATA_MASK                             0xffffffff
+
+#define RX_MSDU_END_14_CCE_METADATA_OFFSET                           0x00000038
+#define RX_MSDU_END_14_CCE_METADATA_LSB                              0
+#define RX_MSDU_END_14_CCE_METADATA_MASK                             0x0000ffff
+
+#define RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET                          0x00000038
+#define RX_MSDU_END_14_SA_SW_PEER_ID_LSB                             16
+#define RX_MSDU_END_14_SA_SW_PEER_ID_MASK                            0xffff0000
+
+#define RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET                      0x0000003c
+#define RX_MSDU_END_15_AGGREGATION_COUNT_LSB                         0
+#define RX_MSDU_END_15_AGGREGATION_COUNT_MASK                        0x000000ff
+
+#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET          0x0000003c
+#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB             8
+#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK            0x00000100
+
+#define RX_MSDU_END_15_FISA_TIMEOUT_OFFSET                           0x0000003c
+#define RX_MSDU_END_15_FISA_TIMEOUT_LSB                              9
+#define RX_MSDU_END_15_FISA_TIMEOUT_MASK                             0x00000200
+
+#define RX_MSDU_END_15_RESERVED_15A_OFFSET                           0x0000003c
+#define RX_MSDU_END_15_RESERVED_15A_LSB                              10
+#define RX_MSDU_END_15_RESERVED_15A_MASK                             0xfffffc00
+
+#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET                 0x00000040
+#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB                    0
+#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK                   0x0000ffff
+
+#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET                   0x00000040
+#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB                      16
+#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK                     0xffff0000
+
+#endif

hw/wcn6450/v1/rx_msdu_link.h

@@ -0,0 +1,659 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MSDU_LINK_H_
+#define _RX_MSDU_LINK_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_descriptor_header.h"
+#include "buffer_addr_info.h"
+#include "rx_msdu_details.h"
+
+#define NUM_OF_DWORDS_RX_MSDU_LINK 32
+
+struct rx_msdu_link {
+    struct            uniform_descriptor_header                       descriptor_header;
+    struct            buffer_addr_info                       next_msdu_link_desc_addr_info;
+             uint32_t receive_queue_number            : 16,
+                      first_rx_msdu_link_struct       :  1,
+                      reserved_3a                     : 15;
+             uint32_t pn_31_0                         : 32;
+             uint32_t pn_63_32                        : 32;
+             uint32_t pn_95_64                        : 32;
+             uint32_t pn_127_96                       : 32;
+    struct            rx_msdu_details                       msdu_0;
+    struct            rx_msdu_details                       msdu_1;
+    struct            rx_msdu_details                       msdu_2;
+    struct            rx_msdu_details                       msdu_3;
+    struct            rx_msdu_details                       msdu_4;
+    struct            rx_msdu_details                       msdu_5;
+};
+
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_OFFSET                0x00000000
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_LSB                   0
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_MASK                  0x0000000f
+
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET          0x00000000
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB             4
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK            0x000000f0
+
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET          0x00000000
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB             8
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK            0xffffff00
+
+#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004
+#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET                   0x0000000c
+#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB                      0
+#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK                     0x0000ffff
+
+#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET              0x0000000c
+#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB                 16
+#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK                0x00010000
+
+#define RX_MSDU_LINK_3_RESERVED_3A_OFFSET                            0x0000000c
+#define RX_MSDU_LINK_3_RESERVED_3A_LSB                               17
+#define RX_MSDU_LINK_3_RESERVED_3A_MASK                              0xfffe0000
+
+#define RX_MSDU_LINK_4_PN_31_0_OFFSET                                0x00000010
+#define RX_MSDU_LINK_4_PN_31_0_LSB                                   0
+#define RX_MSDU_LINK_4_PN_31_0_MASK                                  0xffffffff
+
+#define RX_MSDU_LINK_5_PN_63_32_OFFSET                               0x00000014
+#define RX_MSDU_LINK_5_PN_63_32_LSB                                  0
+#define RX_MSDU_LINK_5_PN_63_32_MASK                                 0xffffffff
+
+#define RX_MSDU_LINK_6_PN_95_64_OFFSET                               0x00000018
+#define RX_MSDU_LINK_6_PN_95_64_LSB                                  0
+#define RX_MSDU_LINK_6_PN_95_64_MASK                                 0xffffffff
+
+#define RX_MSDU_LINK_7_PN_127_96_OFFSET                              0x0000001c
+#define RX_MSDU_LINK_7_PN_127_96_LSB                                 0
+#define RX_MSDU_LINK_7_PN_127_96_MASK                                0xffffffff
+
+#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020
+#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000002c
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000002c
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000002c
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB   30
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK  0x40000000
+
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000002c
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB   31
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK  0x80000000
+
+#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030
+#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000003c
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000003c
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000003c
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB   30
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK  0x40000000
+
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000003c
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB   31
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK  0x80000000
+
+#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040
+#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000004c
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000004c
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000004c
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB   30
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK  0x40000000
+
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000004c
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB   31
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK  0x80000000
+
+#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050
+#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000005c
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000005c
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000005c
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB   30
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK  0x40000000
+
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000005c
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB   31
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK  0x80000000
+
+#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060
+#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000006c
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000006c
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000006c
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB   30
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK  0x40000000
+
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000006c
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB   31
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK  0x80000000
+
+#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070
+#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000007c
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000007c
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000007c
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB   30
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK  0x40000000
+
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000007c
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB   31
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK  0x80000000
+
+#endif

hw/wcn6450/v1/rx_msdu_start.h

@@ -0,0 +1,232 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_MSDU_START_H_
+#define _RX_MSDU_START_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_MSDU_START 9
+
+struct rx_msdu_start {
+             uint32_t rxpcu_mpdu_filter_in_category   :  2,
+                      sw_frame_group_id               :  7,
+                      reserved_0                      :  7,
+                      phy_ppdu_id                     : 16;
+             uint32_t msdu_length                     : 14,
+                      reserved_1a                     :  1,
+                      ipsec_esp                       :  1,
+                      l3_offset                       :  7,
+                      ipsec_ah                        :  1,
+                      l4_offset                       :  8;
+             uint32_t msdu_number                     :  8,
+                      decap_format                    :  2,
+                      ipv4_proto                      :  1,
+                      ipv6_proto                      :  1,
+                      tcp_proto                       :  1,
+                      udp_proto                       :  1,
+                      ip_frag                         :  1,
+                      tcp_only_ack                    :  1,
+                      da_is_bcast_mcast               :  1,
+                      toeplitz_hash_sel               :  2,
+                      ip_fixed_header_valid           :  1,
+                      ip_extn_header_valid            :  1,
+                      tcp_udp_header_valid            :  1,
+                      mesh_control_present            :  1,
+                      ldpc                            :  1,
+                      ip4_protocol_ip6_next_header    :  8;
+             uint32_t toeplitz_hash_2_or_4            : 32;
+             uint32_t flow_id_toeplitz                : 32;
+             uint32_t user_rssi                       :  8,
+                      pkt_type                        :  4,
+                      stbc                            :  1,
+                      sgi                             :  2,
+                      rate_mcs                        :  4,
+                      receive_bandwidth               :  2,
+                      reception_type                  :  3,
+                      mimo_ss_bitmap                  :  8;
+             uint32_t ppdu_start_timestamp            : 32;
+             uint32_t sw_phy_meta_data                : 32;
+             uint32_t vlan_ctag_ci                    : 16,
+                      vlan_stag_ci                    : 16;
+};
+
+#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET         0x00000000
+#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB            0
+#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK           0x00000003
+
+#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_OFFSET                     0x00000000
+#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_LSB                        2
+#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_MASK                       0x000001fc
+
+#define RX_MSDU_START_0_RESERVED_0_OFFSET                            0x00000000
+#define RX_MSDU_START_0_RESERVED_0_LSB                               9
+#define RX_MSDU_START_0_RESERVED_0_MASK                              0x0000fe00
+
+#define RX_MSDU_START_0_PHY_PPDU_ID_OFFSET                           0x00000000
+#define RX_MSDU_START_0_PHY_PPDU_ID_LSB                              16
+#define RX_MSDU_START_0_PHY_PPDU_ID_MASK                             0xffff0000
+
+#define RX_MSDU_START_1_MSDU_LENGTH_OFFSET                           0x00000004
+#define RX_MSDU_START_1_MSDU_LENGTH_LSB                              0
+#define RX_MSDU_START_1_MSDU_LENGTH_MASK                             0x00003fff
+
+#define RX_MSDU_START_1_RESERVED_1A_OFFSET                           0x00000004
+#define RX_MSDU_START_1_RESERVED_1A_LSB                              14
+#define RX_MSDU_START_1_RESERVED_1A_MASK                             0x00004000
+
+#define RX_MSDU_START_1_IPSEC_ESP_OFFSET                             0x00000004
+#define RX_MSDU_START_1_IPSEC_ESP_LSB                                15
+#define RX_MSDU_START_1_IPSEC_ESP_MASK                               0x00008000
+
+#define RX_MSDU_START_1_L3_OFFSET_OFFSET                             0x00000004
+#define RX_MSDU_START_1_L3_OFFSET_LSB                                16
+#define RX_MSDU_START_1_L3_OFFSET_MASK                               0x007f0000
+
+#define RX_MSDU_START_1_IPSEC_AH_OFFSET                              0x00000004
+#define RX_MSDU_START_1_IPSEC_AH_LSB                                 23
+#define RX_MSDU_START_1_IPSEC_AH_MASK                                0x00800000
+
+#define RX_MSDU_START_1_L4_OFFSET_OFFSET                             0x00000004
+#define RX_MSDU_START_1_L4_OFFSET_LSB                                24
+#define RX_MSDU_START_1_L4_OFFSET_MASK                               0xff000000
+
+#define RX_MSDU_START_2_MSDU_NUMBER_OFFSET                           0x00000008
+#define RX_MSDU_START_2_MSDU_NUMBER_LSB                              0
+#define RX_MSDU_START_2_MSDU_NUMBER_MASK                             0x000000ff
+
+#define RX_MSDU_START_2_DECAP_FORMAT_OFFSET                          0x00000008
+#define RX_MSDU_START_2_DECAP_FORMAT_LSB                             8
+#define RX_MSDU_START_2_DECAP_FORMAT_MASK                            0x00000300
+
+#define RX_MSDU_START_2_IPV4_PROTO_OFFSET                            0x00000008
+#define RX_MSDU_START_2_IPV4_PROTO_LSB                               10
+#define RX_MSDU_START_2_IPV4_PROTO_MASK                              0x00000400
+
+#define RX_MSDU_START_2_IPV6_PROTO_OFFSET                            0x00000008
+#define RX_MSDU_START_2_IPV6_PROTO_LSB                               11
+#define RX_MSDU_START_2_IPV6_PROTO_MASK                              0x00000800
+
+#define RX_MSDU_START_2_TCP_PROTO_OFFSET                             0x00000008
+#define RX_MSDU_START_2_TCP_PROTO_LSB                                12
+#define RX_MSDU_START_2_TCP_PROTO_MASK                               0x00001000
+
+#define RX_MSDU_START_2_UDP_PROTO_OFFSET                             0x00000008
+#define RX_MSDU_START_2_UDP_PROTO_LSB                                13
+#define RX_MSDU_START_2_UDP_PROTO_MASK                               0x00002000
+
+#define RX_MSDU_START_2_IP_FRAG_OFFSET                               0x00000008
+#define RX_MSDU_START_2_IP_FRAG_LSB                                  14
+#define RX_MSDU_START_2_IP_FRAG_MASK                                 0x00004000
+
+#define RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET                          0x00000008
+#define RX_MSDU_START_2_TCP_ONLY_ACK_LSB                             15
+#define RX_MSDU_START_2_TCP_ONLY_ACK_MASK                            0x00008000
+
+#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_OFFSET                     0x00000008
+#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_LSB                        16
+#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_MASK                       0x00010000
+
+#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_OFFSET                     0x00000008
+#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_LSB                        17
+#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_MASK                       0x00060000
+
+#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_OFFSET                 0x00000008
+#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_LSB                    19
+#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_MASK                   0x00080000
+
+#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_OFFSET                  0x00000008
+#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_LSB                     20
+#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_MASK                    0x00100000
+
+#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_OFFSET                  0x00000008
+#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_LSB                     21
+#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_MASK                    0x00200000
+
+#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_OFFSET                  0x00000008
+#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_LSB                     22
+#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_MASK                    0x00400000
+
+#define RX_MSDU_START_2_LDPC_OFFSET                                  0x00000008
+#define RX_MSDU_START_2_LDPC_LSB                                     23
+#define RX_MSDU_START_2_LDPC_MASK                                    0x00800000
+
+#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET          0x00000008
+#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB             24
+#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK            0xff000000
+
+#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_OFFSET                  0x0000000c
+#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_LSB                     0
+#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_MASK                    0xffffffff
+
+#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET                      0x00000010
+#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB                         0
+#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK                        0xffffffff
+
+#define RX_MSDU_START_5_USER_RSSI_OFFSET                             0x00000014
+#define RX_MSDU_START_5_USER_RSSI_LSB                                0
+#define RX_MSDU_START_5_USER_RSSI_MASK                               0x000000ff
+
+#define RX_MSDU_START_5_PKT_TYPE_OFFSET                              0x00000014
+#define RX_MSDU_START_5_PKT_TYPE_LSB                                 8
+#define RX_MSDU_START_5_PKT_TYPE_MASK                                0x00000f00
+
+#define RX_MSDU_START_5_STBC_OFFSET                                  0x00000014
+#define RX_MSDU_START_5_STBC_LSB                                     12
+#define RX_MSDU_START_5_STBC_MASK                                    0x00001000
+
+#define RX_MSDU_START_5_SGI_OFFSET                                   0x00000014
+#define RX_MSDU_START_5_SGI_LSB                                      13
+#define RX_MSDU_START_5_SGI_MASK                                     0x00006000
+
+#define RX_MSDU_START_5_RATE_MCS_OFFSET                              0x00000014
+#define RX_MSDU_START_5_RATE_MCS_LSB                                 15
+#define RX_MSDU_START_5_RATE_MCS_MASK                                0x00078000
+
+#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET                     0x00000014
+#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB                        19
+#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK                       0x00180000
+
+#define RX_MSDU_START_5_RECEPTION_TYPE_OFFSET                        0x00000014
+#define RX_MSDU_START_5_RECEPTION_TYPE_LSB                           21
+#define RX_MSDU_START_5_RECEPTION_TYPE_MASK                          0x00e00000
+
+#define RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET                        0x00000014
+#define RX_MSDU_START_5_MIMO_SS_BITMAP_LSB                           24
+#define RX_MSDU_START_5_MIMO_SS_BITMAP_MASK                          0xff000000
+
+#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_OFFSET                  0x00000018
+#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_LSB                     0
+#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_MASK                    0xffffffff
+
+#define RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET                      0x0000001c
+#define RX_MSDU_START_7_SW_PHY_META_DATA_LSB                         0
+#define RX_MSDU_START_7_SW_PHY_META_DATA_MASK                        0xffffffff
+
+#define RX_MSDU_START_8_VLAN_CTAG_CI_OFFSET                          0x00000020
+#define RX_MSDU_START_8_VLAN_CTAG_CI_LSB                             0
+#define RX_MSDU_START_8_VLAN_CTAG_CI_MASK                            0x0000ffff
+
+#define RX_MSDU_START_8_VLAN_STAG_CI_OFFSET                          0x00000020
+#define RX_MSDU_START_8_VLAN_STAG_CI_LSB                             16
+#define RX_MSDU_START_8_VLAN_STAG_CI_MASK                            0xffff0000
+
+#endif

hw/wcn6450/v1/rx_ppdu_end_user_stats.h

@@ -0,0 +1,406 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_PPDU_END_USER_STATS_H_
+#define _RX_PPDU_END_USER_STATS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_rxpcu_classification_overview.h"
+
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 23
+
+struct rx_ppdu_end_user_stats {
+    struct            rx_rxpcu_classification_overview                       rxpcu_classification_details;
+             uint32_t sta_full_aid                    : 13,
+                      mcs                             :  4,
+                      nss                             :  3,
+                      ofdma_info_valid                :  1,
+                      dl_ofdma_ru_start_index         :  7,
+                      reserved_1a                     :  4;
+             uint32_t dl_ofdma_ru_width               :  7,
+                      reserved_2a                     :  1,
+                      user_receive_quality            :  8,
+                      mpdu_cnt_fcs_err                : 10,
+                      wbm2rxdma_buf_source_used       :  1,
+                      fw2rxdma_buf_source_used        :  1,
+                      sw2rxdma_buf_source_used        :  1,
+                      reserved_2b                     :  3;
+             uint32_t mpdu_cnt_fcs_ok                 :  9,
+                      frame_control_info_valid        :  1,
+                      qos_control_info_valid          :  1,
+                      ht_control_info_valid           :  1,
+                      data_sequence_control_info_valid:  1,
+                      ht_control_info_null_valid      :  1,
+                      reserved_3a                     :  2,
+                      rxdma2reo_ring_used             :  1,
+                      rxdma2fw_ring_used              :  1,
+                      rxdma2sw_ring_used              :  1,
+                      rxdma_release_ring_used         :  1,
+                      ht_control_field_pkt_type       :  4,
+                      reserved_3b                     :  8;
+             uint32_t ast_index                       : 16,
+                      frame_control_field             : 16;
+             uint32_t first_data_seq_ctrl             : 16,
+                      qos_control_field               : 16;
+             uint32_t ht_control_field                : 32;
+             uint32_t fcs_ok_bitmap_31_0              : 32;
+             uint32_t fcs_ok_bitmap_63_32             : 32;
+             uint32_t udp_msdu_count                  : 16,
+                      tcp_msdu_count                  : 16;
+             uint32_t other_msdu_count                : 16,
+                      tcp_ack_msdu_count              : 16;
+             uint32_t sw_response_reference_ptr       : 32;
+             uint32_t received_qos_data_tid_bitmap    : 16,
+                      received_qos_data_tid_eosp_bitmap: 16;
+             uint32_t qosctrl_15_8_tid0               :  8,
+                      qosctrl_15_8_tid1               :  8,
+                      qosctrl_15_8_tid2               :  8,
+                      qosctrl_15_8_tid3               :  8;
+             uint32_t qosctrl_15_8_tid4               :  8,
+                      qosctrl_15_8_tid5               :  8,
+                      qosctrl_15_8_tid6               :  8,
+                      qosctrl_15_8_tid7               :  8;
+             uint32_t qosctrl_15_8_tid8               :  8,
+                      qosctrl_15_8_tid9               :  8,
+                      qosctrl_15_8_tid10              :  8,
+                      qosctrl_15_8_tid11              :  8;
+             uint32_t qosctrl_15_8_tid12              :  8,
+                      qosctrl_15_8_tid13              :  8,
+                      qosctrl_15_8_tid14              :  8,
+                      qosctrl_15_8_tid15              :  8;
+             uint32_t mpdu_ok_byte_count              : 25,
+                      ampdu_delim_ok_count_6_0        :  7;
+             uint32_t ampdu_delim_err_count           : 25,
+                      ampdu_delim_ok_count_13_7       :  7;
+             uint32_t mpdu_err_byte_count             : 25,
+                      ampdu_delim_ok_count_20_14      :  7;
+             uint32_t non_consecutive_delimiter_err   : 16,
+                      reserved_20a                    : 16;
+             uint32_t ht_control_null_field           : 32;
+             uint32_t sw_response_reference_ptr_ext   : 32;
+};
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80
+
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_OFFSET                 0x00000004
+#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_LSB                    0
+#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_MASK                   0x00001fff
+
+#define RX_PPDU_END_USER_STATS_1_MCS_OFFSET                          0x00000004
+#define RX_PPDU_END_USER_STATS_1_MCS_LSB                             13
+#define RX_PPDU_END_USER_STATS_1_MCS_MASK                            0x0001e000
+
+#define RX_PPDU_END_USER_STATS_1_NSS_OFFSET                          0x00000004
+#define RX_PPDU_END_USER_STATS_1_NSS_LSB                             17
+#define RX_PPDU_END_USER_STATS_1_NSS_MASK                            0x000e0000
+
+#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET             0x00000004
+#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_LSB                20
+#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_MASK               0x00100000
+
+#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_OFFSET      0x00000004
+#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_LSB         21
+#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_MASK        0x0fe00000
+
+#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_OFFSET                  0x00000004
+#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_LSB                     28
+#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_MASK                    0xf0000000
+
+#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_OFFSET            0x00000008
+#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_LSB               0
+#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_MASK              0x0000007f
+
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_OFFSET                  0x00000008
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_LSB                     7
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_MASK                    0x00000080
+
+#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_OFFSET         0x00000008
+#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_LSB            8
+#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_MASK           0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_OFFSET             0x00000008
+#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_LSB                16
+#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_MASK               0x03ff0000
+
+#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_OFFSET    0x00000008
+#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_LSB       26
+#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_MASK      0x04000000
+
+#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_OFFSET     0x00000008
+#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_LSB        27
+#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_MASK       0x08000000
+
+#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_OFFSET     0x00000008
+#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_LSB        28
+#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_MASK       0x10000000
+
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_OFFSET                  0x00000008
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_LSB                     29
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_MASK                    0xe0000000
+
+#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_OFFSET              0x0000000c
+#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_LSB                 0
+#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_MASK                0x000001ff
+
+#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_OFFSET     0x0000000c
+#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_LSB        9
+#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_MASK       0x00000200
+
+#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_OFFSET       0x0000000c
+#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_LSB          10
+#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_MASK         0x00000400
+
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_OFFSET        0x0000000c
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_LSB           11
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_MASK          0x00000800
+
+#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 12
+#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x00001000
+
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_OFFSET   0x0000000c
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_LSB      13
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_MASK     0x00002000
+
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_OFFSET                  0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_LSB                     14
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_MASK                    0x0000c000
+
+#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_OFFSET          0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_LSB             16
+#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_MASK            0x00010000
+
+#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_OFFSET           0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_LSB              17
+#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_MASK             0x00020000
+
+#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_OFFSET           0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_LSB              18
+#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_MASK             0x00040000
+
+#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_OFFSET      0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_LSB         19
+#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_MASK        0x00080000
+
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_OFFSET    0x0000000c
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_LSB       20
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_MASK      0x00f00000
+
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_OFFSET                  0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_LSB                     24
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_MASK                    0xff000000
+
+#define RX_PPDU_END_USER_STATS_4_AST_INDEX_OFFSET                    0x00000010
+#define RX_PPDU_END_USER_STATS_4_AST_INDEX_LSB                       0
+#define RX_PPDU_END_USER_STATS_4_AST_INDEX_MASK                      0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_OFFSET          0x00000010
+#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_LSB             16
+#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_MASK            0xffff0000
+
+#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_OFFSET          0x00000014
+#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_LSB             0
+#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_MASK            0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_OFFSET            0x00000014
+#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_LSB               16
+#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_MASK              0xffff0000
+
+#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_OFFSET             0x00000018
+#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_LSB                0
+#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_MASK               0xffffffff
+
+#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_OFFSET           0x0000001c
+#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_LSB              0
+#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_MASK             0xffffffff
+
+#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_OFFSET          0x00000020
+#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_LSB             0
+#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_MASK            0xffffffff
+
+#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_OFFSET               0x00000024
+#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_LSB                  0
+#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_MASK                 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_OFFSET               0x00000024
+#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_LSB                  16
+#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_MASK                 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_OFFSET            0x00000028
+#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_LSB               0
+#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_MASK              0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_OFFSET          0x00000028
+#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_LSB             16
+#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_MASK            0xffff0000
+
+#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_OFFSET   0x0000002c
+#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_LSB      0
+#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_MASK     0xffffffff
+
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x00000030
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_LSB   0
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_MASK  0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x00000030
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_OFFSET           0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_LSB              0
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_MASK             0x000000ff
+
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_OFFSET           0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_LSB              8
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_MASK             0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_OFFSET           0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_LSB              16
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_MASK             0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_OFFSET           0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_LSB              24
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_MASK             0xff000000
+
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_OFFSET           0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_LSB              0
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_MASK             0x000000ff
+
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_OFFSET           0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_LSB              8
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_MASK             0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_OFFSET           0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_LSB              16
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_MASK             0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_OFFSET           0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_LSB              24
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_MASK             0xff000000
+
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_OFFSET           0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_LSB              0
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_MASK             0x000000ff
+
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_OFFSET           0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_LSB              8
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_MASK             0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_OFFSET          0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_LSB             16
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_MASK            0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_OFFSET          0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_LSB             24
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_MASK            0xff000000
+
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_OFFSET          0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_LSB             0
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_MASK            0x000000ff
+
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_OFFSET          0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_LSB             8
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_MASK            0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_OFFSET          0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_LSB             16
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_MASK            0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_OFFSET          0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_LSB             24
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_MASK            0xff000000
+
+#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_OFFSET          0x00000044
+#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_LSB             0
+#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_MASK            0x01ffffff
+
+#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_OFFSET    0x00000044
+#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_LSB       25
+#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_MASK      0xfe000000
+
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_OFFSET       0x00000048
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_LSB          0
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_MASK         0x01ffffff
+
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_OFFSET   0x00000048
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_LSB      25
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_MASK     0xfe000000
+
+#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_OFFSET         0x0000004c
+#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_LSB            0
+#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_MASK           0x01ffffff
+
+#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_OFFSET  0x0000004c
+#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_LSB     25
+#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_MASK    0xfe000000
+
+#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x00000050
+#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_LSB  0
+#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_OFFSET                0x00000050
+#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_LSB                   16
+#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_MASK                  0xffff0000
+
+#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_OFFSET       0x00000054
+#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_LSB          0
+#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_MASK         0xffffffff
+
+#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x00000058
+#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_LSB  0
+#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0xffffffff
+
+#endif

hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h

@@ -0,0 +1,101 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_PPDU_END_USER_STATS_EXT_H_
+#define _RX_PPDU_END_USER_STATS_EXT_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_rxpcu_classification_overview.h"
+
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 7
+
+struct rx_ppdu_end_user_stats_ext {
+    struct            rx_rxpcu_classification_overview                       rxpcu_classification_details;
+             uint32_t fcs_ok_bitmap_95_64             : 32;
+             uint32_t fcs_ok_bitmap_127_96            : 32;
+             uint32_t fcs_ok_bitmap_159_128           : 32;
+             uint32_t fcs_ok_bitmap_191_160           : 32;
+             uint32_t fcs_ok_bitmap_223_192           : 32;
+             uint32_t fcs_ok_bitmap_255_224           : 32;
+};
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80
+
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_OFFSET      0x00000004
+#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_LSB         0
+#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_MASK        0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_OFFSET     0x00000008
+#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_LSB        0
+#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_MASK       0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_OFFSET    0x0000000c
+#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_LSB       0
+#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_MASK      0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_OFFSET    0x00000010
+#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_LSB       0
+#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_MASK      0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_OFFSET    0x00000014
+#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_LSB       0
+#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_MASK      0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_OFFSET    0x00000018
+#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_LSB       0
+#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_MASK      0xffffffff
+
+#endif

hw/wcn6450/v1/rx_ppdu_start.h

@@ -0,0 +1,52 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_PPDU_START_H_
+#define _RX_PPDU_START_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_PPDU_START 3
+
+struct rx_ppdu_start {
+             uint32_t phy_ppdu_id                     : 16,
+                      reserved_15                     : 16;
+             uint32_t sw_phy_meta_data                : 32;
+             uint32_t ppdu_start_timestamp            : 32;
+};
+
+#define RX_PPDU_START_0_PHY_PPDU_ID_OFFSET                           0x00000000
+#define RX_PPDU_START_0_PHY_PPDU_ID_LSB                              0
+#define RX_PPDU_START_0_PHY_PPDU_ID_MASK                             0x0000ffff
+
+#define RX_PPDU_START_0_RESERVED_15_OFFSET                           0x00000000
+#define RX_PPDU_START_0_RESERVED_15_LSB                              16
+#define RX_PPDU_START_0_RESERVED_15_MASK                             0xffff0000
+
+#define RX_PPDU_START_1_SW_PHY_META_DATA_OFFSET                      0x00000004
+#define RX_PPDU_START_1_SW_PHY_META_DATA_LSB                         0
+#define RX_PPDU_START_1_SW_PHY_META_DATA_MASK                        0xffffffff
+
+#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_OFFSET                  0x00000008
+#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_LSB                     0
+#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_MASK                    0xffffffff
+
+#endif

hw/wcn6450/v1/rx_ppdu_start_user_info.h

@@ -0,0 +1,95 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_PPDU_START_USER_INFO_H_
+#define _RX_PPDU_START_USER_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "receive_user_info.h"
+
+#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 3
+
+struct rx_ppdu_start_user_info {
+    struct            receive_user_info                       receive_user_info_details;
+};
+
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000
+
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
+
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000
+
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000
+
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f
+
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_LSB  4
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030
+
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 6
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000c0
+
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00
+
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_LSB 16
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_MASK 0x00ff0000
+
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_LSB 24
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_MASK 0x7f000000
+
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_LSB 31
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_MASK 0x80000000
+
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 0
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00000001
+
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_LSB 1
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_MASK 0x000000fe
+
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 8
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0xffffff00
+
+#endif

hw/wcn6450/v1/rx_reo_queue.h

@@ -0,0 +1,362 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_REO_QUEUE_H_
+#define _RX_REO_QUEUE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_descriptor_header.h"
+
+#define NUM_OF_DWORDS_RX_REO_QUEUE 32
+
+struct rx_reo_queue {
+    struct            uniform_descriptor_header                       descriptor_header;
+             uint32_t receive_queue_number            : 16,
+                      reserved_1b                     : 16;
+             uint32_t vld                             :  1,
+                      associated_link_descriptor_counter:  2,
+                      disable_duplicate_detection     :  1,
+                      soft_reorder_enable             :  1,
+                      ac                              :  2,
+                      bar                             :  1,
+                      rty                             :  1,
+                      chk_2k_mode                     :  1,
+                      oor_mode                        :  1,
+                      ba_window_size                  :  8,
+                      pn_check_needed                 :  1,
+                      pn_shall_be_even                :  1,
+                      pn_shall_be_uneven              :  1,
+                      pn_handling_enable              :  1,
+                      pn_size                         :  2,
+                      ignore_ampdu_flag               :  1,
+                      reserved_2b                     :  6;
+             uint32_t svld                            :  1,
+                      ssn                             : 12,
+                      current_index                   :  8,
+                      seq_2k_error_detected_flag      :  1,
+                      pn_error_detected_flag          :  1,
+                      reserved_3a                     :  8,
+                      pn_valid                        :  1;
+             uint32_t pn_31_0                         : 32;
+             uint32_t pn_63_32                        : 32;
+             uint32_t pn_95_64                        : 32;
+             uint32_t pn_127_96                       : 32;
+             uint32_t last_rx_enqueue_timestamp       : 32;
+             uint32_t last_rx_dequeue_timestamp       : 32;
+             uint32_t ptr_to_next_aging_queue_31_0    : 32;
+             uint32_t ptr_to_next_aging_queue_39_32   :  8,
+                      reserved_11a                    : 24;
+             uint32_t ptr_to_previous_aging_queue_31_0: 32;
+             uint32_t ptr_to_previous_aging_queue_39_32:  8,
+                      reserved_13a                    : 24;
+             uint32_t rx_bitmap_31_0                  : 32;
+             uint32_t rx_bitmap_63_32                 : 32;
+             uint32_t rx_bitmap_95_64                 : 32;
+             uint32_t rx_bitmap_127_96                : 32;
+             uint32_t rx_bitmap_159_128               : 32;
+             uint32_t rx_bitmap_191_160               : 32;
+             uint32_t rx_bitmap_223_192               : 32;
+             uint32_t rx_bitmap_255_224               : 32;
+             uint32_t current_mpdu_count              :  7,
+                      current_msdu_count              : 25;
+             uint32_t reserved_23                     :  4,
+                      timeout_count                   :  6,
+                      forward_due_to_bar_count        :  6,
+                      duplicate_count                 : 16;
+             uint32_t frames_in_order_count           : 24,
+                      bar_received_count              :  8;
+             uint32_t mpdu_frames_processed_count     : 32;
+             uint32_t msdu_frames_processed_count     : 32;
+             uint32_t total_processed_byte_count      : 32;
+             uint32_t late_receive_mpdu_count         : 12,
+                      window_jump_2k                  :  4,
+                      hole_count                      : 16;
+             uint32_t reserved_29                     : 32;
+             uint32_t reserved_30                     : 32;
+             uint32_t reserved_31                     : 32;
+};
+
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_OFFSET                0x00000000
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_LSB                   0
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_MASK                  0x0000000f
+
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET          0x00000000
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB             4
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK            0x000000f0
+
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET          0x00000000
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB             8
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK            0xffffff00
+
+#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET                   0x00000004
+#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB                      0
+#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK                     0x0000ffff
+
+#define RX_REO_QUEUE_1_RESERVED_1B_OFFSET                            0x00000004
+#define RX_REO_QUEUE_1_RESERVED_1B_LSB                               16
+#define RX_REO_QUEUE_1_RESERVED_1B_MASK                              0xffff0000
+
+#define RX_REO_QUEUE_2_VLD_OFFSET                                    0x00000008
+#define RX_REO_QUEUE_2_VLD_LSB                                       0
+#define RX_REO_QUEUE_2_VLD_MASK                                      0x00000001
+
+#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET     0x00000008
+#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB        1
+#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK       0x00000006
+
+#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET            0x00000008
+#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB               3
+#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK              0x00000008
+
+#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET                    0x00000008
+#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB                       4
+#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK                      0x00000010
+
+#define RX_REO_QUEUE_2_AC_OFFSET                                     0x00000008
+#define RX_REO_QUEUE_2_AC_LSB                                        5
+#define RX_REO_QUEUE_2_AC_MASK                                       0x00000060
+
+#define RX_REO_QUEUE_2_BAR_OFFSET                                    0x00000008
+#define RX_REO_QUEUE_2_BAR_LSB                                       7
+#define RX_REO_QUEUE_2_BAR_MASK                                      0x00000080
+
+#define RX_REO_QUEUE_2_RTY_OFFSET                                    0x00000008
+#define RX_REO_QUEUE_2_RTY_LSB                                       8
+#define RX_REO_QUEUE_2_RTY_MASK                                      0x00000100
+
+#define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET                            0x00000008
+#define RX_REO_QUEUE_2_CHK_2K_MODE_LSB                               9
+#define RX_REO_QUEUE_2_CHK_2K_MODE_MASK                              0x00000200
+
+#define RX_REO_QUEUE_2_OOR_MODE_OFFSET                               0x00000008
+#define RX_REO_QUEUE_2_OOR_MODE_LSB                                  10
+#define RX_REO_QUEUE_2_OOR_MODE_MASK                                 0x00000400
+
+#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET                         0x00000008
+#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB                            11
+#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK                           0x0007f800
+
+#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET                        0x00000008
+#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB                           19
+#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK                          0x00080000
+
+#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET                       0x00000008
+#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB                          20
+#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK                         0x00100000
+
+#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET                     0x00000008
+#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB                        21
+#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK                       0x00200000
+
+#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET                     0x00000008
+#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB                        22
+#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK                       0x00400000
+
+#define RX_REO_QUEUE_2_PN_SIZE_OFFSET                                0x00000008
+#define RX_REO_QUEUE_2_PN_SIZE_LSB                                   23
+#define RX_REO_QUEUE_2_PN_SIZE_MASK                                  0x01800000
+
+#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET                      0x00000008
+#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB                         25
+#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK                        0x02000000
+
+#define RX_REO_QUEUE_2_RESERVED_2B_OFFSET                            0x00000008
+#define RX_REO_QUEUE_2_RESERVED_2B_LSB                               26
+#define RX_REO_QUEUE_2_RESERVED_2B_MASK                              0xfc000000
+
+#define RX_REO_QUEUE_3_SVLD_OFFSET                                   0x0000000c
+#define RX_REO_QUEUE_3_SVLD_LSB                                      0
+#define RX_REO_QUEUE_3_SVLD_MASK                                     0x00000001
+
+#define RX_REO_QUEUE_3_SSN_OFFSET                                    0x0000000c
+#define RX_REO_QUEUE_3_SSN_LSB                                       1
+#define RX_REO_QUEUE_3_SSN_MASK                                      0x00001ffe
+
+#define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET                          0x0000000c
+#define RX_REO_QUEUE_3_CURRENT_INDEX_LSB                             13
+#define RX_REO_QUEUE_3_CURRENT_INDEX_MASK                            0x001fe000
+
+#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET             0x0000000c
+#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB                21
+#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK               0x00200000
+
+#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET                 0x0000000c
+#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB                    22
+#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK                   0x00400000
+
+#define RX_REO_QUEUE_3_RESERVED_3A_OFFSET                            0x0000000c
+#define RX_REO_QUEUE_3_RESERVED_3A_LSB                               23
+#define RX_REO_QUEUE_3_RESERVED_3A_MASK                              0x7f800000
+
+#define RX_REO_QUEUE_3_PN_VALID_OFFSET                               0x0000000c
+#define RX_REO_QUEUE_3_PN_VALID_LSB                                  31
+#define RX_REO_QUEUE_3_PN_VALID_MASK                                 0x80000000
+
+#define RX_REO_QUEUE_4_PN_31_0_OFFSET                                0x00000010
+#define RX_REO_QUEUE_4_PN_31_0_LSB                                   0
+#define RX_REO_QUEUE_4_PN_31_0_MASK                                  0xffffffff
+
+#define RX_REO_QUEUE_5_PN_63_32_OFFSET                               0x00000014
+#define RX_REO_QUEUE_5_PN_63_32_LSB                                  0
+#define RX_REO_QUEUE_5_PN_63_32_MASK                                 0xffffffff
+
+#define RX_REO_QUEUE_6_PN_95_64_OFFSET                               0x00000018
+#define RX_REO_QUEUE_6_PN_95_64_LSB                                  0
+#define RX_REO_QUEUE_6_PN_95_64_MASK                                 0xffffffff
+
+#define RX_REO_QUEUE_7_PN_127_96_OFFSET                              0x0000001c
+#define RX_REO_QUEUE_7_PN_127_96_LSB                                 0
+#define RX_REO_QUEUE_7_PN_127_96_MASK                                0xffffffff
+
+#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET              0x00000020
+#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB                 0
+#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK                0xffffffff
+
+#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET              0x00000024
+#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB                 0
+#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK                0xffffffff
+
+#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET          0x00000028
+#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB             0
+#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK            0xffffffff
+
+#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET         0x0000002c
+#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB            0
+#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK           0x000000ff
+
+#define RX_REO_QUEUE_11_RESERVED_11A_OFFSET                          0x0000002c
+#define RX_REO_QUEUE_11_RESERVED_11A_LSB                             8
+#define RX_REO_QUEUE_11_RESERVED_11A_MASK                            0xffffff00
+
+#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET      0x00000030
+#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB         0
+#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK        0xffffffff
+
+#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET     0x00000034
+#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB        0
+#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK       0x000000ff
+
+#define RX_REO_QUEUE_13_RESERVED_13A_OFFSET                          0x00000034
+#define RX_REO_QUEUE_13_RESERVED_13A_LSB                             8
+#define RX_REO_QUEUE_13_RESERVED_13A_MASK                            0xffffff00
+
+#define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET                        0x00000038
+#define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB                           0
+#define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK                          0xffffffff
+
+#define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET                       0x0000003c
+#define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB                          0
+#define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK                         0xffffffff
+
+#define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET                       0x00000040
+#define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB                          0
+#define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK                         0xffffffff
+
+#define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET                      0x00000044
+#define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB                         0
+#define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK                        0xffffffff
+
+#define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET                     0x00000048
+#define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB                        0
+#define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK                       0xffffffff
+
+#define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET                     0x0000004c
+#define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB                        0
+#define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK                       0xffffffff
+
+#define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET                     0x00000050
+#define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB                        0
+#define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK                       0xffffffff
+
+#define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET                     0x00000054
+#define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB                        0
+#define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK                       0xffffffff
+
+#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET                    0x00000058
+#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB                       0
+#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK                      0x0000007f
+
+#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET                    0x00000058
+#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB                       7
+#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK                      0xffffff80
+
+#define RX_REO_QUEUE_23_RESERVED_23_OFFSET                           0x0000005c
+#define RX_REO_QUEUE_23_RESERVED_23_LSB                              0
+#define RX_REO_QUEUE_23_RESERVED_23_MASK                             0x0000000f
+
+#define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET                         0x0000005c
+#define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB                            4
+#define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK                           0x000003f0
+
+#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET              0x0000005c
+#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB                 10
+#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK                0x0000fc00
+
+#define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET                       0x0000005c
+#define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB                          16
+#define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK                         0xffff0000
+
+#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET                 0x00000060
+#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB                    0
+#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK                   0x00ffffff
+
+#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET                    0x00000060
+#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB                       24
+#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK                      0xff000000
+
+#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET           0x00000064
+#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB              0
+#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK             0xffffffff
+
+#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET           0x00000068
+#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB              0
+#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK             0xffffffff
+
+#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET            0x0000006c
+#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB               0
+#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK              0xffffffff
+
+#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET               0x00000070
+#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB                  0
+#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK                 0x00000fff
+
+#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET                        0x00000070
+#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB                           12
+#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK                          0x0000f000
+
+#define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET                            0x00000070
+#define RX_REO_QUEUE_28_HOLE_COUNT_LSB                               16
+#define RX_REO_QUEUE_28_HOLE_COUNT_MASK                              0xffff0000
+
+#define RX_REO_QUEUE_29_RESERVED_29_OFFSET                           0x00000074
+#define RX_REO_QUEUE_29_RESERVED_29_LSB                              0
+#define RX_REO_QUEUE_29_RESERVED_29_MASK                             0xffffffff
+
+#define RX_REO_QUEUE_30_RESERVED_30_OFFSET                           0x00000078
+#define RX_REO_QUEUE_30_RESERVED_30_LSB                              0
+#define RX_REO_QUEUE_30_RESERVED_30_MASK                             0xffffffff
+
+#define RX_REO_QUEUE_31_RESERVED_31_OFFSET                           0x0000007c
+#define RX_REO_QUEUE_31_RESERVED_31_LSB                              0
+#define RX_REO_QUEUE_31_RESERVED_31_MASK                             0xffffffff
+
+#endif

hw/wcn6450/v1/rx_reo_queue_ext.h

@@ -0,0 +1,308 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_REO_QUEUE_EXT_H_
+#define _RX_REO_QUEUE_EXT_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_descriptor_header.h"
+#include "rx_mpdu_link_ptr.h"
+
+#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32
+
+struct rx_reo_queue_ext {
+    struct            uniform_descriptor_header                       descriptor_header;
+             uint32_t reserved_1a                     : 32;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_0;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_1;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_2;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_3;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_4;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_5;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_6;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_7;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_8;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_9;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_10;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_11;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_12;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_13;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_14;
+};
+
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_OFFSET            0x00000000
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_LSB               0
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_MASK              0x0000000f
+
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET      0x00000000
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB         4
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK        0x000000f0
+
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET      0x00000000
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB         8
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK        0xffffff00
+
+#define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET                        0x00000004
+#define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB                           0
+#define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK                          0xffffffff
+
+#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008
+#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010
+#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018
+#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020
+#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028
+#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030
+#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038
+#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040
+#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048
+#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050
+#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058
+#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060
+#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068
+#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070
+#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078
+#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#endif

hw/wcn6450/v1/rx_rxpcu_classification_overview.h

@@ -0,0 +1,77 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1
+
+struct rx_rxpcu_classification_overview {
+             uint32_t filter_pass_mpdus               :  1,
+                      filter_pass_mpdus_fcs_ok        :  1,
+                      monitor_direct_mpdus            :  1,
+                      monitor_direct_mpdus_fcs_ok     :  1,
+                      monitor_other_mpdus             :  1,
+                      monitor_other_mpdus_fcs_ok      :  1,
+                      phyrx_abort_received            :  1,
+                      reserved_0                      :  9,
+                      phy_ppdu_id                     : 16;
+};
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_OFFSET  0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_LSB     0
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_MASK    0x00000001
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_LSB  2
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_LSB   4
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_MASK  0x00000010
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_LSB  6
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_MASK 0x00000040
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_OFFSET         0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_LSB            7
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_MASK           0x0000ff80
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_OFFSET        0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_LSB           16
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_MASK          0xffff0000
+
+#endif

hw/wcn6450/v1/rx_timing_offset_info.h

@@ -0,0 +1,42 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RX_TIMING_OFFSET_INFO_H_
+#define _RX_TIMING_OFFSET_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1
+
+struct rx_timing_offset_info {
+             uint32_t residual_phase_offset           : 12,
+                      reserved                        : 20;
+};
+
+#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_OFFSET         0x00000000
+#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_LSB            0
+#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_MASK           0x00000fff
+
+#define RX_TIMING_OFFSET_INFO_0_RESERVED_OFFSET                      0x00000000
+#define RX_TIMING_OFFSET_INFO_0_RESERVED_LSB                         12
+#define RX_TIMING_OFFSET_INFO_0_RESERVED_MASK                        0xfffff000
+
+#endif

hw/wcn6450/v1/rxpcu_ppdu_end_info.h

@@ -0,0 +1,278 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RXPCU_PPDU_END_INFO_H_
+#define _RXPCU_PPDU_END_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "phyrx_abort_request_info.h"
+#include "macrx_abort_request_info.h"
+
+#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 14
+
+struct rxpcu_ppdu_end_info {
+             uint32_t wb_timestamp_lower_32           : 32;
+             uint32_t wb_timestamp_upper_32           : 32;
+             uint32_t rx_antenna                      : 24,
+                      tx_ht_vht_ack                   :  1,
+                      unsupported_mu_nc               :  1,
+                      otp_txbf_disable                :  1,
+                      previous_tlv_corrupted          :  1,
+                      phyrx_abort_request_info_valid  :  1,
+                      macrx_abort_request_info_valid  :  1,
+                      reserved                        :  2;
+             uint32_t coex_bt_tx_from_start_of_rx     :  1,
+                      coex_bt_tx_after_start_of_rx    :  1,
+                      coex_wan_tx_from_start_of_rx    :  1,
+                      coex_wan_tx_after_start_of_rx   :  1,
+                      coex_wlan_tx_from_start_of_rx   :  1,
+                      coex_wlan_tx_after_start_of_rx  :  1,
+                      mpdu_delimiter_errors_seen      :  1,
+                      __reserved_g_0012                          :  2,
+                      dialog_token                    :  8,
+                      follow_up_dialog_token          :  8,
+                      bb_captured_channel             :  1,
+                      bb_captured_reason              :  3,
+                      bb_captured_timeout             :  1,
+                      reserved_3                      :  2;
+             uint32_t before_mpdu_count_passing_fcs   : 10,
+                      before_mpdu_count_failing_fcs   : 10,
+                      after_mpdu_count_passing_fcs    : 10,
+                      reserved_4                      :  2;
+             uint32_t after_mpdu_count_failing_fcs    : 10,
+                      reserved_5                      : 22;
+             uint32_t phy_timestamp_tx_lower_32       : 32;
+             uint32_t phy_timestamp_tx_upper_32       : 32;
+             uint32_t bb_length                       : 16,
+                      bb_data                         :  1,
+                      reserved_8                      :  3,
+                      first_bt_broadcast_status_details: 12;
+             uint32_t rx_ppdu_duration                : 24,
+                      reserved_9                      :  8;
+             uint32_t ast_index                       : 16,
+                      ast_index_valid                 :  1,
+                      reserved_10                     :  3,
+                      second_bt_broadcast_status_details: 12;
+    struct            phyrx_abort_request_info                       phyrx_abort_request_info_details;
+    struct            macrx_abort_request_info                       macrx_abort_request_info_details;
+             uint16_t pre_bt_broadcast_status_details : 12,
+                      reserved_12a                    :  4;
+             uint32_t rx_ppdu_end_marker              : 32;
+};
+
+#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_OFFSET           0x00000000
+#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_LSB              0
+#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_MASK             0xffffffff
+
+#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_OFFSET           0x00000004
+#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_LSB              0
+#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_MASK             0xffffffff
+
+#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_OFFSET                      0x00000008
+#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_LSB                         0
+#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_MASK                        0x00ffffff
+
+#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_OFFSET                   0x00000008
+#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_LSB                      24
+#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_MASK                     0x01000000
+
+#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_OFFSET               0x00000008
+#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_LSB                  25
+#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_MASK                 0x02000000
+
+#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_OFFSET                0x00000008
+#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_LSB                   26
+#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_MASK                  0x04000000
+
+#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_OFFSET          0x00000008
+#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_LSB             27
+#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_MASK            0x08000000
+
+#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET  0x00000008
+#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_LSB     28
+#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_MASK    0x10000000
+
+#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET  0x00000008
+#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_LSB     29
+#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_MASK    0x20000000
+
+#define RXPCU_PPDU_END_INFO_2_RESERVED_OFFSET                        0x00000008
+#define RXPCU_PPDU_END_INFO_2_RESERVED_LSB                           30
+#define RXPCU_PPDU_END_INFO_2_RESERVED_MASK                          0xc0000000
+
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_OFFSET     0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_LSB        0
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_MASK       0x00000001
+
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_OFFSET    0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_LSB       1
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_MASK      0x00000002
+
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_OFFSET    0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_LSB       2
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_MASK      0x00000004
+
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET   0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_LSB      3
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_MASK     0x00000008
+
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET   0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_LSB      4
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_MASK     0x00000010
+
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET  0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_LSB     5
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_MASK    0x00000020
+
+#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_OFFSET      0x0000000c
+#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_LSB         6
+#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_MASK        0x00000040
+
+#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_OFFSET                    0x0000000c
+#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_LSB                       9
+#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_MASK                      0x0001fe00
+
+#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_OFFSET          0x0000000c
+#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_LSB             17
+#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_MASK            0x01fe0000
+
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_OFFSET             0x0000000c
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_LSB                25
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_MASK               0x02000000
+
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_OFFSET              0x0000000c
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_LSB                 26
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_MASK                0x1c000000
+
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_OFFSET             0x0000000c
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_LSB                29
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_MASK               0x20000000
+
+#define RXPCU_PPDU_END_INFO_3_RESERVED_3_OFFSET                      0x0000000c
+#define RXPCU_PPDU_END_INFO_3_RESERVED_3_LSB                         30
+#define RXPCU_PPDU_END_INFO_3_RESERVED_3_MASK                        0xc0000000
+
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET   0x00000010
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_LSB      0
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_MASK     0x000003ff
+
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET   0x00000010
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_LSB      10
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_MASK     0x000ffc00
+
+#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET    0x00000010
+#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_LSB       20
+#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_MASK      0x3ff00000
+
+#define RXPCU_PPDU_END_INFO_4_RESERVED_4_OFFSET                      0x00000010
+#define RXPCU_PPDU_END_INFO_4_RESERVED_4_LSB                         30
+#define RXPCU_PPDU_END_INFO_4_RESERVED_4_MASK                        0xc0000000
+
+#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET    0x00000014
+#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_LSB       0
+#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_MASK      0x000003ff
+
+#define RXPCU_PPDU_END_INFO_5_RESERVED_5_OFFSET                      0x00000014
+#define RXPCU_PPDU_END_INFO_5_RESERVED_5_LSB                         10
+#define RXPCU_PPDU_END_INFO_5_RESERVED_5_MASK                        0xfffffc00
+
+#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_OFFSET       0x00000018
+#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_LSB          0
+#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_MASK         0xffffffff
+
+#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_OFFSET       0x0000001c
+#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_LSB          0
+#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_MASK         0xffffffff
+
+#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_OFFSET                       0x00000020
+#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_LSB                          0
+#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_MASK                         0x0000ffff
+
+#define RXPCU_PPDU_END_INFO_8_BB_DATA_OFFSET                         0x00000020
+#define RXPCU_PPDU_END_INFO_8_BB_DATA_LSB                            16
+#define RXPCU_PPDU_END_INFO_8_BB_DATA_MASK                           0x00010000
+
+#define RXPCU_PPDU_END_INFO_8_RESERVED_8_OFFSET                      0x00000020
+#define RXPCU_PPDU_END_INFO_8_RESERVED_8_LSB                         17
+#define RXPCU_PPDU_END_INFO_8_RESERVED_8_MASK                        0x000e0000
+
+#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020
+#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB  20
+#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000
+
+#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET                0x00000024
+#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB                   0
+#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK                  0x00ffffff
+
+#define RXPCU_PPDU_END_INFO_9_RESERVED_9_OFFSET                      0x00000024
+#define RXPCU_PPDU_END_INFO_9_RESERVED_9_LSB                         24
+#define RXPCU_PPDU_END_INFO_9_RESERVED_9_MASK                        0xff000000
+
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_OFFSET                      0x00000028
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_LSB                         0
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_MASK                        0x0000ffff
+
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_OFFSET                0x00000028
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_LSB                   16
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_MASK                  0x00010000
+
+#define RXPCU_PPDU_END_INFO_10_RESERVED_10_OFFSET                    0x00000028
+#define RXPCU_PPDU_END_INFO_10_RESERVED_10_LSB                       17
+#define RXPCU_PPDU_END_INFO_10_RESERVED_10_MASK                      0x000e0000
+
+#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028
+#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20
+#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000
+
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff
+
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100
+
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
+
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 10
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc00
+
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000
+
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff
+
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00
+
+#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_OFFSET             0x00000034
+#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_LSB                0
+#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_MASK               0xffffffff
+
+#endif

hw/wcn6450/v1/rxpt_classify_info.h

@@ -0,0 +1,77 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _RXPT_CLASSIFY_INFO_H_
+#define _RXPT_CLASSIFY_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1
+
+struct rxpt_classify_info {
+             uint32_t reo_destination_indication      :  5,
+                      lmac_peer_id_msb                :  2,
+                      use_flow_id_toeplitz_clfy       :  1,
+                      pkt_selection_fp_ucast_data     :  1,
+                      pkt_selection_fp_mcast_data     :  1,
+                      pkt_selection_fp_1000           :  1,
+                      rxdma0_source_ring_selection    :  2,
+                      rxdma0_destination_ring_selection:  2,
+                      reserved_0b                     : 17;
+};
+
+#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_OFFSET       0x00000000
+#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_LSB          0
+#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_MASK         0x0000001f
+
+#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_OFFSET                 0x00000000
+#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_LSB                    5
+#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_MASK                   0x00000060
+
+#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET        0x00000000
+#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_LSB           7
+#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_MASK          0x00000080
+
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_OFFSET      0x00000000
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_LSB         8
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_MASK        0x00000100
+
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_OFFSET      0x00000000
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_LSB         9
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_MASK        0x00000200
+
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_OFFSET            0x00000000
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_LSB               10
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_MASK              0x00000400
+
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_OFFSET     0x00000000
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_LSB        11
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_MASK       0x00001800
+
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_LSB   13
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_MASK  0x00006000
+
+#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_OFFSET                      0x00000000
+#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_LSB                         15
+#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_MASK                        0xffff8000
+
+#endif

hw/wcn6450/v1/seq_hwio.h

@@ -0,0 +1,57 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef __SEQ_H__
+#define __SEQ_H__
+
+#include "HALhwio.h"
+
+#define SEQ_INH(base, regtype, reg) \
+        SEQ_##regtype##_INH(base, reg)
+
+#define SEQ_INMH(base, regtype, reg, mask) \
+        SEQ_##regtype##_INMH(base, reg, mask)
+
+#define SEQ_INFH(base, regtype, reg, fld) \
+        (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld))
+
+#define SEQ_OUTH(base, regtype, reg, val) \
+        SEQ_##regtype##_OUTH(base, reg, val)
+
+#define SEQ_OUTMH(base, regtype, reg, mask, val) \
+        SEQ_##regtype##_OUTMH(base, reg, mask, val)
+
+#define SEQ_OUTFH(base, regtype, reg, fld, val) \
+        SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld))
+
+typedef enum {
+    SEC,
+    MS,
+    US,
+    NS
+} SEQ_TimeUnit;
+
+extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit);
+
+extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt);
+
+#endif
+

hw/wcn6450/v1/tcl_data_cmd.h

@@ -0,0 +1,231 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _TCL_DATA_CMD_H_
+#define _TCL_DATA_CMD_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+#define NUM_OF_DWORDS_TCL_DATA_CMD 7
+
+struct tcl_data_cmd {
+    struct            buffer_addr_info                       buf_addr_info;
+             uint32_t buf_or_ext_desc_type            :  1,
+                      epd                             :  1,
+                      encap_type                      :  2,
+                      encrypt_type                    :  4,
+                      src_buffer_swap                 :  1,
+                      link_meta_swap                  :  1,
+                      tqm_no_drop                     :  1,
+                      reserved_2a                     :  1,
+                      search_type                     :  2,
+                      addrx_en                        :  1,
+                      addry_en                        :  1,
+                      tcl_cmd_number                  : 16;
+             uint32_t data_length                     : 16,
+                      ipv4_checksum_en                :  1,
+                      udp_over_ipv4_checksum_en       :  1,
+                      udp_over_ipv6_checksum_en       :  1,
+                      tcp_over_ipv4_checksum_en       :  1,
+                      tcp_over_ipv6_checksum_en       :  1,
+                      to_fw                           :  1,
+                      reserved_3a                     :  1,
+                      packet_offset                   :  9;
+             uint32_t buffer_timestamp                : 19,
+                      buffer_timestamp_valid          :  1,
+                      reserved_4a                     :  1,
+                      hlos_tid_overwrite              :  1,
+                      hlos_tid                        :  4,
+                      lmac_id                         :  2,
+                      udp_flow_override               :  2,
+                      reserved_4b                     :  2;
+             uint32_t dscp_tid_table_num              :  6,
+                      search_index                    : 20,
+                      cache_set_num                   :  4,
+                      mesh_enable                     :  2;
+             uint32_t reserved_6a                     : 20,
+                      ring_id                         :  8,
+                      looping_count                   :  4;
+};
+
+#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET         0x00000000
+#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB            0
+#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK           0xffffffff
+
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET        0x00000004
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB           0
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK          0x000000ff
+
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET    0x00000004
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB       8
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK      0x00000700
+
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET         0x00000004
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB            11
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK           0xfffff800
+
+#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET                   0x00000008
+#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB                      0
+#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK                     0x00000001
+
+#define TCL_DATA_CMD_2_EPD_OFFSET                                    0x00000008
+#define TCL_DATA_CMD_2_EPD_LSB                                       1
+#define TCL_DATA_CMD_2_EPD_MASK                                      0x00000002
+
+#define TCL_DATA_CMD_2_ENCAP_TYPE_OFFSET                             0x00000008
+#define TCL_DATA_CMD_2_ENCAP_TYPE_LSB                                2
+#define TCL_DATA_CMD_2_ENCAP_TYPE_MASK                               0x0000000c
+
+#define TCL_DATA_CMD_2_ENCRYPT_TYPE_OFFSET                           0x00000008
+#define TCL_DATA_CMD_2_ENCRYPT_TYPE_LSB                              4
+#define TCL_DATA_CMD_2_ENCRYPT_TYPE_MASK                             0x000000f0
+
+#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_OFFSET                        0x00000008
+#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_LSB                           8
+#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_MASK                          0x00000100
+
+#define TCL_DATA_CMD_2_LINK_META_SWAP_OFFSET                         0x00000008
+#define TCL_DATA_CMD_2_LINK_META_SWAP_LSB                            9
+#define TCL_DATA_CMD_2_LINK_META_SWAP_MASK                           0x00000200
+
+#define TCL_DATA_CMD_2_TQM_NO_DROP_OFFSET                            0x00000008
+#define TCL_DATA_CMD_2_TQM_NO_DROP_LSB                               10
+#define TCL_DATA_CMD_2_TQM_NO_DROP_MASK                              0x00000400
+
+#define TCL_DATA_CMD_2_RESERVED_2A_OFFSET                            0x00000008
+#define TCL_DATA_CMD_2_RESERVED_2A_LSB                               11
+#define TCL_DATA_CMD_2_RESERVED_2A_MASK                              0x00000800
+
+#define TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET                            0x00000008
+#define TCL_DATA_CMD_2_SEARCH_TYPE_LSB                               12
+#define TCL_DATA_CMD_2_SEARCH_TYPE_MASK                              0x00003000
+
+#define TCL_DATA_CMD_2_ADDRX_EN_OFFSET                               0x00000008
+#define TCL_DATA_CMD_2_ADDRX_EN_LSB                                  14
+#define TCL_DATA_CMD_2_ADDRX_EN_MASK                                 0x00004000
+
+#define TCL_DATA_CMD_2_ADDRY_EN_OFFSET                               0x00000008
+#define TCL_DATA_CMD_2_ADDRY_EN_LSB                                  15
+#define TCL_DATA_CMD_2_ADDRY_EN_MASK                                 0x00008000
+
+#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_OFFSET                         0x00000008
+#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_LSB                            16
+#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_MASK                           0xffff0000
+
+#define TCL_DATA_CMD_3_DATA_LENGTH_OFFSET                            0x0000000c
+#define TCL_DATA_CMD_3_DATA_LENGTH_LSB                               0
+#define TCL_DATA_CMD_3_DATA_LENGTH_MASK                              0x0000ffff
+
+#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_OFFSET                       0x0000000c
+#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_LSB                          16
+#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_MASK                         0x00010000
+
+#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET              0x0000000c
+#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB                 17
+#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK                0x00020000
+
+#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET              0x0000000c
+#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB                 18
+#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK                0x00040000
+
+#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET              0x0000000c
+#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB                 19
+#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK                0x00080000
+
+#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET              0x0000000c
+#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB                 20
+#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK                0x00100000
+
+#define TCL_DATA_CMD_3_TO_FW_OFFSET                                  0x0000000c
+#define TCL_DATA_CMD_3_TO_FW_LSB                                     21
+#define TCL_DATA_CMD_3_TO_FW_MASK                                    0x00200000
+
+#define TCL_DATA_CMD_3_RESERVED_3A_OFFSET                            0x0000000c
+#define TCL_DATA_CMD_3_RESERVED_3A_LSB                               22
+#define TCL_DATA_CMD_3_RESERVED_3A_MASK                              0x00400000
+
+#define TCL_DATA_CMD_3_PACKET_OFFSET_OFFSET                          0x0000000c
+#define TCL_DATA_CMD_3_PACKET_OFFSET_LSB                             23
+#define TCL_DATA_CMD_3_PACKET_OFFSET_MASK                            0xff800000
+
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_OFFSET                       0x00000010
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_LSB                          0
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_MASK                         0x0007ffff
+
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_OFFSET                 0x00000010
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_LSB                    19
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_MASK                   0x00080000
+
+#define TCL_DATA_CMD_4_RESERVED_4A_OFFSET                            0x00000010
+#define TCL_DATA_CMD_4_RESERVED_4A_LSB                               20
+#define TCL_DATA_CMD_4_RESERVED_4A_MASK                              0x00100000
+
+#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_OFFSET                     0x00000010
+#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_LSB                        21
+#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_MASK                       0x00200000
+
+#define TCL_DATA_CMD_4_HLOS_TID_OFFSET                               0x00000010
+#define TCL_DATA_CMD_4_HLOS_TID_LSB                                  22
+#define TCL_DATA_CMD_4_HLOS_TID_MASK                                 0x03c00000
+
+#define TCL_DATA_CMD_4_LMAC_ID_OFFSET                                0x00000010
+#define TCL_DATA_CMD_4_LMAC_ID_LSB                                   26
+#define TCL_DATA_CMD_4_LMAC_ID_MASK                                  0x0c000000
+
+#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_OFFSET                      0x00000010
+#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_LSB                         28
+#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_MASK                        0x30000000
+
+#define TCL_DATA_CMD_4_RESERVED_4B_OFFSET                            0x00000010
+#define TCL_DATA_CMD_4_RESERVED_4B_LSB                               30
+#define TCL_DATA_CMD_4_RESERVED_4B_MASK                              0xc0000000
+
+#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_OFFSET                     0x00000014
+#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_LSB                        0
+#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_MASK                       0x0000003f
+
+#define TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET                           0x00000014
+#define TCL_DATA_CMD_5_SEARCH_INDEX_LSB                              6
+#define TCL_DATA_CMD_5_SEARCH_INDEX_MASK                             0x03ffffc0
+
+#define TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET                          0x00000014
+#define TCL_DATA_CMD_5_CACHE_SET_NUM_LSB                             26
+#define TCL_DATA_CMD_5_CACHE_SET_NUM_MASK                            0x3c000000
+
+#define TCL_DATA_CMD_5_MESH_ENABLE_OFFSET                            0x00000014
+#define TCL_DATA_CMD_5_MESH_ENABLE_LSB                               30
+#define TCL_DATA_CMD_5_MESH_ENABLE_MASK                              0xc0000000
+
+#define TCL_DATA_CMD_6_RESERVED_6A_OFFSET                            0x00000018
+#define TCL_DATA_CMD_6_RESERVED_6A_LSB                               0
+#define TCL_DATA_CMD_6_RESERVED_6A_MASK                              0x000fffff
+
+#define TCL_DATA_CMD_6_RING_ID_OFFSET                                0x00000018
+#define TCL_DATA_CMD_6_RING_ID_LSB                                   20
+#define TCL_DATA_CMD_6_RING_ID_MASK                                  0x0ff00000
+
+#define TCL_DATA_CMD_6_LOOPING_COUNT_OFFSET                          0x00000018
+#define TCL_DATA_CMD_6_LOOPING_COUNT_LSB                             28
+#define TCL_DATA_CMD_6_LOOPING_COUNT_MASK                            0xf0000000
+
+#endif

hw/wcn6450/v1/tcl_gse_cmd.h

@@ -0,0 +1,112 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _TCL_GSE_CMD_H_
+#define _TCL_GSE_CMD_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_TCL_GSE_CMD 7
+
+struct tcl_gse_cmd {
+             uint32_t control_buffer_addr_31_0        : 32;
+             uint32_t control_buffer_addr_39_32       :  8,
+                      gse_ctrl                        :  4,
+                      gse_sel                         :  1,
+                      status_destination_ring_id      :  1,
+                      swap                            :  1,
+                      index_search_en                 :  1,
+                      cache_set_num                   :  4,
+                      reserved_1a                     : 12;
+             uint32_t cmd_meta_data_31_0              : 32;
+             uint32_t cmd_meta_data_63_32             : 32;
+             uint32_t reserved_4a                     : 32;
+             uint32_t reserved_5a                     : 32;
+             uint32_t reserved_6a                     : 20,
+                      ring_id                         :  8,
+                      looping_count                   :  4;
+};
+
+#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET                0x00000000
+#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB                   0
+#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK                  0xffffffff
+
+#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET               0x00000004
+#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB                  0
+#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK                 0x000000ff
+
+#define TCL_GSE_CMD_1_GSE_CTRL_OFFSET                                0x00000004
+#define TCL_GSE_CMD_1_GSE_CTRL_LSB                                   8
+#define TCL_GSE_CMD_1_GSE_CTRL_MASK                                  0x00000f00
+
+#define TCL_GSE_CMD_1_GSE_SEL_OFFSET                                 0x00000004
+#define TCL_GSE_CMD_1_GSE_SEL_LSB                                    12
+#define TCL_GSE_CMD_1_GSE_SEL_MASK                                   0x00001000
+
+#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET              0x00000004
+#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB                 13
+#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK                0x00002000
+
+#define TCL_GSE_CMD_1_SWAP_OFFSET                                    0x00000004
+#define TCL_GSE_CMD_1_SWAP_LSB                                       14
+#define TCL_GSE_CMD_1_SWAP_MASK                                      0x00004000
+
+#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_OFFSET                         0x00000004
+#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_LSB                            15
+#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_MASK                           0x00008000
+
+#define TCL_GSE_CMD_1_CACHE_SET_NUM_OFFSET                           0x00000004
+#define TCL_GSE_CMD_1_CACHE_SET_NUM_LSB                              16
+#define TCL_GSE_CMD_1_CACHE_SET_NUM_MASK                             0x000f0000
+
+#define TCL_GSE_CMD_1_RESERVED_1A_OFFSET                             0x00000004
+#define TCL_GSE_CMD_1_RESERVED_1A_LSB                                20
+#define TCL_GSE_CMD_1_RESERVED_1A_MASK                               0xfff00000
+
+#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET                      0x00000008
+#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB                         0
+#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK                        0xffffffff
+
+#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET                     0x0000000c
+#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB                        0
+#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK                       0xffffffff
+
+#define TCL_GSE_CMD_4_RESERVED_4A_OFFSET                             0x00000010
+#define TCL_GSE_CMD_4_RESERVED_4A_LSB                                0
+#define TCL_GSE_CMD_4_RESERVED_4A_MASK                               0xffffffff
+
+#define TCL_GSE_CMD_5_RESERVED_5A_OFFSET                             0x00000014
+#define TCL_GSE_CMD_5_RESERVED_5A_LSB                                0
+#define TCL_GSE_CMD_5_RESERVED_5A_MASK                               0xffffffff
+
+#define TCL_GSE_CMD_6_RESERVED_6A_OFFSET                             0x00000018
+#define TCL_GSE_CMD_6_RESERVED_6A_LSB                                0
+#define TCL_GSE_CMD_6_RESERVED_6A_MASK                               0x000fffff
+
+#define TCL_GSE_CMD_6_RING_ID_OFFSET                                 0x00000018
+#define TCL_GSE_CMD_6_RING_ID_LSB                                    20
+#define TCL_GSE_CMD_6_RING_ID_MASK                                   0x0ff00000
+
+#define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET                           0x00000018
+#define TCL_GSE_CMD_6_LOOPING_COUNT_LSB                              28
+#define TCL_GSE_CMD_6_LOOPING_COUNT_MASK                             0xf0000000
+
+#endif

hw/wcn6450/v1/tcl_status_ring.h

@@ -0,0 +1,112 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _TCL_STATUS_RING_H_
+#define _TCL_STATUS_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_TCL_STATUS_RING 8
+
+struct tcl_status_ring {
+             uint32_t gse_ctrl                        :  4,
+                      ase_fse_sel                     :  1,
+                      cache_op_res                    :  2,
+                      index_search_en                 :  1,
+                      msdu_cnt_n                      : 24;
+             uint32_t msdu_byte_cnt_n                 : 32;
+             uint32_t msdu_timestmp_n                 : 32;
+             uint32_t cmd_meta_data_31_0              : 32;
+             uint32_t cmd_meta_data_63_32             : 32;
+             uint32_t hash_indx_val                   : 20,
+                      cache_set_num                   :  4,
+                      reserved_5a                     :  8;
+             uint32_t reserved_6a                     : 32;
+             uint32_t reserved_7a                     : 20,
+                      ring_id                         :  8,
+                      looping_count                   :  4;
+};
+
+#define TCL_STATUS_RING_0_GSE_CTRL_OFFSET                            0x00000000
+#define TCL_STATUS_RING_0_GSE_CTRL_LSB                               0
+#define TCL_STATUS_RING_0_GSE_CTRL_MASK                              0x0000000f
+
+#define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET                         0x00000000
+#define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB                            4
+#define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK                           0x00000010
+
+#define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET                        0x00000000
+#define TCL_STATUS_RING_0_CACHE_OP_RES_LSB                           5
+#define TCL_STATUS_RING_0_CACHE_OP_RES_MASK                          0x00000060
+
+#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_OFFSET                     0x00000000
+#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_LSB                        7
+#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_MASK                       0x00000080
+
+#define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET                          0x00000000
+#define TCL_STATUS_RING_0_MSDU_CNT_N_LSB                             8
+#define TCL_STATUS_RING_0_MSDU_CNT_N_MASK                            0xffffff00
+
+#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET                     0x00000004
+#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB                        0
+#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK                       0xffffffff
+
+#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET                     0x00000008
+#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB                        0
+#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK                       0xffffffff
+
+#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET                  0x0000000c
+#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB                     0
+#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK                    0xffffffff
+
+#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET                 0x00000010
+#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB                    0
+#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK                   0xffffffff
+
+#define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET                       0x00000014
+#define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB                          0
+#define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK                         0x000fffff
+
+#define TCL_STATUS_RING_5_CACHE_SET_NUM_OFFSET                       0x00000014
+#define TCL_STATUS_RING_5_CACHE_SET_NUM_LSB                          20
+#define TCL_STATUS_RING_5_CACHE_SET_NUM_MASK                         0x00f00000
+
+#define TCL_STATUS_RING_5_RESERVED_5A_OFFSET                         0x00000014
+#define TCL_STATUS_RING_5_RESERVED_5A_LSB                            24
+#define TCL_STATUS_RING_5_RESERVED_5A_MASK                           0xff000000
+
+#define TCL_STATUS_RING_6_RESERVED_6A_OFFSET                         0x00000018
+#define TCL_STATUS_RING_6_RESERVED_6A_LSB                            0
+#define TCL_STATUS_RING_6_RESERVED_6A_MASK                           0xffffffff
+
+#define TCL_STATUS_RING_7_RESERVED_7A_OFFSET                         0x0000001c
+#define TCL_STATUS_RING_7_RESERVED_7A_LSB                            0
+#define TCL_STATUS_RING_7_RESERVED_7A_MASK                           0x000fffff
+
+#define TCL_STATUS_RING_7_RING_ID_OFFSET                             0x0000001c
+#define TCL_STATUS_RING_7_RING_ID_LSB                                20
+#define TCL_STATUS_RING_7_RING_ID_MASK                               0x0ff00000
+
+#define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET                       0x0000001c
+#define TCL_STATUS_RING_7_LOOPING_COUNT_LSB                          28
+#define TCL_STATUS_RING_7_LOOPING_COUNT_MASK                         0xf0000000
+
+#endif

hw/wcn6450/v1/tlv_hdr.h

@@ -0,0 +1,123 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _TLV_HDR_H_
+
+#define _TLV_HDR_H_
+
+#if !defined(__ASSEMBLER__)
+
+#endif
+
+struct tlv_usr_16_hdr {
+
+   volatile uint16_t             tlv_cflg_reserved   :   1,
+
+                                 tlv_tag             :   5,
+
+                                 tlv_len             :   4,
+
+                                 tlv_usrid           :   6;
+
+};
+
+struct tlv_16_hdr {
+
+   volatile uint16_t             tlv_cflg_reserved   :   1,
+
+                                 tlv_tag             :   5,
+
+                                 tlv_len             :   4,
+
+                                 tlv_reserved        :   6;
+
+};
+
+struct tlv_usr_32_hdr {
+
+   volatile uint32_t             tlv_cflg_reserved   :   1,
+
+                                 tlv_tag             :   9,
+
+                                 tlv_len             :  16,
+
+                                 tlv_usrid           :   6;
+
+};
+
+struct tlv_32_hdr {
+
+   volatile uint32_t             tlv_cflg_reserved   :   1,
+
+                                 tlv_tag             :   9,
+
+                                 tlv_len             :  16,
+
+                                 tlv_reserved        :   6;
+
+};
+
+struct tlv_usr_42_hdr {
+
+   volatile uint64_t             tlv_compression     :   1,
+
+                                 tlv_tag             :   9,
+
+                                 tlv_len             :  16,
+
+                                 tlv_usrid           :   6,
+
+                                 tlv_reserved        :  10,
+
+                                 pad_42to64_bit      :  22;
+
+};
+
+struct tlv_42_hdr {
+
+   volatile uint64_t             tlv_compression     :   1,
+
+                                 tlv_tag             :   9,
+
+                                 tlv_len             :  16,
+
+                                 tlv_reserved        :  16,
+
+                                 pad_42to64_bit      :  22;
+
+};
+
+struct tlv_usr_c_42_hdr {
+
+   volatile uint64_t             tlv_compression     :   1,
+
+                                 tlv_ctag            :   3,
+
+                                 tlv_usrid           :   6,
+
+                                 tlv_cdata           :  32,
+
+                                 pad_42to64_bit      :  22;
+
+};
+
+#endif
+

hw/wcn6450/v1/tlv_tag_def.h

@@ -0,0 +1,528 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _TLV_TAG_DEF_
+#define _TLV_TAG_DEF_
+
+typedef enum {
+
+  WIFIMACTX_CBF_START_E                    =   0  ,
+  WIFIPHYRX_DATA_E                         =   1  ,
+  WIFIPHYRX_CBF_DATA_RESP_E                =   2  ,
+  WIFIPHYRX_ABORT_REQUEST_E                =   3  ,
+  WIFIPHYRX_USER_ABORT_NOTIFICATION_E      =   4  ,
+  WIFIMACTX_DATA_RESP_E                    =   5  ,
+  WIFIMACTX_CBF_DATA_E                     =   6  ,
+  WIFIMACTX_CBF_DONE_E                     =   7  ,
+  WIFIMACRX_CBF_READ_REQUEST_E             =   8  ,
+  WIFIMACRX_CBF_DATA_REQUEST_E             =   9  ,
+  WIFIMACRX_EXPECT_NDP_RECEPTION_E         =  10  ,
+  WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E       =  11  ,
+  WIFIMACRX_NDP_TIMEOUT_E                  =  12  ,
+  WIFIMACRX_ABORT_ACK_E                    =  13  ,
+  WIFIMACRX_REQ_IMPLICIT_FB_E              =  14  ,
+  WIFIMACRX_CHAIN_MASK_E                   =  15  ,
+  WIFIMACRX_NAP_USER_E                     =  16  ,
+  WIFIMACRX_ABORT_REQUEST_E                =  17  ,
+  WIFIPHYTX_OTHER_TRANSMIT_INFO16_E        =  18  ,
+  WIFIPHYTX_ABORT_ACK_E                    =  19  ,
+  WIFIPHYTX_ABORT_REQUEST_E                =  20  ,
+  WIFIPHYTX_PKT_END_E                      =  21  ,
+  WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E     =  22  ,
+  WIFIPHYTX_REQUEST_CTRL_INFO_E            =  23  ,
+  WIFIPHYTX_DATA_REQUEST_E                 =  24  ,
+  WIFIPHYTX_BF_CV_LOADING_DONE_E           =  25  ,
+  WIFIPHYTX_NAP_ACK_E                      =  26  ,
+  WIFIPHYTX_NAP_DONE_E                     =  27  ,
+  WIFIPHYTX_OFF_ACK_E                      =  28  ,
+  WIFIPHYTX_ON_ACK_E                       =  29  ,
+  WIFIPHYTX_SYNTH_OFF_ACK_E                =  30  ,
+  WIFIPHYTX_DEBUG16_E                      =  31  ,
+  WIFIMACTX_ABORT_REQUEST_E                =  32  ,
+  WIFIMACTX_ABORT_ACK_E                    =  33  ,
+  WIFIMACTX_PKT_END_E                      =  34  ,
+  WIFIMACTX_PRE_PHY_DESC_E                 =  35  ,
+  WIFIMACTX_BF_PARAMS_COMMON_E             =  36  ,
+  WIFIMACTX_BF_PARAMS_PER_USER_E           =  37  ,
+  WIFIMACTX_PREFETCH_CV_E                  =  38  ,
+  WIFIMACTX_USER_DESC_COMMON_E             =  39  ,
+  WIFIMACTX_USER_DESC_PER_USER_E           =  40  ,
+  WIFIEXAMPLE_USER_TLV_16_E                =  41  ,
+  WIFIEXAMPLE_TLV_16_E                     =  42  ,
+  WIFIMACTX_PHY_OFF_E                      =  43  ,
+  WIFIMACTX_PHY_ON_E                       =  44  ,
+  WIFIMACTX_SYNTH_OFF_E                    =  45  ,
+  WIFIMACTX_EXPECT_CBF_COMMON_E            =  46  ,
+  WIFIMACTX_EXPECT_CBF_PER_USER_E          =  47  ,
+  WIFIMACTX_PHY_DESC_E                     =  48  ,
+  WIFIMACTX_L_SIG_A_E                      =  49  ,
+  WIFIMACTX_L_SIG_B_E                      =  50  ,
+  WIFIMACTX_HT_SIG_E                       =  51  ,
+  WIFIMACTX_VHT_SIG_A_E                    =  52  ,
+  WIFIMACTX_VHT_SIG_B_SU20_E               =  53  ,
+  WIFIMACTX_VHT_SIG_B_SU40_E               =  54  ,
+  WIFIMACTX_VHT_SIG_B_SU80_E               =  55  ,
+  WIFIMACTX_VHT_SIG_B_SU160_E              =  56  ,
+  WIFIMACTX_VHT_SIG_B_MU20_E               =  57  ,
+  WIFIMACTX_VHT_SIG_B_MU40_E               =  58  ,
+  WIFIMACTX_VHT_SIG_B_MU80_E               =  59  ,
+  WIFIMACTX_VHT_SIG_B_MU160_E              =  60  ,
+  WIFIMACTX_SERVICE_E                      =  61  ,
+  WIFIMACTX_HE_SIG_A_SU_E                  =  62  ,
+  WIFIMACTX_HE_SIG_A_MU_DL_E               =  63  ,
+  WIFIMACTX_HE_SIG_A_MU_UL_E               =  64  ,
+  WIFIMACTX_HE_SIG_B1_MU_E                 =  65  ,
+  WIFIMACTX_HE_SIG_B2_MU_E                 =  66  ,
+  WIFIMACTX_HE_SIG_B2_OFDMA_E              =  67  ,
+  WIFIMACTX_DELETE_CV_E                    =  68  ,
+  WIFIMACTX_MU_UPLINK_COMMON_E             =  69  ,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_E         =  70  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_E          =  71  ,
+  WIFIMACTX_PHY_NAP_E                      =  72  ,
+  WIFIMACTX_DEBUG_E                        =  73  ,
+  WIFIPHYRX_ABORT_ACK_E                    =  74  ,
+  WIFIPHYRX_GENERATED_CBF_DETAILS_E        =  75  ,
+  WIFIPHYRX_RSSI_LEGACY_E                  =  76  ,
+  WIFIPHYRX_RSSI_HT_E                      =  77  ,
+  WIFIPHYRX_USER_INFO_E                    =  78  ,
+  WIFIPHYRX_PKT_END_E                      =  79  ,
+  WIFIPHYRX_DEBUG_E                        =  80  ,
+  WIFIPHYRX_CBF_TRANSFER_DONE_E            =  81  ,
+  WIFIPHYRX_CBF_TRANSFER_ABORT_E           =  82  ,
+  WIFIPHYRX_L_SIG_A_E                      =  83  ,
+  WIFIPHYRX_L_SIG_B_E                      =  84  ,
+  WIFIPHYRX_HT_SIG_E                       =  85  ,
+  WIFIPHYRX_VHT_SIG_A_E                    =  86  ,
+  WIFIPHYRX_VHT_SIG_B_SU20_E               =  87  ,
+  WIFIPHYRX_VHT_SIG_B_SU40_E               =  88  ,
+  WIFIPHYRX_VHT_SIG_B_SU80_E               =  89  ,
+  WIFIPHYRX_VHT_SIG_B_SU160_E              =  90  ,
+  WIFIPHYRX_VHT_SIG_B_MU20_E               =  91  ,
+  WIFIPHYRX_VHT_SIG_B_MU40_E               =  92  ,
+  WIFIPHYRX_VHT_SIG_B_MU80_E               =  93  ,
+  WIFIPHYRX_VHT_SIG_B_MU160_E              =  94  ,
+  WIFIPHYRX_HE_SIG_A_SU_E                  =  95  ,
+  WIFIPHYRX_HE_SIG_A_MU_DL_E               =  96  ,
+  WIFIPHYRX_HE_SIG_A_MU_UL_E               =  97  ,
+  WIFIPHYRX_HE_SIG_B1_MU_E                 =  98  ,
+  WIFIPHYRX_HE_SIG_B2_MU_E                 =  99  ,
+  WIFIPHYRX_HE_SIG_B2_OFDMA_E              = 100  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_E           = 101  ,
+  WIFIPHYRX_COMMON_USER_INFO_E             = 102  ,
+  WIFIPHYRX_DATA_DONE_E                    = 103  ,
+  WIFIRECEIVE_RSSI_INFO_E                  = 104  ,
+  WIFIRECEIVE_USER_INFO_E                  = 105  ,
+  WIFIMIMO_CONTROL_INFO_E                  = 106  ,
+  WIFIRX_LOCATION_INFO_E                   = 107  ,
+  WIFICOEX_TX_REQ_E                        = 108  ,
+  WIFIDUMMY_E                              = 109  ,
+  WIFIRX_TIMING_OFFSET_INFO_E              = 110  ,
+  WIFIEXAMPLE_TLV_32_NAME_E                = 111  ,
+  WIFIMPDU_LIMIT_E                         = 112  ,
+  WIFINA_LENGTH_END_E                      = 113  ,
+  WIFIOLE_BUF_STATUS_E                     = 114  ,
+  WIFIPCU_PPDU_SETUP_DONE_E                = 115  ,
+  WIFIPCU_PPDU_SETUP_END_E                 = 116  ,
+  WIFIPCU_PPDU_SETUP_INIT_E                = 117  ,
+  WIFIPCU_PPDU_SETUP_START_E               = 118  ,
+  WIFIPDG_FES_SETUP_E                      = 119  ,
+  WIFIPDG_RESPONSE_E                       = 120  ,
+  WIFIPDG_TX_REQ_E                         = 121  ,
+  WIFISCH_WAIT_INSTR_E                     = 122  ,
+  WIFISCHEDULER_TLV_E                      = 123  ,
+  WIFITQM_FLOW_EMPTY_STATUS_E              = 124  ,
+  WIFITQM_FLOW_NOT_EMPTY_STATUS_E          = 125  ,
+  WIFITQM_GEN_MPDU_LENGTH_LIST_E           = 126  ,
+  WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E    = 127  ,
+  WIFITQM_GEN_MPDUS_E                      = 128  ,
+  WIFITQM_GEN_MPDUS_STATUS_E               = 129  ,
+  WIFITQM_REMOVE_MPDU_E                    = 130  ,
+  WIFITQM_REMOVE_MPDU_STATUS_E             = 131  ,
+  WIFITQM_REMOVE_MSDU_E                    = 132  ,
+  WIFITQM_REMOVE_MSDU_STATUS_E             = 133  ,
+  WIFITQM_UPDATE_TX_MPDU_COUNT_E           = 134  ,
+  WIFITQM_WRITE_CMD_E                      = 135  ,
+  WIFIOFDMA_TRIGGER_DETAILS_E              = 136  ,
+  WIFITX_DATA_E                            = 137  ,
+  WIFITX_FES_SETUP_E                       = 138  ,
+  WIFIRX_PACKET_E                          = 139  ,
+  WIFIEXPECTED_RESPONSE_E                  = 140  ,
+  WIFITX_MPDU_END_E                        = 141  ,
+  WIFITX_MPDU_START_E                      = 142  ,
+  WIFITX_MSDU_END_E                        = 143  ,
+  WIFITX_MSDU_START_E                      = 144  ,
+  WIFITX_SW_MODE_SETUP_E                   = 145  ,
+  WIFITXPCU_BUFFER_STATUS_E                = 146  ,
+  WIFITXPCU_USER_BUFFER_STATUS_E           = 147  ,
+  WIFIDATA_TO_TIME_CONFIG_E                = 148  ,
+  WIFIEXAMPLE_USER_TLV_32_E                = 149  ,
+  WIFIMPDU_INFO_E                          = 150  ,
+  WIFIPDG_USER_SETUP_E                     = 151  ,
+  WIFITX_11AH_SETUP_E                      = 152  ,
+  WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E     = 153  ,
+  WIFITX_PEER_ENTRY_E                      = 154  ,
+  WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E       = 155  ,
+  WIFIEXAMPLE_STRUCT_NAME_E                = 156  ,
+  WIFIPCU_PPDU_SETUP_END_INFO_E            = 157  ,
+  WIFIPPDU_RATE_SETTING_E                  = 158  ,
+  WIFIPROT_RATE_SETTING_E                  = 159  ,
+  WIFIRX_MPDU_DETAILS_E                    = 160  ,
+  WIFIEXAMPLE_USER_TLV_42_E                = 161  ,
+  WIFIRX_MSDU_LINK_E                       = 162  ,
+  WIFIRX_REO_QUEUE_E                       = 163  ,
+  WIFIADDR_SEARCH_ENTRY_E                  = 164  ,
+  WIFISCHEDULER_CMD_E                      = 165  ,
+  WIFITX_FLUSH_E                           = 166  ,
+  WIFITQM_ENTRANCE_RING_E                  = 167  ,
+  WIFITX_DATA_WORD_E                       = 168  ,
+  WIFITX_MPDU_DETAILS_E                    = 169  ,
+  WIFITX_MPDU_LINK_E                       = 170  ,
+  WIFITX_MPDU_LINK_PTR_E                   = 171  ,
+  WIFITX_MPDU_QUEUE_HEAD_E                 = 172  ,
+  WIFITX_MPDU_QUEUE_EXT_E                  = 173  ,
+  WIFITX_MPDU_QUEUE_EXT_PTR_E              = 174  ,
+  WIFITX_MSDU_DETAILS_E                    = 175  ,
+  WIFITX_MSDU_EXTENSION_E                  = 176  ,
+  WIFITX_MSDU_FLOW_E                       = 177  ,
+  WIFITX_MSDU_LINK_E                       = 178  ,
+  WIFITX_MSDU_LINK_ENTRY_PTR_E             = 179  ,
+  WIFIRESPONSE_RATE_SETTING_E              = 180  ,
+  WIFITXPCU_BUFFER_BASICS_E                = 181  ,
+  WIFIUNIFORM_DESCRIPTOR_HEADER_E          = 182  ,
+  WIFIUNIFORM_TQM_CMD_HEADER_E             = 183  ,
+  WIFIUNIFORM_TQM_STATUS_HEADER_E          = 184  ,
+  WIFIUSER_RATE_SETTING_E                  = 185  ,
+  WIFIWBM_BUFFER_RING_E                    = 186  ,
+  WIFIWBM_LINK_DESCRIPTOR_RING_E           = 187  ,
+  WIFIWBM_RELEASE_RING_E                   = 188  ,
+  WIFITX_FLUSH_REQ_E                       = 189  ,
+  WIFIRX_MSDU_DETAILS_E                    = 190  ,
+  WIFITQM_WRITE_CMD_STATUS_E               = 191  ,
+  WIFITQM_GET_MPDU_QUEUE_STATS_E           = 192  ,
+  WIFITQM_GET_MSDU_FLOW_STATS_E            = 193  ,
+  WIFIEXAMPLE_USER_CTLV_32_E               = 194  ,
+  WIFITX_FES_STATUS_START_E                = 195  ,
+  WIFITX_FES_STATUS_USER_PPDU_E            = 196  ,
+  WIFITX_FES_STATUS_USER_RESPONSE_E        = 197  ,
+  WIFITX_FES_STATUS_END_E                  = 198  ,
+  WIFIRX_TRIG_INFO_E                       = 199  ,
+  WIFIRXPCU_TX_SETUP_CLEAR_E               = 200  ,
+  WIFIRX_FRAME_BITMAP_REQ_E                = 201  ,
+  WIFIRX_FRAME_BITMAP_ACK_E                = 202  ,
+  WIFICOEX_RX_STATUS_E                     = 203  ,
+  WIFIRX_START_PARAM_E                     = 204  ,
+  WIFIRX_PPDU_START_E                      = 205  ,
+  WIFIRX_PPDU_END_E                        = 206  ,
+  WIFIRX_MPDU_START_E                      = 207  ,
+  WIFIRX_MPDU_END_E                        = 208  ,
+  WIFIRX_MSDU_START_E                      = 209  ,
+  WIFIRX_MSDU_END_E                        = 210  ,
+  WIFIRX_ATTENTION_E                       = 211  ,
+  WIFIRECEIVED_RESPONSE_INFO_E             = 212  ,
+  WIFIRX_PHY_SLEEP_E                       = 213  ,
+  WIFIRX_HEADER_E                          = 214  ,
+  WIFIRX_PEER_ENTRY_E                      = 215  ,
+  WIFIRX_FLUSH_E                           = 216  ,
+  WIFIRX_RESPONSE_REQUIRED_INFO_E          = 217  ,
+  WIFIRX_FRAMELESS_BAR_DETAILS_E           = 218  ,
+  WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E    = 219  ,
+  WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E     = 220  ,
+  WIFITX_CBF_INFO_E                        = 221  ,
+  WIFIPCU_PPDU_SETUP_USER_E                = 222  ,
+  WIFIRX_MPDU_PCU_START_E                  = 223  ,
+  WIFIRX_PM_INFO_E                         = 224  ,
+  WIFIRX_USER_PPDU_END_E                   = 225  ,
+  WIFIRX_PRE_PPDU_START_E                  = 226  ,
+  WIFIRX_PREAMBLE_E                        = 227  ,
+  WIFITX_FES_SETUP_COMPLETE_E              = 228  ,
+  WIFITX_LAST_MPDU_FETCHED_E               = 229  ,
+  WIFITXDMA_STOP_REQUEST_E                 = 230  ,
+  WIFIRXPCU_SETUP_E                        = 231  ,
+  WIFIRXPCU_USER_SETUP_E                   = 232  ,
+  WIFITX_FES_STATUS_ACK_OR_BA_E            = 233  ,
+  WIFITQM_ACKED_MPDU_E                     = 234  ,
+  WIFICOEX_TX_RESP_E                       = 235  ,
+  WIFICOEX_TX_STATUS_E                     = 236  ,
+  WIFIMACTX_COEX_PHY_CTRL_E                = 237  ,
+  WIFICOEX_STATUS_BROADCAST_E              = 238  ,
+  WIFIRESPONSE_START_STATUS_E              = 239  ,
+  WIFIRESPONSE_END_STATUS_E                = 240  ,
+  WIFICRYPTO_STATUS_E                      = 241  ,
+  WIFIRECEIVED_TRIGGER_INFO_E              = 242  ,
+  WIFIREO_ENTRANCE_RING_E                  = 243  ,
+  WIFIRX_MPDU_LINK_E                       = 244  ,
+  WIFICOEX_TX_STOP_CTRL_E                  = 245  ,
+  WIFIRX_PPDU_ACK_REPORT_E                 = 246  ,
+  WIFIRX_PPDU_NO_ACK_REPORT_E              = 247  ,
+  WIFISCH_COEX_STATUS_E                    = 248  ,
+  WIFISCHEDULER_COMMAND_STATUS_E           = 249  ,
+  WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 250  ,
+  WIFITX_FES_STATUS_PROT_E                 = 251  ,
+  WIFITX_FES_STATUS_START_PPDU_E           = 252  ,
+  WIFITX_FES_STATUS_START_PROT_E           = 253  ,
+  WIFITXPCU_PHYTX_DEBUG32_E                = 254  ,
+  WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E  = 255  ,
+  WIFITX_MPDU_COUNT_TRANSFER_END_E         = 256  ,
+  WIFIWHO_ANCHOR_OFFSET_E                  = 257  ,
+  WIFIWHO_ANCHOR_VALUE_E                   = 258  ,
+  WIFIWHO_CCE_INFO_E                       = 259  ,
+  WIFIWHO_COMMIT_E                         = 260  ,
+  WIFIWHO_COMMIT_DONE_E                    = 261  ,
+  WIFIWHO_FLUSH_E                          = 262  ,
+  WIFIWHO_L2_LLC_E                         = 263  ,
+  WIFIWHO_L2_PAYLOAD_E                     = 264  ,
+  WIFIWHO_L3_CHECKSUM_E                    = 265  ,
+  WIFIWHO_L3_INFO_E                        = 266  ,
+  WIFIWHO_L4_CHECKSUM_E                    = 267  ,
+  WIFIWHO_L4_INFO_E                        = 268  ,
+  WIFIWHO_MSDU_E                           = 269  ,
+  WIFIWHO_MSDU_MISC_E                      = 270  ,
+  WIFIWHO_PACKET_DATA_E                    = 271  ,
+  WIFIWHO_PACKET_HDR_E                     = 272  ,
+  WIFIWHO_PPDU_END_E                       = 273  ,
+  WIFIWHO_PPDU_START_E                     = 274  ,
+  WIFIWHO_TSO_E                            = 275  ,
+  WIFIWHO_WMAC_HEADER_PV0_E                = 276  ,
+  WIFIWHO_WMAC_HEADER_PV1_E                = 277  ,
+  WIFIWHO_WMAC_IV_E                        = 278  ,
+  WIFIMPDU_INFO_END_E                      = 279  ,
+  WIFIMPDU_INFO_BITMAP_E                   = 280  ,
+  WIFITX_QUEUE_EXTENSION_E                 = 281  ,
+  WIFIRX_PEER_ENTRY_DETAILS_E              = 282  ,
+  WIFIRX_REO_QUEUE_REFERENCE_E             = 283  ,
+  WIFIRX_REO_QUEUE_EXT_E                   = 284  ,
+  WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E  = 285  ,
+  WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E    = 286  ,
+  WIFITQM_ACKED_MPDU_STATUS_E              = 287  ,
+  WIFITQM_ADD_MSDU_STATUS_E                = 288  ,
+  WIFIRX_MPDU_LINK_PTR_E                   = 289  ,
+  WIFIREO_DESTINATION_RING_E               = 290  ,
+  WIFITQM_LIST_GEN_DONE_E                  = 291  ,
+  WIFIWHO_TERMINATE_E                      = 292  ,
+  WIFITX_LAST_MPDU_END_E                   = 293  ,
+  WIFITX_CV_DATA_E                         = 294  ,
+  WIFITCL_ENTRANCE_FROM_PPE_RING_E         = 295  ,
+  WIFIPPDU_TX_END_E                        = 296  ,
+  WIFIPROT_TX_END_E                        = 297  ,
+  WIFIPDG_RESPONSE_RATE_SETTING_E          = 298  ,
+  WIFIMPDU_INFO_GLOBAL_END_E               = 299  ,
+  WIFITQM_SCH_INSTR_GLOBAL_END_E           = 300  ,
+  WIFIRX_PPDU_END_USER_STATS_E             = 301  ,
+  WIFIRX_PPDU_END_USER_STATS_EXT_E         = 302  ,
+  WIFINO_ACK_REPORT_E                      = 303  ,
+  WIFIACK_REPORT_E                         = 304  ,
+  WIFIUNIFORM_REO_CMD_HEADER_E             = 305  ,
+  WIFIREO_GET_QUEUE_STATS_E                = 306  ,
+  WIFIREO_FLUSH_QUEUE_E                    = 307  ,
+  WIFIREO_FLUSH_CACHE_E                    = 308  ,
+  WIFIREO_UNBLOCK_CACHE_E                  = 309  ,
+  WIFIUNIFORM_REO_STATUS_HEADER_E          = 310  ,
+  WIFIREO_GET_QUEUE_STATS_STATUS_E         = 311  ,
+  WIFIREO_FLUSH_QUEUE_STATUS_E             = 312  ,
+  WIFIREO_FLUSH_CACHE_STATUS_E             = 313  ,
+  WIFIREO_UNBLOCK_CACHE_STATUS_E           = 314  ,
+  WIFITQM_FLUSH_CACHE_E                    = 315  ,
+  WIFITQM_UNBLOCK_CACHE_E                  = 316  ,
+  WIFITQM_FLUSH_CACHE_STATUS_E             = 317  ,
+  WIFITQM_UNBLOCK_CACHE_STATUS_E           = 318  ,
+  WIFIRX_PPDU_END_STATUS_DONE_E            = 319  ,
+  WIFIRX_STATUS_BUFFER_DONE_E              = 320  ,
+  WIFIBUFFER_ADDR_INFO_E                   = 321  ,
+  WIFIRX_MSDU_DESC_INFO_E                  = 322  ,
+  WIFIRX_MPDU_DESC_INFO_E                  = 323  ,
+  WIFITCL_DATA_CMD_E                       = 324  ,
+  WIFITCL_GSE_CMD_E                        = 325  ,
+  WIFITCL_EXIT_BASE_E                      = 326  ,
+  WIFITCL_COMPACT_EXIT_RING_E              = 327  ,
+  WIFITCL_REGULAR_EXIT_RING_E              = 328  ,
+  WIFITCL_EXTENDED_EXIT_RING_E             = 329  ,
+  WIFIUPLINK_COMMON_INFO_E                 = 330  ,
+  WIFIUPLINK_USER_SETUP_INFO_E             = 331  ,
+  WIFITX_DATA_SYNC_E                       = 332  ,
+  WIFIPHYRX_CBF_READ_REQUEST_ACK_E         = 333  ,
+  WIFITCL_STATUS_RING_E                    = 334  ,
+  WIFITQM_GET_MPDU_HEAD_INFO_E             = 335  ,
+  WIFITQM_SYNC_CMD_E                       = 336  ,
+  WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E      = 337  ,
+  WIFITQM_SYNC_CMD_STATUS_E                = 338  ,
+  WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 339  ,
+  WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 340  ,
+  WIFIREO_FLUSH_TIMEOUT_LIST_E             = 341  ,
+  WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E      = 342  ,
+  WIFIREO_TO_PPE_RING_E                    = 343  ,
+  WIFIRX_MPDU_INFO_E                       = 344  ,
+  WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 345  ,
+  WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 346  ,
+  WIFIEXAMPLE_USER_TLV_32_NAME_E           = 347  ,
+  WIFIRX_PPDU_START_USER_INFO_E            = 348  ,
+  WIFIRX_RXPCU_CLASSIFICATION_OVERVIEW_E   = 349  ,
+  WIFIRX_RING_MASK_E                       = 350  ,
+  WIFIWHO_CLASSIFY_INFO_E                  = 351  ,
+  WIFITXPT_CLASSIFY_INFO_E                 = 352  ,
+  WIFIRXPT_CLASSIFY_INFO_E                 = 353  ,
+  WIFITX_FLOW_SEARCH_ENTRY_E               = 354  ,
+  WIFIRX_FLOW_SEARCH_ENTRY_E               = 355  ,
+  WIFIRECEIVED_TRIGGER_INFO_DETAILS_E      = 356  ,
+  WIFICOEX_MAC_NAP_E                       = 357  ,
+  WIFIMACRX_ABORT_REQUEST_INFO_E           = 358  ,
+  WIFIMACTX_ABORT_REQUEST_INFO_E           = 359  ,
+  WIFIPHYRX_ABORT_REQUEST_INFO_E           = 360  ,
+  WIFIPHYTX_ABORT_REQUEST_INFO_E           = 361  ,
+  WIFIRXPCU_PPDU_END_INFO_E                = 362  ,
+  WIFIWHO_MESH_CONTROL_E                   = 363  ,
+  WIFIL_SIG_A_INFO_E                       = 364  ,
+  WIFIL_SIG_B_INFO_E                       = 365  ,
+  WIFIHT_SIG_INFO_E                        = 366  ,
+  WIFIVHT_SIG_A_INFO_E                     = 367  ,
+  WIFIVHT_SIG_B_SU20_INFO_E                = 368  ,
+  WIFIVHT_SIG_B_SU40_INFO_E                = 369  ,
+  WIFIVHT_SIG_B_SU80_INFO_E                = 370  ,
+  WIFIVHT_SIG_B_SU160_INFO_E               = 371  ,
+  WIFIVHT_SIG_B_MU20_INFO_E                = 372  ,
+  WIFIVHT_SIG_B_MU40_INFO_E                = 373  ,
+  WIFIVHT_SIG_B_MU80_INFO_E                = 374  ,
+  WIFIVHT_SIG_B_MU160_INFO_E               = 375  ,
+  WIFISERVICE_INFO_E                       = 376  ,
+  WIFIHE_SIG_A_SU_INFO_E                   = 377  ,
+  WIFIHE_SIG_A_MU_DL_INFO_E                = 378  ,
+  WIFIHE_SIG_A_MU_UL_INFO_E                = 379  ,
+  WIFIHE_SIG_B1_MU_INFO_E                  = 380  ,
+  WIFIHE_SIG_B2_MU_INFO_E                  = 381  ,
+  WIFIHE_SIG_B2_OFDMA_INFO_E               = 382  ,
+  WIFIPDG_SW_MODE_BW_START_E               = 383  ,
+  WIFIPDG_SW_MODE_BW_END_E                 = 384  ,
+  WIFIPDG_WAIT_FOR_MAC_REQUEST_E           = 385  ,
+  WIFIPDG_WAIT_FOR_PHY_REQUEST_E           = 386  ,
+  WIFISCHEDULER_END_E                      = 387  ,
+  WIFIPEER_TABLE_ENTRY_E                   = 388  ,
+  WIFISW_PEER_INFO_E                       = 389  ,
+  WIFIRXOLE_CCE_CLASSIFY_INFO_E            = 390  ,
+  WIFITCL_CCE_CLASSIFY_INFO_E              = 391  ,
+  WIFIRXOLE_CCE_INFO_E                     = 392  ,
+  WIFITCL_CCE_INFO_E                       = 393  ,
+  WIFITCL_CCE_SUPERRULE_E                  = 394  ,
+  WIFICCE_RULE_E                           = 395  ,
+  WIFIRX_PPDU_START_DROPPED_E              = 396  ,
+  WIFIRX_PPDU_END_DROPPED_E                = 397  ,
+  WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E    = 398  ,
+  WIFIRX_MPDU_START_DROPPED_E              = 399  ,
+  WIFIRX_MSDU_START_DROPPED_E              = 400  ,
+  WIFIRX_MSDU_END_DROPPED_E                = 401  ,
+  WIFIRX_MPDU_END_DROPPED_E                = 402  ,
+  WIFIRX_ATTENTION_DROPPED_E               = 403  ,
+  WIFITXPCU_USER_SETUP_E                   = 404  ,
+  WIFIRXPCU_USER_SETUP_EXT_E               = 405  ,
+  WIFICE_SRC_DESC_E                        = 406  ,
+  WIFICE_STAT_DESC_E                       = 407  ,
+  WIFIRXOLE_CCE_SUPERRULE_E                = 408  ,
+  WIFITX_RATE_STATS_INFO_E                 = 409  ,
+  WIFICMD_PART_0_END_E                     = 410  ,
+  WIFIMACTX_SYNTH_ON_E                     = 411  ,
+  WIFISCH_CRITICAL_TLV_REFERENCE_E         = 412  ,
+  WIFITQM_MPDU_GLOBAL_START_E              = 413  ,
+  WIFIEXAMPLE_TLV_32_E                     = 414  ,
+  WIFITQM_UPDATE_TX_MSDU_FLOW_E            = 415  ,
+  WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E      = 416  ,
+  WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E     = 417  ,
+  WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 418  ,
+  WIFIREO_UPDATE_RX_REO_QUEUE_E            = 419  ,
+  WIFICE_DST_DESC_E                        = 420  ,
+  WIFITQM_MPDU_QUEUE_EMPTY_STATUS_E        = 421  ,
+  WIFITQM_2_SCH_MPDU_AVAILABLE_E           = 422  ,
+  WIFIPDG_TRIG_RESPONSE_E                  = 423  ,
+  WIFITRIGGER_RESPONSE_TX_DONE_E           = 424  ,
+  WIFIABORT_FROM_PHYRX_DETAILS_E           = 425  ,
+  WIFISCH_TQM_CMD_WRAPPER_E                = 426  ,
+  WIFIMPDUS_AVAILABLE_E                    = 427  ,
+  WIFIRECEIVED_RESPONSE_INFO_PART2_E       = 428  ,
+  WIFIPHYRX_PKT_END_INFO_E                 = 429  ,
+  WIFIPHYRX_TX_START_TIMING_E              = 430  ,
+  WIFITXPCU_PREAMBLE_DONE_E                = 431  ,
+  WIFINDP_PREAMBLE_DONE_E                  = 432  ,
+  WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E       = 433  ,
+  WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E      = 434  ,
+  WIFIMACTX_CLEAR_PREV_TX_INFO_E           = 435  ,
+  WIFITX_PUNCTURE_SETUP_E                  = 436  ,
+  WIFITX_PUNCTURE_PATTERN_E                = 437  ,
+  WIFIR2R_STATUS_END_E                     = 438  ,
+  WIFIMACTX_PREFETCH_CV_COMMON_E           = 439  ,
+  WIFIEND_OF_FLUSH_MARKER_E                = 440  ,
+  WIFIUPLINK_COMMON_INFO_PUNC_E            = 441  ,
+  WIFIMACTX_MU_UPLINK_COMMON_PUNC_E        = 442  ,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E    = 443  ,
+  WIFIRECEIVED_RESPONSE_USER_7_0_E         = 444  ,
+  WIFIRECEIVED_RESPONSE_USER_15_8_E        = 445  ,
+  WIFIRECEIVED_RESPONSE_USER_23_16_E       = 446  ,
+  WIFIRECEIVED_RESPONSE_USER_31_24_E       = 447  ,
+  WIFIRECEIVED_RESPONSE_USER_36_32_E       = 448  ,
+  WIFIRECEIVED_RESPONSE_USER_INFO_E        = 449  ,
+  WIFITX_LOOPBACK_SETUP_E                  = 450  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 451  ,
+  WIFISCH_WAIT_INSTR_TX_PATH_E             = 452  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E    = 453  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 454  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 455  ,
+  WIFITX_WUR_DATA_E                        = 456  ,
+  WIFIRX_PPDU_END_START_E                  = 457  ,
+  WIFIRX_PPDU_END_MIDDLE_E                 = 458  ,
+  WIFIRX_PPDU_END_LAST_E                   = 459  ,
+  WIFIRECEIVE_USER_INFO_L1_E               = 460  ,
+  WIFIMIMO_CONTROL_INFO_L1_E               = 461  ,
+  WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E   = 462  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 463  ,
+  WIFISRP_INFO_E                           = 464  ,
+  WIFIOBSS_SR_INFO_E                       = 465  ,
+  WIFISCHEDULER_SW_MSG_STATUS_E            = 466  ,
+  WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E  = 467  ,
+  WIFIRXPCU_SETUP_COMPLETE_E               = 468  ,
+  WIFISNOOP_PPDU_START_E                   = 469  ,
+  WIFISNOOP_MPDU_USR_DBG_INFO_E            = 470  ,
+  WIFISNOOP_MSDU_USR_DBG_INFO_E            = 471  ,
+  WIFISNOOP_MSDU_USR_DATA_E                = 472  ,
+  WIFISNOOP_MPDU_USR_STAT_INFO_E           = 473  ,
+  WIFISNOOP_PPDU_END_E                     = 474  ,
+  WIFISNOOP_SPARE_E                        = 475  ,
+  WIFIMACTX_PREFETCH_CV_BULK_E             = 476  ,
+  WIFIMACTX_PREFETCH_CV_BULK_USER_E        = 477  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 478  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 479  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 480  ,
+  WIFISW_MONITOR_RING_E                    = 481  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 482  ,
+  WIFISCH_TLV_WRAPPER_E                    = 483  ,
+  WIFISCHEDULER_STATUS_WRAPPER_E           = 484  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_EXPECT_RX_E = 485  ,
+  WIFITX_HW_MPDU_LINK_E                    = 486  ,
+  WIFITX_HW_MPDU_LINK_PTR_E                = 487  ,
+  WIFITX_HW_MPDU_QUEUE_EXT_E               = 488  ,
+  WIFITX_HW_MPDU_QUEUE_HEAD_E              = 489  ,
+  WIFITQM_ADD_MPDUS_E                      = 490  ,
+  WIFITQM_WRITE_BACK_MPDU_INFO_E           = 491  ,
+  WIFIUNIFORM_TQM_LITE_STATUS_HEADER_E     = 492  ,
+  WIFITQM_ADD_MPDUS_STATUS_E               = 493  ,
+  WIFITQM_MPDU_RELEASE_STATUS_E            = 494  ,
+  WIFITQM_WRITE_BACK_MPDU_INFO_STATUS_E    = 495  ,
+  WIFITX_HW_MPDU_DETAILS_E                 = 496  ,
+  WIFITLV_BASE_E                           = 511
+
+} tlv_tag_def__e;
+
+#endif

hw/wcn6450/v1/tx_msdu_extension.h

@@ -0,0 +1,247 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _TX_MSDU_EXTENSION_H_
+#define _TX_MSDU_EXTENSION_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
+
+struct tx_msdu_extension {
+             uint32_t tso_enable                      :  1,
+                      reserved_0a                     :  6,
+                      tcp_flag                        :  9,
+                      tcp_flag_mask                   :  9,
+                      reserved_0b                     :  7;
+             uint32_t l2_length                       : 16,
+                      ip_length                       : 16;
+             uint32_t tcp_seq_number                  : 32;
+             uint32_t ip_identification               : 16,
+                      udp_length                      : 16;
+             uint32_t checksum_offset                 : 14,
+                      partial_checksum_en             :  1,
+                      reserved_4a                     :  1,
+                      payload_start_offset            : 14,
+                      reserved_4b                     :  2;
+             uint32_t payload_end_offset              : 14,
+                      reserved_5a                     :  2,
+                      wds                             :  1,
+                      reserved_5b                     : 15;
+             uint32_t buf0_ptr_31_0                   : 32;
+             uint32_t buf0_ptr_39_32                  :  8,
+                      reserved_7a                     :  8,
+                      buf0_len                        : 16;
+             uint32_t buf1_ptr_31_0                   : 32;
+             uint32_t buf1_ptr_39_32                  :  8,
+                      reserved_9a                     :  8,
+                      buf1_len                        : 16;
+             uint32_t buf2_ptr_31_0                   : 32;
+             uint32_t buf2_ptr_39_32                  :  8,
+                      reserved_11a                    :  8,
+                      buf2_len                        : 16;
+             uint32_t buf3_ptr_31_0                   : 32;
+             uint32_t buf3_ptr_39_32                  :  8,
+                      reserved_13a                    :  8,
+                      buf3_len                        : 16;
+             uint32_t buf4_ptr_31_0                   : 32;
+             uint32_t buf4_ptr_39_32                  :  8,
+                      reserved_15a                    :  8,
+                      buf4_len                        : 16;
+             uint32_t buf5_ptr_31_0                   : 32;
+             uint32_t buf5_ptr_39_32                  :  8,
+                      reserved_17a                    :  8,
+                      buf5_len                        : 16;
+};
+
+#define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET                        0x00000000
+#define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB                           0
+#define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK                          0x00000001
+
+#define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET                       0x00000000
+#define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB                          1
+#define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK                         0x0000007e
+
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET                          0x00000000
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB                             7
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK                            0x0000ff80
+
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET                     0x00000000
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB                        16
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK                       0x01ff0000
+
+#define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET                       0x00000000
+#define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB                          25
+#define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK                         0xfe000000
+
+#define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET                         0x00000004
+#define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB                            0
+#define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK                           0x0000ffff
+
+#define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET                         0x00000004
+#define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB                            16
+#define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK                           0xffff0000
+
+#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET                    0x00000008
+#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB                       0
+#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK                      0xffffffff
+
+#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET                 0x0000000c
+#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB                    0
+#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK                   0x0000ffff
+
+#define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET                        0x0000000c
+#define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB                           16
+#define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK                          0xffff0000
+
+#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET                   0x00000010
+#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB                      0
+#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK                     0x00003fff
+
+#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET               0x00000010
+#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB                  14
+#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK                 0x00004000
+
+#define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET                       0x00000010
+#define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB                          15
+#define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK                         0x00008000
+
+#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET              0x00000010
+#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB                 16
+#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK                0x3fff0000
+
+#define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET                       0x00000010
+#define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB                          30
+#define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK                         0xc0000000
+
+#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET                0x00000014
+#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB                   0
+#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK                  0x00003fff
+
+#define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET                       0x00000014
+#define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB                          14
+#define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK                         0x0000c000
+
+#define TX_MSDU_EXTENSION_5_WDS_OFFSET                               0x00000014
+#define TX_MSDU_EXTENSION_5_WDS_LSB                                  16
+#define TX_MSDU_EXTENSION_5_WDS_MASK                                 0x00010000
+
+#define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET                       0x00000014
+#define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB                          17
+#define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK                         0xfffe0000
+
+#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET                     0x00000018
+#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB                        0
+#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK                       0xffffffff
+
+#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET                    0x0000001c
+#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB                       0
+#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK                      0x000000ff
+
+#define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET                       0x0000001c
+#define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB                          8
+#define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET                          0x0000001c
+#define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB                             16
+#define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK                            0xffff0000
+
+#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET                     0x00000020
+#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB                        0
+#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK                       0xffffffff
+
+#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET                    0x00000024
+#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB                       0
+#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK                      0x000000ff
+
+#define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET                       0x00000024
+#define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB                          8
+#define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET                          0x00000024
+#define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB                             16
+#define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK                            0xffff0000
+
+#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET                    0x00000028
+#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB                       0
+#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK                      0xffffffff
+
+#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET                   0x0000002c
+#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB                      0
+#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK                     0x000000ff
+
+#define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET                     0x0000002c
+#define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB                        8
+#define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK                       0x0000ff00
+
+#define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET                         0x0000002c
+#define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB                            16
+#define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK                           0xffff0000
+
+#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET                    0x00000030
+#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB                       0
+#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK                      0xffffffff
+
+#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET                   0x00000034
+#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB                      0
+#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK                     0x000000ff
+
+#define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET                     0x00000034
+#define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB                        8
+#define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK                       0x0000ff00
+
+#define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET                         0x00000034
+#define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB                            16
+#define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK                           0xffff0000
+
+#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET                    0x00000038
+#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB                       0
+#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK                      0xffffffff
+
+#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET                   0x0000003c
+#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB                      0
+#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK                     0x000000ff
+
+#define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET                     0x0000003c
+#define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB                        8
+#define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK                       0x0000ff00
+
+#define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET                         0x0000003c
+#define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB                            16
+#define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK                           0xffff0000
+
+#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET                    0x00000040
+#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB                       0
+#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK                      0xffffffff
+
+#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET                   0x00000044
+#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB                      0
+#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK                     0x000000ff
+
+#define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET                     0x00000044
+#define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB                        8
+#define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK                       0x0000ff00
+
+#define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET                         0x00000044
+#define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB                            16
+#define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK                           0xffff0000
+
+#endif

hw/wcn6450/v1/tx_rate_stats_info.h

@@ -0,0 +1,87 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _TX_RATE_STATS_INFO_H_
+#define _TX_RATE_STATS_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2
+
+struct tx_rate_stats_info {
+             uint32_t tx_rate_stats_info_valid        :  1,
+                      transmit_bw                     :  2,
+                      transmit_pkt_type               :  4,
+                      transmit_stbc                   :  1,
+                      transmit_ldpc                   :  1,
+                      transmit_sgi                    :  2,
+                      transmit_mcs                    :  4,
+                      ofdma_transmission              :  1,
+                      tones_in_ru                     : 12,
+                      reserved_0a                     :  4;
+             uint32_t ppdu_transmission_tsf           : 32;
+};
+
+#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_OFFSET         0x00000000
+#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_LSB            0
+#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_MASK           0x00000001
+
+#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_OFFSET                      0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_LSB                         1
+#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_MASK                        0x00000006
+
+#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_OFFSET                0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_LSB                   3
+#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_MASK                  0x00000078
+
+#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_OFFSET                    0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_LSB                       7
+#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_MASK                      0x00000080
+
+#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_OFFSET                    0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_LSB                       8
+#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_MASK                      0x00000100
+
+#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_OFFSET                     0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_LSB                        9
+#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_MASK                       0x00000600
+
+#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_OFFSET                     0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_LSB                        11
+#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_MASK                       0x00007800
+
+#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_OFFSET               0x00000000
+#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_LSB                  15
+#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_MASK                 0x00008000
+
+#define TX_RATE_STATS_INFO_0_TONES_IN_RU_OFFSET                      0x00000000
+#define TX_RATE_STATS_INFO_0_TONES_IN_RU_LSB                         16
+#define TX_RATE_STATS_INFO_0_TONES_IN_RU_MASK                        0x0fff0000
+
+#define TX_RATE_STATS_INFO_0_RESERVED_0A_OFFSET                      0x00000000
+#define TX_RATE_STATS_INFO_0_RESERVED_0A_LSB                         28
+#define TX_RATE_STATS_INFO_0_RESERVED_0A_MASK                        0xf0000000
+
+#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_OFFSET            0x00000004
+#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_LSB               0
+#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_MASK              0xffffffff
+
+#endif

hw/wcn6450/v1/uniform_descriptor_header.h

@@ -0,0 +1,47 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
+#define _UNIFORM_DESCRIPTOR_HEADER_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
+
+struct uniform_descriptor_header {
+             uint32_t owner                           :  4,
+                      buffer_type                     :  4,
+                      reserved_0a                     : 24;
+};
+
+#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_OFFSET                     0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_LSB                        0
+#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_MASK                       0x0000000f
+
+#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_OFFSET               0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_LSB                  4
+#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_MASK                 0x000000f0
+
+#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_OFFSET               0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_LSB                  8
+#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_MASK                 0xffffff00
+
+#endif

hw/wcn6450/v1/uniform_reo_cmd_header.h

@@ -0,0 +1,47 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _UNIFORM_REO_CMD_HEADER_H_
+#define _UNIFORM_REO_CMD_HEADER_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1
+
+struct uniform_reo_cmd_header {
+             uint32_t reo_cmd_number                  : 16,
+                      reo_status_required             :  1,
+                      reserved_0a                     : 15;
+};
+
+#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_OFFSET               0x00000000
+#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_LSB                  0
+#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_MASK                 0x0000ffff
+
+#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_OFFSET          0x00000000
+#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_LSB             16
+#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_MASK            0x00010000
+
+#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_OFFSET                  0x00000000
+#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_LSB                     17
+#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_MASK                    0xfffe0000
+
+#endif

hw/wcn6450/v1/uniform_reo_status_header.h

@@ -0,0 +1,57 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _UNIFORM_REO_STATUS_HEADER_H_
+#define _UNIFORM_REO_STATUS_HEADER_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2
+
+struct uniform_reo_status_header {
+             uint32_t reo_status_number               : 16,
+                      cmd_execution_time              : 10,
+                      reo_cmd_execution_status        :  2,
+                      reserved_0a                     :  4;
+             uint32_t timestamp                       : 32;
+};
+
+#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_OFFSET         0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_LSB            0
+#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_MASK           0x0000ffff
+
+#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_OFFSET        0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_LSB           16
+#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_MASK          0x03ff0000
+
+#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_OFFSET  0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_LSB     26
+#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_MASK    0x0c000000
+
+#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_OFFSET               0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_LSB                  28
+#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_MASK                 0xf0000000
+
+#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_OFFSET                 0x00000004
+#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_LSB                    0
+#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_MASK                   0xffffffff
+
+#endif

hw/wcn6450/v1/vht_sig_a_info.h

@@ -0,0 +1,117 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _VHT_SIG_A_INFO_H_
+#define _VHT_SIG_A_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2
+
+struct vht_sig_a_info {
+             uint32_t bandwidth                       :  2,
+                      vhta_reserved_0                 :  1,
+                      stbc                            :  1,
+                      group_id                        :  6,
+                      n_sts                           : 12,
+                      txop_ps_not_allowed             :  1,
+                      vhta_reserved_0b                :  1,
+                      reserved_0                      :  8;
+             uint32_t gi_setting                      :  2,
+                      su_mu_coding                    :  1,
+                      ldpc_extra_symbol               :  1,
+                      mcs                             :  4,
+                      beamformed                      :  1,
+                      vhta_reserved_1                 :  1,
+                      crc                             :  8,
+                      tail                            :  6,
+                      reserved_1                      :  8;
+};
+
+#define VHT_SIG_A_INFO_0_BANDWIDTH_OFFSET                            0x00000000
+#define VHT_SIG_A_INFO_0_BANDWIDTH_LSB                               0
+#define VHT_SIG_A_INFO_0_BANDWIDTH_MASK                              0x00000003
+
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_OFFSET                      0x00000000
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_LSB                         2
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_MASK                        0x00000004
+
+#define VHT_SIG_A_INFO_0_STBC_OFFSET                                 0x00000000
+#define VHT_SIG_A_INFO_0_STBC_LSB                                    3
+#define VHT_SIG_A_INFO_0_STBC_MASK                                   0x00000008
+
+#define VHT_SIG_A_INFO_0_GROUP_ID_OFFSET                             0x00000000
+#define VHT_SIG_A_INFO_0_GROUP_ID_LSB                                4
+#define VHT_SIG_A_INFO_0_GROUP_ID_MASK                               0x000003f0
+
+#define VHT_SIG_A_INFO_0_N_STS_OFFSET                                0x00000000
+#define VHT_SIG_A_INFO_0_N_STS_LSB                                   10
+#define VHT_SIG_A_INFO_0_N_STS_MASK                                  0x003ffc00
+
+#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_OFFSET                  0x00000000
+#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_LSB                     22
+#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_MASK                    0x00400000
+
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_OFFSET                     0x00000000
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_LSB                        23
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_MASK                       0x00800000
+
+#define VHT_SIG_A_INFO_0_RESERVED_0_OFFSET                           0x00000000
+#define VHT_SIG_A_INFO_0_RESERVED_0_LSB                              24
+#define VHT_SIG_A_INFO_0_RESERVED_0_MASK                             0xff000000
+
+#define VHT_SIG_A_INFO_1_GI_SETTING_OFFSET                           0x00000004
+#define VHT_SIG_A_INFO_1_GI_SETTING_LSB                              0
+#define VHT_SIG_A_INFO_1_GI_SETTING_MASK                             0x00000003
+
+#define VHT_SIG_A_INFO_1_SU_MU_CODING_OFFSET                         0x00000004
+#define VHT_SIG_A_INFO_1_SU_MU_CODING_LSB                            2
+#define VHT_SIG_A_INFO_1_SU_MU_CODING_MASK                           0x00000004
+
+#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET                    0x00000004
+#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_LSB                       3
+#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_MASK                      0x00000008
+
+#define VHT_SIG_A_INFO_1_MCS_OFFSET                                  0x00000004
+#define VHT_SIG_A_INFO_1_MCS_LSB                                     4
+#define VHT_SIG_A_INFO_1_MCS_MASK                                    0x000000f0
+
+#define VHT_SIG_A_INFO_1_BEAMFORMED_OFFSET                           0x00000004
+#define VHT_SIG_A_INFO_1_BEAMFORMED_LSB                              8
+#define VHT_SIG_A_INFO_1_BEAMFORMED_MASK                             0x00000100
+
+#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_OFFSET                      0x00000004
+#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_LSB                         9
+#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_MASK                        0x00000200
+
+#define VHT_SIG_A_INFO_1_CRC_OFFSET                                  0x00000004
+#define VHT_SIG_A_INFO_1_CRC_LSB                                     10
+#define VHT_SIG_A_INFO_1_CRC_MASK                                    0x0003fc00
+
+#define VHT_SIG_A_INFO_1_TAIL_OFFSET                                 0x00000004
+#define VHT_SIG_A_INFO_1_TAIL_LSB                                    18
+#define VHT_SIG_A_INFO_1_TAIL_MASK                                   0x00fc0000
+
+#define VHT_SIG_A_INFO_1_RESERVED_1_OFFSET                           0x00000004
+#define VHT_SIG_A_INFO_1_RESERVED_1_LSB                              24
+#define VHT_SIG_A_INFO_1_RESERVED_1_MASK                             0xff000000
+
+#endif

hw/wcn6450/v1/wbm_buffer_ring.h

@@ -0,0 +1,51 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _WBM_BUFFER_RING_H_
+#define _WBM_BUFFER_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+#define NUM_OF_DWORDS_WBM_BUFFER_RING 2
+
+struct wbm_buffer_ring {
+    struct            buffer_addr_info                       buf_addr_info;
+};
+
+#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET      0x00000000
+#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB         0
+#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK        0xffffffff
+
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET     0x00000004
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB        0
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK       0x000000ff
+
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB    8
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK   0x00000700
+
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET      0x00000004
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB         11
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK        0xfffff800
+
+#endif

hw/wcn6450/v1/wbm_link_descriptor_ring.h

@@ -0,0 +1,51 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _WBM_LINK_DESCRIPTOR_RING_H_
+#define _WBM_LINK_DESCRIPTOR_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2
+
+struct wbm_link_descriptor_ring {
+    struct            buffer_addr_info                       desc_addr_info;
+};
+
+#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#endif

hw/wcn6450/v1/wbm_release_ring.h

@@ -0,0 +1,217 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef _WBM_RELEASE_RING_H_
+#define _WBM_RELEASE_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "tx_rate_stats_info.h"
+
+#define NUM_OF_DWORDS_WBM_RELEASE_RING 8
+
+struct wbm_release_ring {
+    struct            buffer_addr_info                       released_buff_or_desc_addr_info;
+             uint32_t release_source_module           :  3,
+                      bm_action                       :  3,
+                      buffer_or_desc_type             :  3,
+                      first_msdu_index                :  4,
+                      tqm_release_reason              :  4,
+                      rxdma_push_reason               :  2,
+                      rxdma_error_code                :  5,
+                      reo_push_reason                 :  2,
+                      reo_error_code                  :  5,
+                      wbm_internal_error              :  1;
+             uint32_t tqm_status_number               : 24,
+                      transmit_count                  :  7,
+                      msdu_continuation               :  1;
+             uint32_t ack_frame_rssi                  :  8,
+                      sw_release_details_valid        :  1,
+                      first_msdu                      :  1,
+                      last_msdu                       :  1,
+                      msdu_part_of_amsdu              :  1,
+                      fw_tx_notify_frame              :  1,
+                      buffer_timestamp                : 19;
+    struct            tx_rate_stats_info                       tx_rate_stats;
+             uint32_t sw_peer_id                      : 16,
+                      tid                             :  4,
+                      ring_id                         :  8,
+                      looping_count                   :  4;
+};
+
+#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET              0x00000008
+#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB                 0
+#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK                0x00000007
+
+#define WBM_RELEASE_RING_2_BM_ACTION_OFFSET                          0x00000008
+#define WBM_RELEASE_RING_2_BM_ACTION_LSB                             3
+#define WBM_RELEASE_RING_2_BM_ACTION_MASK                            0x00000038
+
+#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET                0x00000008
+#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB                   6
+#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK                  0x000001c0
+
+#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_OFFSET                   0x00000008
+#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_LSB                      9
+#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_MASK                     0x00001e00
+
+#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET                 0x00000008
+#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB                    13
+#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK                   0x0001e000
+
+#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET                  0x00000008
+#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB                     17
+#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK                    0x00060000
+
+#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET                   0x00000008
+#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB                      19
+#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK                     0x00f80000
+
+#define WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET                    0x00000008
+#define WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB                       24
+#define WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK                      0x03000000
+
+#define WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET                     0x00000008
+#define WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB                        26
+#define WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK                       0x7c000000
+
+#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET                 0x00000008
+#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB                    31
+#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK                   0x80000000
+
+#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_OFFSET                  0x0000000c
+#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_LSB                     0
+#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_MASK                    0x00ffffff
+
+#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_OFFSET                     0x0000000c
+#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_LSB                        24
+#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_MASK                       0x7f000000
+
+#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET                  0x0000000c
+#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB                     31
+#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK                    0x80000000
+
+#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_OFFSET                     0x00000010
+#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_LSB                        0
+#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_MASK                       0x000000ff
+
+#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_OFFSET           0x00000010
+#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_LSB              8
+#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_MASK             0x00000100
+
+#define WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET                         0x00000010
+#define WBM_RELEASE_RING_4_FIRST_MSDU_LSB                            9
+#define WBM_RELEASE_RING_4_FIRST_MSDU_MASK                           0x00000200
+
+#define WBM_RELEASE_RING_4_LAST_MSDU_OFFSET                          0x00000010
+#define WBM_RELEASE_RING_4_LAST_MSDU_LSB                             10
+#define WBM_RELEASE_RING_4_LAST_MSDU_MASK                            0x00000400
+
+#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_OFFSET                 0x00000010
+#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_LSB                    11
+#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_MASK                   0x00000800
+
+#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_OFFSET                 0x00000010
+#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_LSB                    12
+#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_MASK                   0x00001000
+
+#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_OFFSET                   0x00000010
+#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_LSB                      13
+#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_MASK                     0xffffe000
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_OFFSET          0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_LSB             1
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_MASK            0x00000006
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET    0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB       3
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK      0x00000078
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_OFFSET        0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_LSB           7
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_MASK          0x00000080
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET        0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_LSB           8
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_MASK          0x00000100
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_OFFSET         0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_LSB            9
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_MASK           0x00000600
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_OFFSET         0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_LSB            11
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_MASK           0x00007800
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET   0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB      15
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK     0x00008000
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_OFFSET          0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_LSB             16
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_MASK            0x0fff0000
+
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_OFFSET          0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_LSB             28
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_MASK            0xf0000000
+
+#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018
+#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB   0
+#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK  0xffffffff
+
+#define WBM_RELEASE_RING_7_SW_PEER_ID_OFFSET                         0x0000001c
+#define WBM_RELEASE_RING_7_SW_PEER_ID_LSB                            0
+#define WBM_RELEASE_RING_7_SW_PEER_ID_MASK                           0x0000ffff
+
+#define WBM_RELEASE_RING_7_TID_OFFSET                                0x0000001c
+#define WBM_RELEASE_RING_7_TID_LSB                                   16
+#define WBM_RELEASE_RING_7_TID_MASK                                  0x000f0000
+
+#define WBM_RELEASE_RING_7_RING_ID_OFFSET                            0x0000001c
+#define WBM_RELEASE_RING_7_RING_ID_LSB                               20
+#define WBM_RELEASE_RING_7_RING_ID_MASK                              0x0ff00000
+
+#define WBM_RELEASE_RING_7_LOOPING_COUNT_OFFSET                      0x0000001c
+#define WBM_RELEASE_RING_7_LOOPING_COUNT_LSB                         28
+#define WBM_RELEASE_RING_7_LOOPING_COUNT_MASK                        0xf0000000
+
+#endif

hw/wcn6450/v1/wcss_seq_hwiobase.h

@@ -0,0 +1,609 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+
+#ifndef __WCSS_SEQ_BASE_H__
+#define __WCSS_SEQ_BASE_H__
+
+#ifdef SCALE_INCLUDES
+	#include "HALhwio.h"
+#else
+	#include "msmhwio.h"
+#endif
+
+#ifndef SOC_WCSS_BASE_ADDR
+    #if defined(WCSS_BASE)
+        #if ( WCSS_BASE != 0x0 )
+            #error WCSS_BASE incorrectly redefined!
+        #endif
+    #endif
+
+    #define SOC_WCSS_BASE_ADDR 0x0
+#else
+    #if ( SOC_WCSS_BASE_ADDR != 0x0 )
+        #error SOC_WCSS_BASE_ADDR incorrectly redefined!
+    #endif
+#endif
+
+#define SEQ_WCSS_UMAC_NOC_OFFSET                                     0x00140000
+#define SEQ_WCSS_PHYA_OFFSET                                         0x00300000
+#define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET                 0x00300000
+#define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET                       0x00338000
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET                 0x00338400
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET                 0x00338800
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET                 0x00338c00
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET                 0x00339000
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET                 0x00339400
+#define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET                0x00339800
+#define SEQ_WCSS_PHYA_WFAX_PCSS_IUSS_REG_MAP_OFFSET                  0x0033f400
+#define SEQ_WCSS_PHYA_WFAX_PCSS_IUSS_COMMON_REG_MAP_OFFSET           0x0033f600
+#define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET                        0x00388000
+#define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET                       0x00390000
+#define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET                       0x003a0000
+#define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET                       0x003b0000
+#define SEQ_WCSS_PHYA_WFAX_DEMFRONT_0_REG_MAP_OFFSET                 0x00400000
+#define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET                      0x00480000
+#define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET                       0x004b0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET                     0x005c0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET             0x005c0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET  0x005cf000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET     0x005cf400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x005cf800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x005cfc00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET     0x005c0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x005c5000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET         0x005d1000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x005d1000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OTP_OFFSET 0x005d1038
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OFFSET     0x005d10cc
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x005c7000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x005c9b00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x005c7000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x005cb000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET             0x005d4000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET         0x005d4000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SW_RST_OFFSET  0x005d41fc
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_RAH_OFFSET      0x005d4204
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET      0x005d4300
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET    0x005d43c0
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x005d4424
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x005d4800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET     0x005d4880
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET      0x005d4c00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET     0x005d5c00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6840
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6900
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6940
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6980
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d69c0
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d7000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d7040
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d7100
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d7140
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d7180
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d71c0
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x005d7c00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET    0x005d7400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x005d7400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x005d7438
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OFFSET 0x005d74cc
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET              0x005d8000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET        0x005d8000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET        0x005d8400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET  0x005d8800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x005d8880
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x005d88c0
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET  0x005d8940
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET  0x005d8980
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET              0x005dc000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET       0x005dc000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DRM_REG_OFFSET   0x005dc400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET      0x005dc800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_OFFSET      0x005dcc00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_OFFSET      0x005dd000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_OFFSET      0x005dd400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x005dd800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET       0x005dd980
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x005dd9c0
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET  0x005ddac0
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET  0x005dfc00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x005dfc40
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET  0x005dfc80
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET  0x005dfcc0
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x005dfd40
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET              0x005e0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x005e0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x005e021c
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x005e1000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1300
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x005e21b8
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x005e4000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x005e8000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x005e821c
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET  0x005e8400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET  0x005e8800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x005e9000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9300
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x005ea000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x005ec000
+#define SEQ_WCSS_UMAC_OFFSET                                         0x00a00000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET                             0x00a20000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET                 0x00a20000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET                0x00a22000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET            0x00a24000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET                 0x00a26000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET                 0x00a28000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET                 0x00a2a000
+#define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET                          0x00a30000
+#define SEQ_WCSS_UMAC_TQM_REG_OFFSET                                 0x00a3c000
+#define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET                           0x00a40000
+#define SEQ_WCSS_WMAC0_OFFSET                                        0x00a80000
+#define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET                            0x00a80000
+#define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET                          0x00a83000
+#define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET                          0x00a86000
+#define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET                           0x00a89000
+#define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET                          0x00a8c000
+#define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET                          0x00a8f000
+#define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET                           0x00a92000
+#define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET                          0x00a95000
+#define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET                   0x00a98000
+#define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET                            0x00a9b000
+#define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET                          0x00a9e000
+#define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET                   0x00aa1000
+#define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET                            0x00aa4000
+#define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET                         0x00aa7000
+#define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET                          0x00aaa000
+#define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET                            0x00ab0000
+#define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET                            0x00ab3000
+#define SEQ_WCSS_APB_TSLV_OFFSET                                     0x00b40000
+#define SEQ_WCSS_TOP_CMN_OFFSET                                      0x00b50000
+#define SEQ_WCSS_WCMN_CORE_OFFSET                                    0x00b58000
+#define SEQ_WCSS_WFSS_PMM_OFFSET                                     0x00b60000
+#define SEQ_WCSS_PMM_TOP_OFFSET                                      0x00b70000
+#define SEQ_WCSS_MSIP_OFFSET                                         0x00b80000
+#define SEQ_WCSS_MSIP_RBIST_TX_CH0_OFFSET                            0x00b80000
+#define SEQ_WCSS_MSIP_WL_DAC_CH0_OFFSET                              0x00b80180
+#define SEQ_WCSS_MSIP_WL_DAC_CALIB_CH0_OFFSET                        0x00b80190
+#define SEQ_WCSS_MSIP_WL_DAC_REGARRAY_CH0_OFFSET                     0x00b80200
+#define SEQ_WCSS_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET                     0x00b802c0
+#define SEQ_WCSS_MSIP_WL_ADC_CH0_OFFSET                              0x00b80400
+#define SEQ_WCSS_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET                     0x00b80434
+#define SEQ_WCSS_MSIP_MSIP_SHD_OTP_OFFSET                            0x00b8d000
+#define SEQ_WCSS_MSIP_MSIP_TMUX_OFFSET                               0x00b8d040
+#define SEQ_WCSS_MSIP_MSIP_OTP_OFFSET                                0x00b8d080
+#define SEQ_WCSS_MSIP_MSIP_LDO_CTRL_OFFSET                           0x00b8d0b4
+#define SEQ_WCSS_MSIP_MSIP_CLKGEN_OFFSET                             0x00b8d100
+#define SEQ_WCSS_MSIP_MSIP_BIAS_OFFSET                               0x00b8e000
+#define SEQ_WCSS_MSIP_BBPLL_OFFSET                                   0x00b8f000
+#define SEQ_WCSS_MSIP_WL_CLKGEN_OFFSET                               0x00b8f800
+#define SEQ_WCSS_MSIP_MSIP_DRM_REG_OFFSET                            0x00b8fc00
+#define SEQ_WCSS_DBG_OFFSET                                          0x00b90000
+#define SEQ_WCSS_DBG_WCSS_DBG_ROM_TABLE_OFFSET                       0x00b90000
+#define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET                         0x00b91000
+#define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET                            0x00b92000
+#define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET                    0x00b94000
+#define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET                     0x00b95000
+#define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET                    0x00b96000
+#define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET                           0x00bb0000
+#define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET              0x00bb1000
+#define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET                               0x00bb2000
+#define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET                0x00bb3000
+#define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET                             0x00bb4000
+#define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET               0x00bb5000
+#define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET                    0x00bb6000
+#define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET                    0x00bb8000
+#define SEQ_WCSS_DBG_TPDM_OFFSET                                     0x00bb9000
+#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280
+#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000
+#define SEQ_WCSS_DBG_TPDA_OFFSET                                     0x00bba000
+#define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET                      0x00bbb000
+#define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET                       0x00bbc000
+#define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET               0x00bbe000
+#define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET               0x00bbf000
+#define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET                        0x00bc0000
+#define SEQ_WCSS_DBG_TRCCNTRS_OFFSET                                 0x00bc1000
+#define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET                  0x00bc4000
+#define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET                     0x00bc5000
+#define SEQ_WCSS_DBG_BTSS_PMM_FUN_CXATBFUNNEL_32W2SP_OFFSET          0x00bc9000
+#define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET                            0x00bd0000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET                            0x00be0000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET                   0x00be0000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET     0x00be4000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET         0x00be5000
+#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET            0x00be6000
+#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET                              0x00c31000
+#define SEQ_WCSS_RET_AHB_OFFSET                                      0x00c90000
+#define SEQ_WCSS_WAHB_TSLV_OFFSET                                    0x00ca0000
+#define SEQ_WCSS_CC_OFFSET                                           0x00cb0000
+#define SEQ_WCSS_UMAC_ACMT_OFFSET                                    0x00cc0000
+
+#define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET                  0x00000000
+#define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET                        0x00038000
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET                  0x00038400
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET                  0x00038800
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET                  0x00038c00
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET                  0x00039000
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET                  0x00039400
+#define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET                 0x00039800
+#define SEQ_WFAX_TOP_WFAX_PCSS_IUSS_REG_MAP_OFFSET                   0x0003f400
+#define SEQ_WFAX_TOP_WFAX_PCSS_IUSS_COMMON_REG_MAP_OFFSET            0x0003f600
+#define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET                         0x00088000
+#define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET                        0x00090000
+#define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET                        0x000a0000
+#define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET                        0x000b0000
+#define SEQ_WFAX_TOP_WFAX_DEMFRONT_0_REG_MAP_OFFSET                  0x00100000
+#define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET                       0x00180000
+#define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET                        0x001b0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET                      0x002c0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET              0x002c0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET   0x002cf000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET      0x002cf400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x002cf800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET  0x002cfc00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET      0x002c0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x002c5000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET          0x002d1000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x002d1000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OTP_OFFSET  0x002d1038
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OFFSET      0x002d10cc
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x002c7000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x002c9b00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x002c7000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x002cb000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET              0x002d4000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET          0x002d4000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SW_RST_OFFSET   0x002d41fc
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_RAH_OFFSET       0x002d4204
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET       0x002d4300
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET     0x002d43c0
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x002d4424
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET  0x002d4800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET      0x002d4880
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET       0x002d4c00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET      0x002d5c00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x002d6800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x002d6840
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x002d6900
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x002d6940
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x002d6980
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x002d69c0
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x002d7000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x002d7040
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x002d7100
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x002d7140
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x002d7180
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x002d71c0
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x002d7c00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET     0x002d7400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x002d7400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x002d7438
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OFFSET 0x002d74cc
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET               0x002d8000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET         0x002d8000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET         0x002d8400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET   0x002d8800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x002d8880
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x002d88c0
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET   0x002d8940
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET   0x002d8980
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET               0x002dc000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET        0x002dc000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DRM_REG_OFFSET    0x002dc400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET       0x002dc800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_OFFSET       0x002dcc00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_OFFSET       0x002dd000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_OFFSET       0x002dd400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x002dd800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET        0x002dd980
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x002dd9c0
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET   0x002ddac0
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET   0x002dfc00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x002dfc40
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET   0x002dfc80
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET   0x002dfcc0
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x002dfd40
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET               0x002e0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET  0x002e0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x002e021c
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x002e1000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x002e1300
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x002e21b8
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x002e4000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET  0x002e8000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x002e821c
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET   0x002e8400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET   0x002e8800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x002e9000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x002e9300
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x002ea000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x002ec000
+
+#define SEQ_RFA_FROM_WSI_RFA_SOC_OFFSET                              0x00000000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_SYSCTRL_OFFSET                   0x0000f000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_TLMM_OFFSET                      0x0000f400
+#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_OVERRIDE_REG_OFFSET              0x0000f800
+#define SEQ_RFA_FROM_WSI_RFA_SOC_AON_1P8_REG_OFFSET                  0x0000fc00
+#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_TLMM_OFFSET                      0x00000000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET             0x00005000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_OFFSET                          0x00011000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET              0x00011000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_OTP_OFFSET                  0x00011038
+#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_OFFSET                      0x000110cc
+#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_OFFSET          0x00007000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00009b00
+#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x00007000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x0000b000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET                              0x00014000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET                          0x00014000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SW_RST_OFFSET                   0x000141fc
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_RAH_OFFSET                       0x00014204
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET                       0x00014300
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET                     0x000143c0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_CAL_OFFSET                 0x00014424
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET                  0x00014800
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET                      0x00014880
+#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET                       0x00014c00
+#define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET                      0x00015c00
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET                 0x00016800
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET               0x00016840
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET               0x00016900
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET                 0x00016940
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET               0x00016980
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET                 0x000169c0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET                 0x00017000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET               0x00017040
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET               0x00017100
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET                 0x00017140
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET               0x00017180
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET                 0x000171c0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET               0x00017c00
+#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_OFFSET                     0x00017400
+#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET         0x00017400
+#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET             0x00017438
+#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_OFFSET                 0x000174cc
+#define SEQ_RFA_FROM_WSI_RFA_FM_OFFSET                               0x00018000
+#define SEQ_RFA_FROM_WSI_RFA_FM_FM_MC_OFFSET                         0x00018000
+#define SEQ_RFA_FROM_WSI_RFA_FM_FM_RX_OFFSET                         0x00018400
+#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BS_OFFSET                   0x00018800
+#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_CLBS_OFFSET                 0x00018880
+#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BIST_OFFSET                 0x000188c0
+#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_PC_OFFSET                   0x00018940
+#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_AC_OFFSET                   0x00018980
+#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET                               0x0001c000
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TOP_OFFSET                        0x0001c000
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DRM_REG_OFFSET                    0x0001c400
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXBB_OFFSET                       0x0001c800
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXFE_OFFSET                       0x0001cc00
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXBB_OFFSET                       0x0001d000
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXFE_OFFSET                       0x0001d400
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET          0x0001d800
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_OFFSET                        0x0001d980
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET         0x0001d9c0
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_MISC_OFFSET                   0x0001dac0
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET                   0x0001fc00
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET                 0x0001fc40
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET                   0x0001fc80
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET                   0x0001fcc0
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_CLBS_OFFSET                 0x0001fd40
+#define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET                               0x00020000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET                  0x00020000
+#define SEQ_RFA_FROM_WSI_RFA_WL_RFA_TGL_2G_CH0_OFFSET                0x0002021c
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET                0x00021000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET                0x00021300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET                 0x000221b8
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH0_OFFSET                 0x00024000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET                  0x00028000
+#define SEQ_RFA_FROM_WSI_RFA_WL_RFA_TGL_5G_CH0_OFFSET                0x0002821c
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET                   0x00028400
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET                   0x00028800
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET                0x00029000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET                0x00029300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET                 0x0002a000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH0_OFFSET                 0x0002c000
+
+#define SEQ_RFA_SOC_AO_SYSCTRL_OFFSET                                0x0000f000
+#define SEQ_RFA_SOC_AO_TLMM_OFFSET                                   0x0000f400
+#define SEQ_RFA_SOC_AO_OVERRIDE_REG_OFFSET                           0x0000f800
+#define SEQ_RFA_SOC_AON_1P8_REG_OFFSET                               0x0000fc00
+#define SEQ_RFA_SOC_HZ_TLMM_OFFSET                                   0x00000000
+#define SEQ_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET                          0x00005000
+#define SEQ_RFA_SOC_PMU_OFFSET                                       0x00011000
+#define SEQ_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET                           0x00011000
+#define SEQ_RFA_SOC_PMU_PMU_OTP_OFFSET                               0x00011038
+#define SEQ_RFA_SOC_PMU_PMU_OFFSET                                   0x000110cc
+#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_OFFSET                       0x00007000
+#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00009b00
+#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET   0x00007000
+#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET  0x0000b000
+
+#define SEQ_PMU_TOP_PMU_SHD_OTP_OFFSET                               0x00000000
+#define SEQ_PMU_TOP_PMU_OTP_OFFSET                                   0x00000038
+#define SEQ_PMU_TOP_PMU_OFFSET                                       0x000000cc
+
+#define SEQ_SECURITY_CONTROL_BT_CMN_SECURITY_CONTROL_CORE_OFFSET     0x00002b00
+#define SEQ_SECURITY_CONTROL_BT_CMN_QFPROM_RAW_FUSE_OFFSET           0x00000000
+#define SEQ_SECURITY_CONTROL_BT_CMN_QFPROM_CORR_FUSE_OFFSET          0x00004000
+
+#define SEQ_RFA_CMN_AON_OFFSET                                       0x00000000
+#define SEQ_RFA_CMN_RFA_SW_RST_OFFSET                                0x000001fc
+#define SEQ_RFA_CMN_WL_RAH_OFFSET                                    0x00000204
+#define SEQ_RFA_CMN_RFFE_M_OFFSET                                    0x00000300
+#define SEQ_RFA_CMN_AON_COEX_OFFSET                                  0x000003c0
+#define SEQ_RFA_CMN_AON_COEX_CAL_OFFSET                              0x00000424
+#define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET                               0x00000800
+#define SEQ_RFA_CMN_RFA_OTP_OFFSET                                   0x00000880
+#define SEQ_RFA_CMN_CLKGEN_OFFSET                                    0x00000c00
+#define SEQ_RFA_CMN_BTFMPLL_OFFSET                                   0x00001c00
+#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET                              0x00002800
+#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET                            0x00002840
+#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET                            0x00002900
+#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET                              0x00002940
+#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET                            0x00002980
+#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET                              0x000029c0
+#define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET                              0x00003000
+#define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET                            0x00003040
+#define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET                            0x00003100
+#define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET                              0x00003140
+#define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET                            0x00003180
+#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET                              0x000031c0
+#define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET                            0x00003c00
+#define SEQ_RFA_CMN_PMU_TEST_OFFSET                                  0x00003400
+#define SEQ_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET                      0x00003400
+#define SEQ_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET                          0x00003438
+#define SEQ_RFA_CMN_PMU_TEST_PMU_OFFSET                              0x000034cc
+
+#define SEQ_RFA_FM_FM_MC_OFFSET                                      0x00000000
+#define SEQ_RFA_FM_FM_RX_OFFSET                                      0x00000400
+#define SEQ_RFA_FM_FM_SYNTH_BS_OFFSET                                0x00000800
+#define SEQ_RFA_FM_FM_SYNTH_CLBS_OFFSET                              0x00000880
+#define SEQ_RFA_FM_FM_SYNTH_BIST_OFFSET                              0x000008c0
+#define SEQ_RFA_FM_FM_SYNTH_PC_OFFSET                                0x00000940
+#define SEQ_RFA_FM_FM_SYNTH_AC_OFFSET                                0x00000980
+
+#define SEQ_RFA_BT_BT_TOP_OFFSET                                     0x00000000
+#define SEQ_RFA_BT_BT_DRM_REG_OFFSET                                 0x00000400
+#define SEQ_RFA_BT_BT_TXBB_OFFSET                                    0x00000800
+#define SEQ_RFA_BT_BT_TXFE_OFFSET                                    0x00000c00
+#define SEQ_RFA_BT_BT_RXBB_OFFSET                                    0x00001000
+#define SEQ_RFA_BT_BT_RXFE_OFFSET                                    0x00001400
+#define SEQ_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET                       0x00001800
+#define SEQ_RFA_BT_BT_DAC_OFFSET                                     0x00001980
+#define SEQ_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET                      0x000019c0
+#define SEQ_RFA_BT_BT_DAC_MISC_OFFSET                                0x00001ac0
+#define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET                                0x00003c00
+#define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET                              0x00003c40
+#define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET                                0x00003c80
+#define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET                                0x00003cc0
+#define SEQ_RFA_BT_BT_SYNTH_CLBS_OFFSET                              0x00003d40
+
+#define SEQ_RFA_WL_WL_MC_2G_CH0_OFFSET                               0x00000000
+#define SEQ_RFA_WL_RFA_TGL_2G_CH0_OFFSET                             0x0000021c
+#define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET                             0x00001000
+#define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET                             0x00001300
+#define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET                              0x000021b8
+#define SEQ_RFA_WL_WL_MEM_2G_CH0_OFFSET                              0x00004000
+#define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET                               0x00008000
+#define SEQ_RFA_WL_RFA_TGL_5G_CH0_OFFSET                             0x0000821c
+#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET                                0x00008400
+#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET                                0x00008800
+#define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET                             0x00009000
+#define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET                             0x00009300
+#define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET                              0x0000a000
+#define SEQ_RFA_WL_WL_MEM_5G_CH0_OFFSET                              0x0000c000
+
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET                          0x00020000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET              0x00020000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET             0x00022000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET         0x00024000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET              0x00026000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET              0x00028000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET              0x0002a000
+#define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET                       0x00030000
+#define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET                              0x0003c000
+#define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET                        0x00040000
+
+#define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET                           0x00000000
+#define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET                          0x00002000
+#define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET                      0x00004000
+#define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET                           0x00006000
+#define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET                           0x00008000
+#define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET                           0x0000a000
+
+#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET                          0x00000000
+#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET                        0x00003000
+#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET                        0x00006000
+#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET                         0x00009000
+#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET                        0x0000c000
+#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET                        0x0000f000
+#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET                         0x00012000
+#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET                        0x00015000
+#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET                 0x00018000
+#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET                          0x0001b000
+#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET                        0x0001e000
+#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET                 0x00021000
+#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET                          0x00024000
+#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET                       0x00027000
+#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET                        0x0002a000
+#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET                          0x00030000
+#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET                          0x00033000
+
+#define SEQ_MSIP_RBIST_TX_CH0_OFFSET                                 0x00000000
+#define SEQ_MSIP_WL_DAC_CH0_OFFSET                                   0x00000180
+#define SEQ_MSIP_WL_DAC_CALIB_CH0_OFFSET                             0x00000190
+#define SEQ_MSIP_WL_DAC_REGARRAY_CH0_OFFSET                          0x00000200
+#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET                          0x000002c0
+#define SEQ_MSIP_WL_ADC_CH0_OFFSET                                   0x00000400
+#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET                          0x00000434
+#define SEQ_MSIP_MSIP_SHD_OTP_OFFSET                                 0x0000d000
+#define SEQ_MSIP_MSIP_TMUX_OFFSET                                    0x0000d040
+#define SEQ_MSIP_MSIP_OTP_OFFSET                                     0x0000d080
+#define SEQ_MSIP_MSIP_LDO_CTRL_OFFSET                                0x0000d0b4
+#define SEQ_MSIP_MSIP_CLKGEN_OFFSET                                  0x0000d100
+#define SEQ_MSIP_MSIP_BIAS_OFFSET                                    0x0000e000
+#define SEQ_MSIP_BBPLL_OFFSET                                        0x0000f000
+#define SEQ_MSIP_WL_CLKGEN_OFFSET                                    0x0000f800
+#define SEQ_MSIP_MSIP_DRM_REG_OFFSET                                 0x0000fc00
+
+#define SEQ_WCSSDBG_WCSS_DBG_ROM_TABLE_OFFSET                        0x00000000
+#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET                          0x00001000
+#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET                             0x00002000
+#define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET                     0x00004000
+#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET                      0x00005000
+#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET                     0x00006000
+#define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET                            0x00020000
+#define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET               0x00021000
+#define SEQ_WCSSDBG_TLV_MACTLV_OFFSET                                0x00022000
+#define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET                 0x00023000
+#define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET                              0x00024000
+#define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET                0x00025000
+#define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET                     0x00026000
+#define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET                     0x00028000
+#define SEQ_WCSSDBG_TPDM_OFFSET                                      0x00029000
+#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280
+#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000
+#define SEQ_WCSSDBG_TPDA_OFFSET                                      0x0002a000
+#define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET                       0x0002b000
+#define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET                        0x0002c000
+#define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET                0x0002e000
+#define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET                0x0002f000
+#define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET                         0x00030000
+#define SEQ_WCSSDBG_TRCCNTRS_OFFSET                                  0x00031000
+#define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET                   0x00034000
+#define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET                      0x00035000
+#define SEQ_WCSSDBG_BTSS_PMM_FUN_CXATBFUNNEL_32W2SP_OFFSET           0x00039000
+#define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET                             0x00040000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET                             0x00050000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET                    0x00050000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET      0x00054000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET          0x00055000
+#define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET             0x00056000
+#define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET                               0x000a1000
+
+#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280
+#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000
+
+#define SEQ_PHYA_DBG_PHYA_NOC_OFFSET                                 0x00000000
+#define SEQ_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET                   0x00004000
+#define SEQ_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET                       0x00005000
+#define SEQ_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET                          0x00006000
+
+#endif
+

hw/wcn6450/v1/wcss_version.h

@@ -0,0 +1,20 @@
+
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define WCSS_VERSION 33