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qcacmn: Default CE_COUNT_MAX to 12

Bladeren bron 
CE_COUNT_MAX should be the maximum number of CE's supported.
Set it to 12 to support all chipsets dynamically.

Change-Id: Id65278ee452a4ca2e3b0dcfe5c082a7e7a286347
CRs-Fixed: 1002084
This commit is contained in:
Houston Hoffman
2016-04-06 15:16:00 -07:00
gecommit door Gerrit - the friendly Code Review server
bovenliggende 6ee559010d
commit d6f946ce21
4 gewijzigde bestanden met toevoegingen van 14 en 11 verwijderingen
Download Patch-bestand Download Diff-bestand Expand all files Collapse all files

4
hif/inc/hif.h
Bestand weergeven

@@ -80,11 +80,7 @@ typedef void *hif_handle_t;
#define TARGET_TYPE_ADRASTEA 16
struct CE_state;
#ifdef QCA_WIFI_3_0_ADRASTEA
#define CE_COUNT_MAX 12
#else
#define CE_COUNT_MAX 8
#endif
/* These numbers are selected so that the product is close to current
higher limit of packets HIF services at one shot (1000) */

13
hif/src/ce/ce_main.c
Bestand weergeven

@@ -1974,7 +1974,7 @@ int hif_ce_fastpath_cb_register(fastpath_msg_handler handler, void *context)
return QDF_STATUS_E_FAILURE;
}
for (i = 0; i < CE_COUNT_MAX; i++) {
for (i = 0; i < scn->ce_count; i++) {
ce_state = scn->ce_id_to_state[i];
if (ce_state->htt_rx_data) {
ce_state->fastpath_handler = handler;
@@ -2175,7 +2175,7 @@ void ce_lro_flush_cb_register(struct hif_opaque_softc *hif_hdl,
QDF_ASSERT(scn != NULL);
for (i = 0; i < CE_COUNT_MAX; i++) {
for (i = 0; i < scn->ce_count; i++) {
ce_state = scn->ce_id_to_state[i];
if (ce_state->htt_rx_data) {
ce_state->lro_flush_cb = handler;
@@ -2201,7 +2201,7 @@ void ce_lro_flush_cb_deregister(struct hif_opaque_softc *hif_hdl)
QDF_ASSERT(scn != NULL);
for (i = 0; i < CE_COUNT_MAX; i++) {
for (i = 0; i < scn->ce_count; i++) {
ce_state = scn->ce_id_to_state[i];
if (ce_state->htt_rx_data) {
ce_state->lro_flush_cb = NULL;
@@ -2431,7 +2431,12 @@ int hif_dump_ce_registers(struct hif_softc *scn)
uint16_t i;
QDF_STATUS status;
for (i = 0; i < CE_COUNT_MAX; i++, ce_reg_address += CE_OFFSET) {
for (i = 0; i < scn->ce_count; i++, ce_reg_address += CE_OFFSET) {
if (scn->ce_id_to_state[i] == NULL) {
HIF_DBG("CE%d not used.", i);
continue;
}
status = hif_diag_read_mem(hif_hdl, ce_reg_address,
(uint8_t *) &ce_reg_values[i][0],
ce_reg_word_size * sizeof(uint32_t));

6
hif/src/ce/ce_tasklet.c
Bestand weergeven

@@ -331,13 +331,14 @@ const char *ce_name[ICNSS_MAX_IRQ_REGISTRATIONS] = {
QDF_STATUS ce_unregister_irq(struct HIF_CE_state *hif_ce_state, uint32_t mask)
{
int id;
int ce_count = HIF_GET_SOFTC(hif_ce_state)->ce_count;
int ret;
if (hif_ce_state == NULL) {
HIF_WARN("%s: hif_ce_state = NULL", __func__);
return QDF_STATUS_SUCCESS;
}
for (id = 0; id < CE_COUNT_MAX; id++) {
for (id = 0; id < ce_count; id++) {
if ((mask & (1 << id)) && hif_ce_state->tasklets[id].inited) {
ret = icnss_ce_free_irq(id,
&hif_ce_state->tasklets[id]);
@@ -362,11 +363,12 @@ QDF_STATUS ce_unregister_irq(struct HIF_CE_state *hif_ce_state, uint32_t mask)
QDF_STATUS ce_register_irq(struct HIF_CE_state *hif_ce_state, uint32_t mask)
{
int id;
int ce_count = HIF_GET_SOFTC(hif_ce_state)->ce_count;
int ret;
unsigned long irqflags = IRQF_TRIGGER_RISING;
uint32_t done_mask = 0;
for (id = 0; id < CE_COUNT_MAX; id++) {
for (id = 0; id < ce_count; id++) {
if ((mask & (1 << id)) && hif_ce_state->tasklets[id].inited) {
ret = icnss_ce_request_irq(id,
hif_snoc_interrupt_handler,

2
hif/src/hif_napi.c
Bestand weergeven

@@ -94,7 +94,7 @@ int hif_napi_create(struct hif_opaque_softc *hif_ctx,
NAPI_DEBUG("NAPI structures initialized");
}
for (i = 0; i < CE_COUNT_MAX; i++) {
for (i = 0; i < hif->ce_count; i++) {
ce_state = hif->ce_id_to_state[i];
NAPI_DEBUG("ce %d: htt_rx=%d htt_rx=%d",
i, ce_state->htt_rx_data,