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@@ -5284,7 +5284,12 @@ static int dsi_display_set_mode_sub(struct dsi_display *display,
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dsi_display_validate_dms_fps(display->panel->cur_mode, mode);
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}
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- if (priv_info->phy_timing_len) {
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+ if (priv_info->phy_timing_len &&
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+ !atomic_read(&display->clkrate_change_pending)) {
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+ /*
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+ * In case of clkrate change, the PHY timing update will happen
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+ * together with the clock update.
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+ */
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display_for_each_ctrl(i, display) {
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ctrl = &display->ctrl[i];
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rc = dsi_phy_set_timing_params(ctrl->phy,
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@@ -8611,9 +8616,12 @@ int dsi_display_pre_kickoff(struct drm_connector *connector,
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struct dsi_display *display,
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struct msm_display_kickoff_params *params)
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{
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+ struct dsi_display_mode *mode;
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int rc = 0, ret = 0;
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int i;
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+ mode = display->panel->cur_mode;
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+
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/* check and setup MISR */
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if (display->misr_enable)
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_dsi_display_setup_misr(display);
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@@ -8641,6 +8649,24 @@ int dsi_display_pre_kickoff(struct drm_connector *connector,
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goto wait_failure;
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}
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+ if (mode->priv_info->phy_timing_len) {
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+ display_for_each_ctrl(i, display) {
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+ struct dsi_display_ctrl *ctrl;
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+ bool commit_phy_timing = false;
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+
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+ if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS)
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+ commit_phy_timing = true;
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+
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+ ctrl = &display->ctrl[i];
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+ ret = dsi_phy_set_timing_params(ctrl->phy,
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+ mode->priv_info->phy_timing_val,
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+ mode->priv_info->phy_timing_len,
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+ commit_phy_timing);
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+ if (ret)
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+ DSI_ERR("failed to add DSI PHY timing params\n");
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+ }
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+ }
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+
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/*
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* Don't check the return value so as not to impact DRM commit
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* when error occurs.
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