qcacmn: Fix active_tasklet_cnt mismatch issue

Issue can be reproduced when test D0WOW ROME PCIE.
Multi interrupts may only trigger tasklet one time,
which will cause active_tasklet_cnt mismatch.

Check tasklet/napi scheduled state

Change-Id: I66b5544c4d57fe91eae75d4cf8578e30b498e1fd
CRs-Fixed: 2070872
This commit is contained in:
Will Huang
2018-06-26 10:53:59 +08:00
committed by nshrivas
parent fe1ee41cd8
commit d6c3b87fcd
3 changed files with 36 additions and 9 deletions

View File

@@ -750,17 +750,14 @@ inline void hif_napi_enable_irq(struct hif_opaque_softc *hif, int id)
* @scn: hif context
* @ce_id: index of napi instance
*
* Return: void
* Return: false if napi didn't enable or already scheduled, otherwise true
*/
int hif_napi_schedule(struct hif_opaque_softc *hif_ctx, int ce_id)
bool hif_napi_schedule(struct hif_opaque_softc *hif_ctx, int ce_id)
{
int cpu = smp_processor_id();
struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx);
struct qca_napi_info *napii;
hif_record_ce_desc_event(scn, ce_id, NAPI_SCHEDULE,
NULL, NULL, 0, 0);
napii = scn->napi_data.napis[ce_id];
if (qdf_unlikely(!napii)) {
HIF_ERROR("%s, scheduling unallocated napi (ce:%d)",
@@ -769,6 +766,14 @@ int hif_napi_schedule(struct hif_opaque_softc *hif_ctx, int ce_id)
return false;
}
if (test_bit(NAPI_STATE_SCHED, &napii->napi.state)) {
NAPI_DEBUG("napi scheduled, return");
qdf_atomic_dec(&scn->active_tasklet_cnt);
return false;
}
hif_record_ce_desc_event(scn, ce_id, NAPI_SCHEDULE,
NULL, NULL, 0, 0);
napii->stats[cpu].napi_schedules++;
NAPI_DEBUG("scheduling napi %d (ce:%d)", napii->id, ce_id);
napi_schedule(&(napii->napi));