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@@ -273,8 +273,14 @@ static int cam_top_tpg_ver1_start(
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soc_info->reg_map[0].mem_base + tpg_reg->tpg_vbi_cfg);
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soc_info->reg_map[0].mem_base + tpg_reg->tpg_vbi_cfg);
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/* Set the TOP tpg mux sel*/
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/* Set the TOP tpg mux sel*/
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- cam_io_w_mb((1 << tpg_hw->hw_intf->hw_idx),
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+ val = cam_io_r_mb(soc_info->reg_map[1].mem_base +
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+ tpg_reg->top_mux_reg_offset);
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+ val |= (1 << tpg_hw->hw_intf->hw_idx);
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+
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+ cam_io_w_mb(val,
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soc_info->reg_map[1].mem_base + tpg_reg->top_mux_reg_offset);
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soc_info->reg_map[1].mem_base + tpg_reg->top_mux_reg_offset);
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+ CAM_DBG(CAM_ISP, "TPG:%d Set top Mux: 0x%x",
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+ tpg_hw->hw_intf->hw_idx, val);
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val = ((tpg_data->num_active_lanes - 1) <<
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val = ((tpg_data->num_active_lanes - 1) <<
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tpg_reg->tpg_num_active_lines_shift) |
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tpg_reg->tpg_num_active_lines_shift) |
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@@ -307,6 +313,7 @@ static int cam_top_tpg_ver1_stop(
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struct cam_isp_resource_node *tpg_res;
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struct cam_isp_resource_node *tpg_res;
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const struct cam_top_tpg_ver1_reg_offset *tpg_reg;
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const struct cam_top_tpg_ver1_reg_offset *tpg_reg;
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struct cam_top_tpg_cfg *tpg_data;
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struct cam_top_tpg_cfg *tpg_data;
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+ uint32_t val;
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if (!hw_priv || !stop_args ||
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if (!hw_priv || !stop_args ||
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(arg_size != sizeof(struct cam_isp_resource_node))) {
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(arg_size != sizeof(struct cam_isp_resource_node))) {
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@@ -333,6 +340,16 @@ static int cam_top_tpg_ver1_stop(
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cam_io_w_mb(0, soc_info->reg_map[0].mem_base +
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cam_io_w_mb(0, soc_info->reg_map[0].mem_base +
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tpg_reg->tpg_ctrl);
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tpg_reg->tpg_ctrl);
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+ /* Reset the TOP tpg mux sel*/
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+ val = cam_io_r_mb(soc_info->reg_map[1].mem_base +
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+ tpg_reg->top_mux_reg_offset);
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+ val &= ~(1 << tpg_hw->hw_intf->hw_idx);
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+
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+ cam_io_w_mb(val,
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+ soc_info->reg_map[1].mem_base + tpg_reg->top_mux_reg_offset);
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+ CAM_DBG(CAM_ISP, "TPG:%d Reset Top Mux: 0x%x",
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+ tpg_hw->hw_intf->hw_idx, val);
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+
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tpg_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED;
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tpg_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED;
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CAM_DBG(CAM_ISP, "TPG:%d stopped", tpg_hw->hw_intf->hw_idx);
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CAM_DBG(CAM_ISP, "TPG:%d stopped", tpg_hw->hw_intf->hw_idx);
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