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@@ -155,6 +155,75 @@ wma_update_eht_cap_support_for_320mhz(struct target_psoc_info *tgt_hdl,
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wma_debug("Support for 320MHz 0x%01x", eht_cap->support_320mhz_6ghz);
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}
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+static void
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+wma_update_eht_20mhz_only_mcs(uint32_t *mcs_2g_20, tDot11fIEeht_cap *eht_cap)
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+{
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+ eht_cap->bw_20_rx_max_nss_for_mcs_0_to_7 |= QDF_GET_BITS(*mcs_2g_20, 0, 4);
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+ eht_cap->bw_20_tx_max_nss_for_mcs_0_to_7 |= QDF_GET_BITS(*mcs_2g_20, 4, 4);
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+ eht_cap->bw_20_rx_max_nss_for_mcs_8_and_9 |= QDF_GET_BITS(*mcs_2g_20, 8, 4);
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+ eht_cap->bw_20_tx_max_nss_for_mcs_8_and_9 |=
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+ QDF_GET_BITS(*mcs_2g_20, 12, 4);
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+ eht_cap->bw_20_rx_max_nss_for_mcs_10_and_11 |=
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+ QDF_GET_BITS(*mcs_2g_20, 16, 4);
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+ eht_cap->bw_20_tx_max_nss_for_mcs_10_and_11 |=
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+ QDF_GET_BITS(*mcs_2g_20, 20, 4);
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+ eht_cap->bw_20_rx_max_nss_for_mcs_12_and_13 |=
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+ QDF_GET_BITS(*mcs_2g_20, 24, 4);
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+ eht_cap->bw_20_tx_max_nss_for_mcs_12_and_13 |=
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+ QDF_GET_BITS(*mcs_2g_20, 28, 4);
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+}
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+
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+static void
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+wma_update_eht_le_80mhz_mcs(uint32_t *mcs_le_80, tDot11fIEeht_cap *eht_cap)
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+{
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+ eht_cap->bw_le_80_rx_max_nss_for_mcs_0_to_9 |=
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+ QDF_GET_BITS(*mcs_le_80, 0, 4);
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+ eht_cap->bw_le_80_tx_max_nss_for_mcs_0_to_9 |=
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+ QDF_GET_BITS(*mcs_le_80, 4, 4);
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+ eht_cap->bw_le_80_rx_max_nss_for_mcs_10_and_11 |=
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+ QDF_GET_BITS(*mcs_le_80, 8, 4);
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+ eht_cap->bw_le_80_tx_max_nss_for_mcs_10_and_11 |=
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+ QDF_GET_BITS(*mcs_le_80, 12, 4);
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+ eht_cap->bw_le_80_rx_max_nss_for_mcs_12_and_13 |=
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+ QDF_GET_BITS(*mcs_le_80, 16, 4);
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+ eht_cap->bw_le_80_tx_max_nss_for_mcs_12_and_13 |=
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+ QDF_GET_BITS(*mcs_le_80, 20, 4);
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+}
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+
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+static void
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+wma_update_eht_160mhz_mcs(uint32_t *mcs_160mhz, tDot11fIEeht_cap *eht_cap)
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+{
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+ eht_cap->bw_160_rx_max_nss_for_mcs_0_to_9 |=
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+ QDF_GET_BITS(*mcs_160mhz, 0, 4);
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+ eht_cap->bw_160_tx_max_nss_for_mcs_0_to_9 |=
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+ QDF_GET_BITS(*mcs_160mhz, 4, 4);
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+ eht_cap->bw_160_rx_max_nss_for_mcs_10_and_11 |=
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+ QDF_GET_BITS(*mcs_160mhz, 8, 4);
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+ eht_cap->bw_160_tx_max_nss_for_mcs_10_and_11 |=
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+ QDF_GET_BITS(*mcs_160mhz, 12, 4);
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+ eht_cap->bw_160_rx_max_nss_for_mcs_12_and_13 |=
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+ QDF_GET_BITS(*mcs_160mhz, 16, 4);
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+ eht_cap->bw_160_tx_max_nss_for_mcs_12_and_13 |=
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+ QDF_GET_BITS(*mcs_160mhz, 20, 4);
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+}
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+
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+static void
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+wma_update_eht_320mhz_mcs(uint32_t *mcs_320mhz, tDot11fIEeht_cap *eht_cap)
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+{
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+ eht_cap->bw_320_rx_max_nss_for_mcs_0_to_9 |=
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+ QDF_GET_BITS(*mcs_320mhz, 0, 4);
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+ eht_cap->bw_320_tx_max_nss_for_mcs_0_to_9 |=
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+ QDF_GET_BITS(*mcs_320mhz, 4, 4);
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+ eht_cap->bw_320_rx_max_nss_for_mcs_10_and_11 |=
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+ QDF_GET_BITS(*mcs_320mhz, 8, 4);
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+ eht_cap->bw_320_tx_max_nss_for_mcs_10_and_11 |=
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+ QDF_GET_BITS(*mcs_320mhz, 12, 4);
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+ eht_cap->bw_320_rx_max_nss_for_mcs_12_and_13 |=
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+ QDF_GET_BITS(*mcs_320mhz, 16, 4);
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+ eht_cap->bw_320_tx_max_nss_for_mcs_12_and_13 |=
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+ QDF_GET_BITS(*mcs_320mhz, 20, 4);
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+}
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+
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void wma_update_target_ext_eht_cap(struct target_psoc_info *tgt_hdl,
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struct wma_tgt_cfg *tgt_cfg)
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{
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@@ -163,9 +232,10 @@ void wma_update_target_ext_eht_cap(struct target_psoc_info *tgt_hdl,
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tDot11fIEeht_cap *eht_cap_5g = &tgt_cfg->eht_cap_5g;
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int i, num_hw_modes, total_mac_phy_cnt;
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tDot11fIEeht_cap eht_cap_mac;
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- struct wlan_psoc_host_mac_phy_caps_ext2 *mac_cap, *mac_phy_cap;
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+ struct wlan_psoc_host_mac_phy_caps_ext2 *mac_phy_cap, *mac_phy_caps2;
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struct wlan_psoc_host_mac_phy_caps *host_cap;
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uint32_t supported_bands;
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+ uint32_t *mcs_supp;
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qdf_mem_zero(eht_cap_2g, sizeof(tDot11fIEeht_cap));
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qdf_mem_zero(eht_cap_5g, sizeof(tDot11fIEeht_cap));
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@@ -194,24 +264,45 @@ void wma_update_target_ext_eht_cap(struct target_psoc_info *tgt_hdl,
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supported_bands = host_cap->supported_bands;
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for (i = 0; i < total_mac_phy_cnt; i++) {
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qdf_mem_zero(&eht_cap_mac, sizeof(tDot11fIEeht_cap));
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- mac_cap = &mac_phy_cap[i];
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+ mac_phy_caps2 = &mac_phy_cap[i];
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if (supported_bands & WLAN_2G_CAPABILITY) {
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wma_convert_eht_cap(&eht_cap_mac,
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- mac_cap->eht_cap_info_2G,
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- mac_cap->eht_cap_phy_info_2G);
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+ mac_phy_caps2->eht_cap_info_2G,
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+ mac_phy_caps2->eht_cap_phy_info_2G);
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wma_convert_eht_cap(eht_cap_2g,
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- mac_cap->eht_cap_info_2G,
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- mac_cap->eht_cap_phy_info_2G);
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+ mac_phy_caps2->eht_cap_info_2G,
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+ mac_phy_caps2->eht_cap_phy_info_2G);
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+ /* TODO: PPET */
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+ /* WMI_EHT_SUPP_MCS_20MHZ_ONLY */
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+ mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_2G[0];
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+ wma_update_eht_20mhz_only_mcs(mcs_supp, &eht_cap_mac);
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+ /* WMI_EHT_SUPP_MCS_LE_80MHZ */
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+ mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_2G[1];
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+ wma_update_eht_le_80mhz_mcs(mcs_supp, &eht_cap_mac);
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}
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if (supported_bands & WLAN_5G_CAPABILITY) {
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qdf_mem_zero(&eht_cap_mac, sizeof(tDot11fIEeht_cap));
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wma_convert_eht_cap(&eht_cap_mac,
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- mac_cap->eht_cap_info_5G,
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- mac_cap->eht_cap_phy_info_5G);
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+ mac_phy_caps2->eht_cap_info_5G,
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+ mac_phy_caps2->eht_cap_phy_info_5G);
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wma_convert_eht_cap(eht_cap_5g,
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- mac_cap->eht_cap_info_5G,
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- mac_cap->eht_cap_phy_info_5G);
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+ mac_phy_caps2->eht_cap_info_5G,
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+ mac_phy_caps2->eht_cap_phy_info_5G);
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+
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+ /* WMI_EHT_SUPP_MCS_20MHZ_ONLY */
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+ mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_5G[0];
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+ wma_update_eht_20mhz_only_mcs(mcs_supp, &eht_cap_mac);
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+ /* WMI_EHT_SUPP_MCS_LE_80MHZ */
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+ mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_5G[1];
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+ wma_update_eht_le_80mhz_mcs(mcs_supp, &eht_cap_mac);
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+
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+ /* WMI_EHT_SUPP_MCS_160MHZ */
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+ mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_5G[1];
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+ wma_update_eht_160mhz_mcs(mcs_supp, &eht_cap_mac);
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+ /* WMI_EHT_SUPP_MCS_320MHZ */
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+ mcs_supp = &mac_phy_caps2->eht_supp_mcs_ext_5G[2];
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+ wma_update_eht_320mhz_mcs(mcs_supp, &eht_cap_mac);
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}
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}
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qdf_mem_copy(eht_cap, &eht_cap_mac, sizeof(tDot11fIEeht_cap));
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@@ -327,6 +418,58 @@ void wma_print_eht_cap(tDot11fIEeht_cap *eht_cap)
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eht_cap->rx_1k_qam_in_wider_bw_dl_ofdma);
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wma_nofl_debug("\tRx 4096-QAM in wider bandwidth DL OFDMA support: 0x%01x",
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eht_cap->rx_4k_qam_in_wider_bw_dl_ofdma);
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+ wma_nofl_debug("\t EHT MCS 20 rx 0-7 0x%x",
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+ eht_cap->bw_20_rx_max_nss_for_mcs_0_to_7);
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+ wma_nofl_debug("\t EHT MCS 20 tx 0-7 0x%x",
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+ eht_cap->bw_20_tx_max_nss_for_mcs_0_to_7);
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+ wma_nofl_debug("\t EHT MCS 20 rx 8-9 0x%x",
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+ eht_cap->bw_20_rx_max_nss_for_mcs_8_and_9);
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+ wma_nofl_debug("\t EHT MCS 20 tx 8-9 0x%x",
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+ eht_cap->bw_20_tx_max_nss_for_mcs_8_and_9);
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+ wma_nofl_debug("\t EHT MCS 20 rx 10-11 0x%x",
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+ eht_cap->bw_20_rx_max_nss_for_mcs_10_and_11);
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+ wma_nofl_debug("\t EHT MCS 20 tx 10-11 0x%x",
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+ eht_cap->bw_20_tx_max_nss_for_mcs_10_and_11);
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+ wma_nofl_debug("\t EHT MCS 20 rx 12-13 0x%x",
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+ eht_cap->bw_20_rx_max_nss_for_mcs_12_and_13);
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+ wma_nofl_debug("\t EHT MCS 20 tx 12-13 0x%x",
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+ eht_cap->bw_20_tx_max_nss_for_mcs_12_and_13);
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+ wma_nofl_debug("\t EHT MCS 80 rx 0-9 0x%x",
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+ eht_cap->bw_le_80_rx_max_nss_for_mcs_0_to_9);
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+ wma_nofl_debug("\t EHT MCS 80 tx 0-9 0x%x",
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+ eht_cap->bw_le_80_tx_max_nss_for_mcs_0_to_9);
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+ wma_nofl_debug("\t EHT MCS 80 rx 10-11 0x%x",
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+ eht_cap->bw_le_80_rx_max_nss_for_mcs_10_and_11);
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+ wma_nofl_debug("\t EHT MCS 80 tx 10-11 0x%x",
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+ eht_cap->bw_le_80_tx_max_nss_for_mcs_10_and_11);
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+ wma_nofl_debug("\t EHT MCS 80 rx 12-13 0x%x",
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+ eht_cap->bw_le_80_rx_max_nss_for_mcs_12_and_13);
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+ wma_nofl_debug("\t EHT MCS 80 tx 12-13 0x%x",
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+ eht_cap->bw_le_80_tx_max_nss_for_mcs_12_and_13);
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+ wma_nofl_debug("\t EHT MCS 160 rx 0-9 0x%x",
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+ eht_cap->bw_160_rx_max_nss_for_mcs_0_to_9);
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+ wma_nofl_debug("\t EHT MCS 160 tx 0-9 0x%x",
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+ eht_cap->bw_160_tx_max_nss_for_mcs_0_to_9);
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+ wma_nofl_debug("\t EHT MCS 160 rx 10-11 0x%x",
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+ eht_cap->bw_160_rx_max_nss_for_mcs_10_and_11);
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+ wma_nofl_debug("\t EHT MCS 160 tx 10-11 0x%x",
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+ eht_cap->bw_160_tx_max_nss_for_mcs_10_and_11);
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+ wma_nofl_debug("\t EHT MCS 160 rx 12-13 0x%x",
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+ eht_cap->bw_160_rx_max_nss_for_mcs_12_and_13);
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+ wma_nofl_debug("\t EHT MCS 160 rx 12-13 0x%x",
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+ eht_cap->bw_160_tx_max_nss_for_mcs_12_and_13);
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+ wma_nofl_debug("\t EHT MCS 320 rx 0-9 0x%x",
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+ eht_cap->bw_320_rx_max_nss_for_mcs_0_to_9);
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+ wma_nofl_debug("\t EHT MCS 320 tx 0-9 0x%x",
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+ eht_cap->bw_320_tx_max_nss_for_mcs_0_to_9);
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+ wma_nofl_debug("\t EHT MCS 320 rx 10-11 0x%x",
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+ eht_cap->bw_320_rx_max_nss_for_mcs_10_and_11);
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+ wma_nofl_debug("\t EHT MCS 320 tx 10-11 0x%x",
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+ eht_cap->bw_320_tx_max_nss_for_mcs_10_and_11);
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+ wma_nofl_debug("\t EHT MCS 320 rx 12-13 0x%x",
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+ eht_cap->bw_320_rx_max_nss_for_mcs_12_and_13);
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+ wma_nofl_debug("\t EHT MCS 320 tx 12-13 0x%x",
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+ eht_cap->bw_320_tx_max_nss_for_mcs_12_and_13);
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}
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void wma_print_eht_phy_cap(uint32_t *phy_cap)
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@@ -448,6 +591,7 @@ void wma_populate_peer_eht_cap(struct peer_assoc_params *peer,
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tDot11fIEeht_cap *eht_cap = ¶ms->eht_config;
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uint32_t *phy_cap = peer->peer_eht_cap_phyinfo;
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uint32_t *mac_cap = peer->peer_eht_cap_macinfo;
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+ struct supported_rates *rates;
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if (!params->eht_capable)
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return;
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@@ -525,12 +669,97 @@ void wma_populate_peer_eht_cap(struct peer_assoc_params *peer,
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WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_SET(phy_cap,
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eht_cap->rx_4k_qam_in_wider_bw_dl_ofdma);
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- qdf_mem_copy(peer->peer_eht_rx_mcs_set, peer->peer_he_rx_mcs_set,
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- sizeof(peer->peer_he_rx_mcs_set));
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- qdf_mem_copy(peer->peer_eht_tx_mcs_set, peer->peer_he_tx_mcs_set,
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- sizeof(peer->peer_he_tx_mcs_set));
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-
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- peer->peer_eht_mcs_count = peer->peer_he_mcs_count;
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+ peer->peer_eht_mcs_count = 0;
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+ rates = ¶ms->supportedRates;
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+
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+ /*
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+ * Convert eht mcs to firmware understandable format
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+ * BITS 0:3 indicates support for mcs 0 to 7
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+ * BITS 4:7 indicates support for mcs 8 and 9
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+ * BITS 8:11 indicates support for mcs 10 and 11
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+ * BITS 12:15 indicates support for mcs 12 and 13
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+ */
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+ switch (params->ch_width) {
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+ case CH_WIDTH_320MHZ:
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+ peer->peer_eht_mcs_count++;
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+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
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+ 0, 4, rates->bw_320_rx_max_nss_for_mcs_0_to_9);
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+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
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+ 0, 4, rates->bw_320_tx_max_nss_for_mcs_0_to_9);
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+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
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+ 4, 4, rates->bw_320_rx_max_nss_for_mcs_0_to_9);
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+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
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+ 4, 4, rates->bw_320_tx_max_nss_for_mcs_0_to_9);
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+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
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+ 8, 4, rates->bw_320_rx_max_nss_for_mcs_10_and_11);
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+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
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+ 8, 4, rates->bw_320_tx_max_nss_for_mcs_10_and_11);
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+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
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+ 12, 4, rates->bw_320_rx_max_nss_for_mcs_12_and_13);
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+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX2],
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+ 12, 4, rates->bw_320_tx_max_nss_for_mcs_12_and_13);
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+ /* fall through */
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+ case CH_WIDTH_160MHZ:
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+ peer->peer_eht_mcs_count++;
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+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
|
|
|
+ 0, 4, rates->bw_160_rx_max_nss_for_mcs_0_to_9);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
|
|
|
+ 0, 4, rates->bw_160_tx_max_nss_for_mcs_0_to_9);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
|
|
|
+ 4, 4, rates->bw_160_rx_max_nss_for_mcs_0_to_9);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
|
|
|
+ 4, 4, rates->bw_160_tx_max_nss_for_mcs_0_to_9);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
|
|
|
+ 8, 4, rates->bw_160_rx_max_nss_for_mcs_10_and_11);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
|
|
|
+ 8, 4, rates->bw_160_rx_max_nss_for_mcs_10_and_11);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
|
|
|
+ 12, 4, rates->bw_160_rx_max_nss_for_mcs_12_and_13);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX1],
|
|
|
+ 12, 4, rates->bw_160_tx_max_nss_for_mcs_12_and_13);
|
|
|
+ /* fall through */
|
|
|
+ case CH_WIDTH_80MHZ:
|
|
|
+ case CH_WIDTH_40MHZ:
|
|
|
+ peer->peer_eht_mcs_count++;
|
|
|
+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 0, 4, rates->bw_le_80_rx_max_nss_for_mcs_0_to_9);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 0, 4, rates->bw_le_80_tx_max_nss_for_mcs_0_to_9);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 4, 4, rates->bw_le_80_rx_max_nss_for_mcs_0_to_9);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 4, 4, rates->bw_le_80_tx_max_nss_for_mcs_0_to_9);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 8, 4, rates->bw_le_80_rx_max_nss_for_mcs_10_and_11);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 8, 4, rates->bw_le_80_tx_max_nss_for_mcs_10_and_11);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 12, 4, rates->bw_le_80_rx_max_nss_for_mcs_12_and_13);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 12, 4, rates->bw_le_80_rx_max_nss_for_mcs_12_and_13);
|
|
|
+ break;
|
|
|
+ case CH_WIDTH_20MHZ:
|
|
|
+ peer->peer_eht_mcs_count++;
|
|
|
+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 0, 4, rates->bw_20_rx_max_nss_for_mcs_0_to_7);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 0, 4, rates->bw_20_tx_max_nss_for_mcs_0_to_7);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 4, 4, rates->bw_20_rx_max_nss_for_mcs_8_and_9);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 4, 4, rates->bw_20_tx_max_nss_for_mcs_8_and_9);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 8, 4, rates->bw_20_rx_max_nss_for_mcs_10_and_11);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 8, 4, rates->bw_20_tx_max_nss_for_mcs_10_and_11);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_rx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 12, 4, rates->bw_20_rx_max_nss_for_mcs_12_and_13);
|
|
|
+ QDF_SET_BITS(peer->peer_eht_tx_mcs_set[EHTCAP_TXRX_MCS_NSS_IDX0],
|
|
|
+ 12, 4, rates->bw_20_tx_max_nss_for_mcs_12_and_13);
|
|
|
+ /* fall through */
|
|
|
+ default:
|
|
|
+ break;
|
|
|
+ }
|
|
|
|
|
|
wma_print_eht_cap(eht_cap);
|
|
|
wma_debug("Peer EHT Capabilities:");
|