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asoc: clean up audio drivers and remove unused files

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Clean up audio drivers and remove unused files.

Change-Id: I50559ac3c5f4a1f4336e4480cd3ff235d015441e
Signed-off-by: Meng Wang <mengw@codeaurora.org>
This commit is contained in:
Meng Wang
2018-11-16 13:06:16 +08:00
parent 53ad8477b6
commit d6107d0bbe
68 changed files with 18 additions and 53146 deletions
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16
Android.mk
View File

@@ -3,7 +3,7 @@ MY_LOCAL_PATH := $(call my-dir)
UAPI_OUT := $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/include UAPI_OUT := $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/include
ifeq ($(call is-board-platform-in-list,msm8953 sdm845 sdm670 qcs605 msmnile $(MSMSTEPPE) $(TRINKET)),true) ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET)),true)
$(shell mkdir -p $(UAPI_OUT)/linux;) $(shell mkdir -p $(UAPI_OUT)/linux;)
$(shell mkdir -p $(UAPI_OUT)/sound;) $(shell mkdir -p $(UAPI_OUT)/sound;)
$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers)
@@ -24,7 +24,7 @@ include $(MY_LOCAL_PATH)/asoc/codecs/Android.mk
include $(MY_LOCAL_PATH)/asoc/codecs/wcd934x/Android.mk include $(MY_LOCAL_PATH)/asoc/codecs/wcd934x/Android.mk
endif endif
ifeq ($(call is-board-platform-in-list,sdm670 msmnile),true) ifeq ($(call is-board-platform-in-list,msmnile),true)
$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/aqt1000/Module.symvers) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/aqt1000/Module.symvers)
include $(MY_LOCAL_PATH)/asoc/codecs/aqt1000/Android.mk include $(MY_LOCAL_PATH)/asoc/codecs/aqt1000/Android.mk
endif endif
@@ -35,15 +35,3 @@ include $(MY_LOCAL_PATH)/asoc/codecs/bolero/Android.mk
$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wcd937x/Module.symvers) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wcd937x/Module.symvers)
include $(MY_LOCAL_PATH)/asoc/codecs/wcd937x/Android.mk include $(MY_LOCAL_PATH)/asoc/codecs/wcd937x/Android.mk
endif endif
ifeq ($(call is-board-platform-in-list,msm8953 sdm670 qcs605),true)
$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/sdm660_cdc/Module.symvers)
$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/msm_sdw/Module.symvers)
include $(MY_LOCAL_PATH)/asoc/codecs/sdm660_cdc/Android.mk
include $(MY_LOCAL_PATH)/asoc/codecs/msm_sdw/Android.mk
endif
ifeq ($(call is-board-platform-in-list,msmnile),true)
$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wcd9360/Module.symvers)
include $(MY_LOCAL_PATH)/asoc/codecs/wcd9360/Android.mk
endif

16
Makefile
View File

@@ -1,12 +1,4 @@
# auto-detect subdirs # auto-detect subdirs
ifeq ($(CONFIG_ARCH_SDM845), y)
include $(srctree)/techpack/audio/config/sdm845auto.conf
export
endif
ifeq ($(CONFIG_ARCH_SDM670), y)
include $(srctree)/techpack/audio/config/sdm670auto_static.conf
export
endif
ifeq ($(CONFIG_ARCH_SDXPOORWILLS), y) ifeq ($(CONFIG_ARCH_SDXPOORWILLS), y)
include $(srctree)/techpack/audio/config/sdxpoorwillsauto.conf include $(srctree)/techpack/audio/config/sdxpoorwillsauto.conf
export export
@@ -30,14 +22,6 @@ LINUXINCLUDE += \
-I$(srctree)/techpack/audio/include/uapi \ -I$(srctree)/techpack/audio/include/uapi \
-I$(srctree)/techpack/audio/include -I$(srctree)/techpack/audio/include
ifeq ($(CONFIG_ARCH_SDM845), y)
LINUXINCLUDE += \
-include $(srctree)/techpack/audio/config/sdm845autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM670), y)
LINUXINCLUDE += \
-include $(srctree)/techpack/audio/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDXPOORWILLS), y) ifeq ($(CONFIG_ARCH_SDXPOORWILLS), y)
LINUXINCLUDE += \ LINUXINCLUDE += \
-include $(srctree)/techpack/audio/config/sdxpoorwillsautoconf.h -include $(srctree)/techpack/audio/config/sdxpoorwillsautoconf.h

17
Makefile.am
View File

@@ -11,15 +11,6 @@ AUDIO_KERNEL_HEADERS_PATH1 = $(shell ls ./include/uapi/linux/*.h)
AUDIO_KERNEL_HEADERS_PATH2 = $(shell ls ./include/uapi/linux/mfd/wcd9xxx/*.h) AUDIO_KERNEL_HEADERS_PATH2 = $(shell ls ./include/uapi/linux/mfd/wcd9xxx/*.h)
AUDIO_KERNEL_HEADERS_PATH3 = $(shell ls ./include/uapi/sound/*.h) AUDIO_KERNEL_HEADERS_PATH3 = $(shell ls ./include/uapi/sound/*.h)
ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sdm670 qcs605))
KBUILD_OPTIONS += CONFIG_ARCH_SDM670=y
endif
ifeq ($(TARGET_SUPPORT),sdm845)
KBUILD_OPTIONS += CONFIG_ARCH_SDM845=y
endif
ifeq ($(TARGET_SUPPORT),apq8053)
KBUILD_OPTIONS += CONFIG_ARCH_SDM450=y
endif
ifeq ($(TARGET_SUPPORT),qcs40x) ifeq ($(TARGET_SUPPORT),qcs40x)
KBUILD_OPTIONS += CONFIG_ARCH_QCS405=y KBUILD_OPTIONS += CONFIG_ARCH_QCS405=y
endif endif
@@ -33,15 +24,9 @@ obj-m += dsp/codecs/
obj-m += soc/ obj-m += soc/
obj-m += asoc/ obj-m += asoc/
obj-m += asoc/codecs/ obj-m += asoc/codecs/
ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sdm670 qcs605 sdmsteppe)) ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sdmsteppe))
obj-m += asoc/codecs/wcd934x/ obj-m += asoc/codecs/wcd934x/
endif endif
ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), apq8053 sdm670 qcs605))
obj-m += asoc/codecs/sdm660_cdc/
endif
ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sdm670 qcs605))
obj-m += asoc/codecs/msm_sdw/
endif
ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), qcs40x)) ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), qcs40x))
obj-m += asoc/codecs/bolero/ obj-m += asoc/codecs/bolero/
obj-m += asoc/codecs/csra66x0/ obj-m += asoc/codecs/csra66x0/

14
asoc/Android.mk
View File

@@ -3,16 +3,6 @@
# Assume no targets will be supported # Assume no targets will be supported
# Check if this driver needs be built for current target # Check if this driver needs be built for current target
ifeq ($(call is-board-platform,sdm845),true)
TARGET := sdm845
AUDIO_SELECT := CONFIG_SND_SOC_SDM845=m
endif
ifeq ($(call is-board-platform-in-list,msm8953 sdm670 qcs605),true)
TARGET := sdm670
AUDIO_SELECT := CONFIG_SND_SOC_SDM670=m
endif
ifeq ($(call is-board-platform,msmnile),true) ifeq ($(call is-board-platform,msmnile),true)
TARGET := msmnile TARGET := msmnile
AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m
@@ -30,7 +20,7 @@ endif
AUDIO_CHIPSET := audio AUDIO_CHIPSET := audio
# Build/Package only in case of supported target # Build/Package only in case of supported target
ifeq ($(call is-board-platform-in-list,msm8953 sdm845 sdm670 qcs605 msmnile $(MSMSTEPPE) $(TRINKET)),true) ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET)),true)
LOCAL_PATH := $(call my-dir) LOCAL_PATH := $(call my-dir)
@@ -65,7 +55,7 @@ LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/AndroidKernelModule.mk include $(DLKM_DIR)/AndroidKernelModule.mk
########################################################### ###########################################################
ifeq ($(call is-board-platform-in-list,msm8953 sdm670 qcs605),true) ifeq ($(call is-board-platform-in-list, ),true)
include $(CLEAR_VARS) include $(CLEAR_VARS)
LOCAL_MODULE := $(AUDIO_CHIPSET)_cpe_lsm.ko LOCAL_MODULE := $(AUDIO_CHIPSET)_cpe_lsm.ko
LOCAL_MODULE_KBUILD_NAME := cpe_lsm_dlkm.ko LOCAL_MODULE_KBUILD_NAME := cpe_lsm_dlkm.ko

48
asoc/Kbuild
View File

@@ -14,21 +14,6 @@ ifeq ($(KERNEL_BUILD), 1)
endif endif
ifeq ($(KERNEL_BUILD), 0) ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SDM845), y)
include $(AUDIO_ROOT)/config/sdm845auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm845autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM670), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM450), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SM8150), y) ifeq ($(CONFIG_ARCH_SM8150), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf include $(AUDIO_ROOT)/config/sm8150auto.conf
export export
@@ -82,28 +67,6 @@ COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
############ ASoC Drivers ############ ############ ASoC Drivers ############
# for SDM6xx sound card driver
ifdef CONFIG_SND_SOC_SDM670
MACHINE_OBJS += sdm660-common.o
endif
# for SDM6xx sound card driver
ifdef CONFIG_SND_SOC_INT_CODEC
MACHINE_OBJS += sdm660-internal.o
endif
# for SDM6xx sound card driver
ifdef CONFIG_SND_SOC_EXT_CODEC
MACHINE_OBJS += sdm660-external.o
MACHINE_OBJS += sdm660-ext-dai-links.o
endif
# for SDM845 sound card driver
ifdef CONFIG_SND_SOC_MACHINE_SDM845
MACHINE_OBJS += sdm845.o
endif
# for SM8150 sound card driver # for SM8150 sound card driver
ifdef CONFIG_SND_SOC_SM8150 ifdef CONFIG_SND_SOC_SM8150
MACHINE_OBJS += sa8155.o MACHINE_OBJS += sa8155.o
@@ -197,8 +160,6 @@ KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wcd934x/Module.symvers KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wcd934x/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wcd937x/Module.symvers KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wcd937x/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/sdm660_cdc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/msm_sdw/Module.symvers
endif endif
ifeq ($(KERNEL_BUILD), 1) ifeq ($(KERNEL_BUILD), 1)
obj-y += codecs/ obj-y += codecs/
@@ -207,9 +168,6 @@ endif
obj-$(CONFIG_SND_SOC_QDSP6V2) += platform_dlkm.o obj-$(CONFIG_SND_SOC_QDSP6V2) += platform_dlkm.o
platform_dlkm-y := $(PLATFORM_OBJS) platform_dlkm-y := $(PLATFORM_OBJS)
obj-$(CONFIG_SND_SOC_MACHINE_SDM845) += machine_dlkm.o
machine_dlkm-y := $(MACHINE_OBJS)
obj-$(CONFIG_SND_SOC_SM8150) += machine_dlkm.o obj-$(CONFIG_SND_SOC_SM8150) += machine_dlkm.o
machine_dlkm-y := $(MACHINE_OBJS) machine_dlkm-y := $(MACHINE_OBJS)
@@ -219,12 +177,6 @@ machine_dlkm-y := $(MACHINE_OBJS)
obj-$(CONFIG_SND_SOC_QCS405) += machine_dlkm.o obj-$(CONFIG_SND_SOC_QCS405) += machine_dlkm.o
machine_dlkm-y := $(MACHINE_OBJS) machine_dlkm-y := $(MACHINE_OBJS)
obj-$(CONFIG_SND_SOC_EXT_CODEC) += machine_dlkm.o
machine_dlkm-y := $(MACHINE_OBJS)
obj-$(CONFIG_SND_SOC_INT_CODEC) += machine_dlkm.o
machine_dlkm-y := $(MACHINE_OBJS)
obj-$(CONFIG_SND_SOC_CPE) += cpe_lsm_dlkm.o obj-$(CONFIG_SND_SOC_CPE) += cpe_lsm_dlkm.o
cpe_lsm_dlkm-y := $(CPE_LSM_OBJS) cpe_lsm_dlkm-y := $(CPE_LSM_OBJS)

14
asoc/codecs/Android.mk
View File

@@ -3,14 +3,6 @@
# Assume no targets will be supported # Assume no targets will be supported
# Check if this driver needs be built for current target # Check if this driver needs be built for current target
ifeq ($(call is-board-platform,sdm845),true)
AUDIO_SELECT := CONFIG_SND_SOC_SDM845=m
endif
ifeq ($(call is-board-platform-in-list,msm8953 sdm670 qcs605),true)
AUDIO_SELECT := CONFIG_SND_SOC_SDM670=m
endif
ifeq ($(call is-board-platform,msmnile),true) ifeq ($(call is-board-platform,msmnile),true)
AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m
endif endif
@@ -25,7 +17,7 @@ endif
AUDIO_CHIPSET := audio AUDIO_CHIPSET := audio
# Build/Package only in case of supported target # Build/Package only in case of supported target
ifeq ($(call is-board-platform-in-list,msm8953 sdm845 sdm670 qcs605 msmnile $(MSMSTEPPE) $(TRINKET)),true) ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET)),true)
LOCAL_PATH := $(call my-dir) LOCAL_PATH := $(call my-dir)
@@ -68,7 +60,7 @@ LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/AndroidKernelModule.mk include $(DLKM_DIR)/AndroidKernelModule.mk
########################################################### ###########################################################
ifeq ($(call is-board-platform-in-list,sdm670 qcs605),true) ifeq ($(call is-board-platform-in-list, ),true)
include $(CLEAR_VARS) include $(CLEAR_VARS)
LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd_cpe.ko LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd_cpe.ko
LOCAL_MODULE_KBUILD_NAME := wcd_cpe_dlkm.ko LOCAL_MODULE_KBUILD_NAME := wcd_cpe_dlkm.ko
@@ -86,7 +78,7 @@ LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/AndroidKernelModule.mk include $(DLKM_DIR)/AndroidKernelModule.mk
########################################################### ###########################################################
ifeq ($(call is-board-platform-in-list,msm8953 sdm670 qcs605),true) ifeq ($(call is-board-platform-in-list, ),true)
include $(CLEAR_VARS) include $(CLEAR_VARS)
LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd9335.ko LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd9335.ko
LOCAL_MODULE_KBUILD_NAME := wcd9335_dlkm.ko LOCAL_MODULE_KBUILD_NAME := wcd9335_dlkm.ko

19
asoc/codecs/Kbuild
View File

@@ -14,21 +14,6 @@ ifeq ($(KERNEL_BUILD), 1)
endif endif
ifeq ($(KERNEL_BUILD), 0) ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SDM845), y)
include $(AUDIO_ROOT)/config/sdm845auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm845autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM670), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM450), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SM8150), y) ifeq ($(CONFIG_ARCH_SM8150), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf include $(AUDIO_ROOT)/config/sm8150auto.conf
export export
@@ -94,7 +79,6 @@ ifdef CONFIG_WCD9XXX_CODEC_CORE
CORE_OBJS += msm-cdc-supply.o CORE_OBJS += msm-cdc-supply.o
CORE_OBJS += wcd934x/wcd934x-regmap.o CORE_OBJS += wcd934x/wcd934x-regmap.o
CORE_OBJS += wcd934x/wcd934x-tables.o CORE_OBJS += wcd934x/wcd934x-tables.o
CORE_OBJS += wcd9360/wcd9360-regmap.o
endif endif
ifdef CONFIG_SND_SOC_WCD9XXX_V2 ifdef CONFIG_SND_SOC_WCD9XXX_V2
@@ -193,9 +177,6 @@ endif
ifeq ($(KERNEL_BUILD), 1) ifeq ($(KERNEL_BUILD), 1)
obj-y += wcd934x/ obj-y += wcd934x/
obj-y += sdm660_cdc/
obj-y += msm_sdw/
obj-y += wcd9360/
obj-y += wcd937x/ obj-y += wcd937x/
endif endif
# Module information used by KBuild framework # Module information used by KBuild framework

4
asoc/codecs/core.h
View File

@@ -105,8 +105,6 @@
#define IS_CODEC_VERSION(wcd, wcdversion) \ #define IS_CODEC_VERSION(wcd, wcdversion) \
((wcd->version == wcdversion) ? true : false) ((wcd->version == wcdversion) ? true : false)
#define PAHU_VERSION_1_0 0
enum { enum {
CDC_V_1_0, CDC_V_1_0,
CDC_V_1_1, CDC_V_1_1,
@@ -119,7 +117,6 @@ enum codec_variant {
WCD9335, WCD9335,
WCD9326, WCD9326,
WCD934X, WCD934X,
WCD9360,
}; };
enum wcd9xxx_slim_slave_addr_type { enum wcd9xxx_slim_slave_addr_type {
@@ -298,7 +295,6 @@ enum wcd9xxx_chipid_major {
TASHA_MAJOR = cpu_to_le16(0x0), TASHA_MAJOR = cpu_to_le16(0x0),
TASHA2P0_MAJOR = cpu_to_le16(0x107), TASHA2P0_MAJOR = cpu_to_le16(0x107),
TAVIL_MAJOR = cpu_to_le16(0x108), TAVIL_MAJOR = cpu_to_le16(0x108),
PAHU_MAJOR = cpu_to_le16(0x109),
}; };
enum codec_power_states { enum codec_power_states {

46
asoc/codecs/msm_sdw/Android.mk
View File

@@ -1,46 +0,0 @@
# Android makefile for audio kernel modules
# Assume no targets will be supported
AUDIO_CHIPSET := audio
# Build/Package only in case of supported target
ifeq ($(call is-board-platform-in-list,msm8953 sdm670 qcs605),true)
AUDIO_SELECT := CONFIG_SND_SOC_SDM670=m
LOCAL_PATH := $(call my-dir)
# This makefile is only for DLKM
ifneq ($(findstring vendor,$(LOCAL_PATH)),)
ifneq ($(findstring opensource,$(LOCAL_PATH)),)
AUDIO_BLD_DIR := $(shell pwd)/vendor/qcom/opensource/audio-kernel
endif # opensource
DLKM_DIR := $(TOP)/device/qcom/common/dlkm
# Build audio.ko as $(AUDIO_CHIPSET)_audio.ko
###########################################################
# This is set once per LOCAL_PATH, not per (kernel) module
KBUILD_OPTIONS := AUDIO_ROOT=$(AUDIO_BLD_DIR)
# We are actually building audio.ko here, as per the
# requirement we are specifying <chipset>_audio.ko as LOCAL_MODULE.
# This means we need to rename the module to <chipset>_audio.ko
# after audio.ko is built.
KBUILD_OPTIONS += MODNAME=msm_sdw_dlkm
KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM)
KBUILD_OPTIONS += $(AUDIO_SELECT)
###########################################################
include $(CLEAR_VARS)
LOCAL_MODULE := $(AUDIO_CHIPSET)_msm_sdw.ko
LOCAL_MODULE_KBUILD_NAME := msm_sdw_dlkm.ko
LOCAL_MODULE_TAGS := optional
LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/AndroidKernelModule.mk
###########################################################
###########################################################
endif # DLKM check
endif # supported target check

115
asoc/codecs/msm_sdw/Kbuild
View File

@@ -1,115 +0,0 @@
# We can build either as part of a standalone Kernel build or as
# an external module. Determine which mechanism is being used
ifeq ($(MODNAME),)
KERNEL_BUILD := 1
else
KERNEL_BUILD := 0
endif
ifeq ($(KERNEL_BUILD), 1)
# These are configurable via Kconfig for kernel-based builds
# Need to explicitly configure for Android-based builds
AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-4.9
AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
endif
ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SDM845), y)
include $(AUDIO_ROOT)/config/sdm845auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm845autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM670), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM450), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
endif
# As per target team, build is done as follows:
# Defconfig : build with default flags
# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
# Perf : Using appropriate msmXXXX-perf_defconfig
#
# Shipment builds (user variants) should not have any debug feature
# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
# there is no other way to identify defconfig builds, QTI internal
# representation of perf builds (identified using the string 'perf'),
# is used to identify if the build is a slub or defconfig one. This
# way no critical debug feature will be enabled for perf and shipment
# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
# config.
############ UAPI ############
UAPI_DIR := uapi
UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
############ COMMON ############
COMMON_DIR := include
COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
############ MSM Soundwire ############
# for MSM Soundwire Codec
ifdef CONFIG_SND_SOC_MSM_SDW
MSM_SDW_OBJS += msm_sdw_cdc.o
MSM_SDW_OBJS += msm_sdw_regmap.o
MSM_SDW_OBJS += msm-sdw-tables.o
MSM_SDW_OBJS += msm_sdw_cdc_utils.o
endif
LINUX_INC += -Iinclude/linux
INCS += $(COMMON_INC) \
$(UAPI_INC)
EXTRA_CFLAGS += $(INCS)
CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
-DANI_LITTLE_BIT_ENDIAN \
-DDOT11F_LITTLE_ENDIAN_HOST \
-DANI_COMPILER_TYPE_GCC \
-DANI_OS_TYPE_ANDROID=6 \
-DPTT_SOCK_SVC_ENABLE \
-Wall\
-Werror\
-D__linux__
KBUILD_CPPFLAGS += $(CDEFINES)
# Currently, for versions of gcc which support it, the kernel Makefile
# is disabling the maybe-uninitialized warning. Re-enable it for the
# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
# will override the kernel settings.
ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
EXTRA_CFLAGS += -Wmaybe-uninitialized
endif
#EXTRA_CFLAGS += -Wmissing-prototypes
ifeq ($(call cc-option-yn, -Wheader-guard),y)
EXTRA_CFLAGS += -Wheader-guard
endif
ifeq ($(KERNEL_BUILD), 0)
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
endif
# Module information used by KBuild framework
obj-$(CONFIG_SND_SOC_MSM_SDW) += msm_sdw_dlkm.o
msm_sdw_dlkm-y := $(MSM_SDW_OBJS)
# inject some build related information
DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

319
asoc/codecs/msm_sdw/msm-sdw-tables.c
View File

@@ -1,319 +0,0 @@
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/types.h>
#include "msm_sdw.h"
const u8 msm_sdw_page_map[MSM_SDW_MAX_REGISTER] = {
[MSM_SDW_TX9_SPKR_PROT_PATH_CTL] = 0xa,
[MSM_SDW_TX9_SPKR_PROT_PATH_CFG0] = 0xa,
[MSM_SDW_TX10_SPKR_PROT_PATH_CTL] = 0xa,
[MSM_SDW_TX10_SPKR_PROT_PATH_CFG0] = 0xa,
[MSM_SDW_TX11_SPKR_PROT_PATH_CTL] = 0xa,
[MSM_SDW_TX11_SPKR_PROT_PATH_CFG0] = 0xa,
[MSM_SDW_TX12_SPKR_PROT_PATH_CTL] = 0xa,
[MSM_SDW_TX12_SPKR_PROT_PATH_CFG0] = 0xa,
[MSM_SDW_COMPANDER7_CTL0] = 0xb,
[MSM_SDW_COMPANDER7_CTL1] = 0xb,
[MSM_SDW_COMPANDER7_CTL2] = 0xb,
[MSM_SDW_COMPANDER7_CTL3] = 0xb,
[MSM_SDW_COMPANDER7_CTL4] = 0xb,
[MSM_SDW_COMPANDER7_CTL5] = 0xb,
[MSM_SDW_COMPANDER7_CTL6] = 0xb,
[MSM_SDW_COMPANDER7_CTL7] = 0xb,
[MSM_SDW_COMPANDER8_CTL0] = 0xb,
[MSM_SDW_COMPANDER8_CTL1] = 0xb,
[MSM_SDW_COMPANDER8_CTL2] = 0xb,
[MSM_SDW_COMPANDER8_CTL3] = 0xb,
[MSM_SDW_COMPANDER8_CTL4] = 0xb,
[MSM_SDW_COMPANDER8_CTL5] = 0xb,
[MSM_SDW_COMPANDER8_CTL6] = 0xb,
[MSM_SDW_COMPANDER8_CTL7] = 0xb,
[MSM_SDW_RX7_RX_PATH_CTL] = 0xb,
[MSM_SDW_RX7_RX_PATH_CFG0] = 0xb,
[MSM_SDW_RX7_RX_PATH_CFG1] = 0xb,
[MSM_SDW_RX7_RX_PATH_CFG2] = 0xb,
[MSM_SDW_RX7_RX_VOL_CTL] = 0xb,
[MSM_SDW_RX7_RX_PATH_MIX_CTL] = 0xb,
[MSM_SDW_RX7_RX_PATH_MIX_CFG] = 0xb,
[MSM_SDW_RX7_RX_VOL_MIX_CTL] = 0xb,
[MSM_SDW_RX7_RX_PATH_SEC0] = 0xb,
[MSM_SDW_RX7_RX_PATH_SEC1] = 0xb,
[MSM_SDW_RX7_RX_PATH_SEC2] = 0xb,
[MSM_SDW_RX7_RX_PATH_SEC3] = 0xb,
[MSM_SDW_RX7_RX_PATH_SEC5] = 0xb,
[MSM_SDW_RX7_RX_PATH_SEC6] = 0xb,
[MSM_SDW_RX7_RX_PATH_SEC7] = 0xb,
[MSM_SDW_RX7_RX_PATH_MIX_SEC0] = 0xb,
[MSM_SDW_RX7_RX_PATH_MIX_SEC1] = 0xb,
[MSM_SDW_RX8_RX_PATH_CTL] = 0xb,
[MSM_SDW_RX8_RX_PATH_CFG0] = 0xb,
[MSM_SDW_RX8_RX_PATH_CFG1] = 0xb,
[MSM_SDW_RX8_RX_PATH_CFG2] = 0xb,
[MSM_SDW_RX8_RX_VOL_CTL] = 0xb,
[MSM_SDW_RX8_RX_PATH_MIX_CTL] = 0xb,
[MSM_SDW_RX8_RX_PATH_MIX_CFG] = 0xb,
[MSM_SDW_RX8_RX_VOL_MIX_CTL] = 0xb,
[MSM_SDW_RX8_RX_PATH_SEC0] = 0xb,
[MSM_SDW_RX8_RX_PATH_SEC1] = 0xb,
[MSM_SDW_RX8_RX_PATH_SEC2] = 0xb,
[MSM_SDW_RX8_RX_PATH_SEC3] = 0xb,
[MSM_SDW_RX8_RX_PATH_SEC5] = 0xb,
[MSM_SDW_RX8_RX_PATH_SEC6] = 0xb,
[MSM_SDW_RX8_RX_PATH_SEC7] = 0xb,
[MSM_SDW_RX8_RX_PATH_MIX_SEC0] = 0xb,
[MSM_SDW_RX8_RX_PATH_MIX_SEC1] = 0xb,
[MSM_SDW_BOOST0_BOOST_PATH_CTL] = 0xc,
[MSM_SDW_BOOST0_BOOST_CTL] = 0xc,
[MSM_SDW_BOOST0_BOOST_CFG1] = 0xc,
[MSM_SDW_BOOST0_BOOST_CFG2] = 0xc,
[MSM_SDW_BOOST1_BOOST_PATH_CTL] = 0xc,
[MSM_SDW_BOOST1_BOOST_CTL] = 0xc,
[MSM_SDW_BOOST1_BOOST_CFG1] = 0xc,
[MSM_SDW_BOOST1_BOOST_CFG2] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_DATA_0] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_DATA_1] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_DATA_2] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_DATA_3] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_0] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_1] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_2] = 0xc,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_3] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_0] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_1] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_2] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_3] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_DATA_0] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_DATA_1] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_DATA_2] = 0xc,
[MSM_SDW_AHB_BRIDGE_RD_DATA_3] = 0xc,
[MSM_SDW_AHB_BRIDGE_ACCESS_CFG] = 0xc,
[MSM_SDW_AHB_BRIDGE_ACCESS_STATUS] = 0xc,
[MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL] = 0xd,
[MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL] = 0xd,
[MSM_SDW_CLK_RST_CTRL_SWR_CONTROL] = 0xd,
[MSM_SDW_TOP_TOP_CFG0] = 0xd,
[MSM_SDW_TOP_TOP_CFG1] = 0xd,
[MSM_SDW_TOP_RX_I2S_CTL] = 0xd,
[MSM_SDW_TOP_TX_I2S_CTL] = 0xd,
[MSM_SDW_TOP_I2S_CLK] = 0xd,
[MSM_SDW_TOP_RX7_PATH_INPUT0_MUX] = 0xd,
[MSM_SDW_TOP_RX7_PATH_INPUT1_MUX] = 0xd,
[MSM_SDW_TOP_RX8_PATH_INPUT0_MUX] = 0xd,
[MSM_SDW_TOP_RX8_PATH_INPUT1_MUX] = 0xd,
[MSM_SDW_TOP_FREQ_MCLK] = 0xd,
[MSM_SDW_TOP_DEBUG_BUS_SEL] = 0xd,
[MSM_SDW_TOP_DEBUG_EN] = 0xd,
[MSM_SDW_TOP_I2S_RESET] = 0xd,
[MSM_SDW_TOP_BLOCKS_RESET] = 0xd,
};
const u8 msm_sdw_reg_readable[MSM_SDW_MAX_REGISTER] = {
[MSM_SDW_PAGE_REGISTER] = 1,
[MSM_SDW_TX9_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX9_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_TX10_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX10_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_TX11_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX11_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_TX12_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX12_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_COMPANDER7_CTL0] = 1,
[MSM_SDW_COMPANDER7_CTL1] = 1,
[MSM_SDW_COMPANDER7_CTL2] = 1,
[MSM_SDW_COMPANDER7_CTL3] = 1,
[MSM_SDW_COMPANDER7_CTL4] = 1,
[MSM_SDW_COMPANDER7_CTL5] = 1,
[MSM_SDW_COMPANDER7_CTL6] = 1,
[MSM_SDW_COMPANDER7_CTL7] = 1,
[MSM_SDW_COMPANDER8_CTL0] = 1,
[MSM_SDW_COMPANDER8_CTL1] = 1,
[MSM_SDW_COMPANDER8_CTL2] = 1,
[MSM_SDW_COMPANDER8_CTL3] = 1,
[MSM_SDW_COMPANDER8_CTL4] = 1,
[MSM_SDW_COMPANDER8_CTL5] = 1,
[MSM_SDW_COMPANDER8_CTL6] = 1,
[MSM_SDW_COMPANDER8_CTL7] = 1,
[MSM_SDW_RX7_RX_PATH_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_CFG0] = 1,
[MSM_SDW_RX7_RX_PATH_CFG1] = 1,
[MSM_SDW_RX7_RX_PATH_CFG2] = 1,
[MSM_SDW_RX7_RX_VOL_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_CFG] = 1,
[MSM_SDW_RX7_RX_VOL_MIX_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_SEC0] = 1,
[MSM_SDW_RX7_RX_PATH_SEC1] = 1,
[MSM_SDW_RX7_RX_PATH_SEC2] = 1,
[MSM_SDW_RX7_RX_PATH_SEC3] = 1,
[MSM_SDW_RX7_RX_PATH_SEC5] = 1,
[MSM_SDW_RX7_RX_PATH_SEC6] = 1,
[MSM_SDW_RX7_RX_PATH_SEC7] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_SEC0] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_SEC1] = 1,
[MSM_SDW_RX8_RX_PATH_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_CFG0] = 1,
[MSM_SDW_RX8_RX_PATH_CFG1] = 1,
[MSM_SDW_RX8_RX_PATH_CFG2] = 1,
[MSM_SDW_RX8_RX_VOL_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_CFG] = 1,
[MSM_SDW_RX8_RX_VOL_MIX_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_SEC0] = 1,
[MSM_SDW_RX8_RX_PATH_SEC1] = 1,
[MSM_SDW_RX8_RX_PATH_SEC2] = 1,
[MSM_SDW_RX8_RX_PATH_SEC3] = 1,
[MSM_SDW_RX8_RX_PATH_SEC5] = 1,
[MSM_SDW_RX8_RX_PATH_SEC6] = 1,
[MSM_SDW_RX8_RX_PATH_SEC7] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_SEC0] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_SEC1] = 1,
[MSM_SDW_BOOST0_BOOST_PATH_CTL] = 1,
[MSM_SDW_BOOST0_BOOST_CTL] = 1,
[MSM_SDW_BOOST0_BOOST_CFG1] = 1,
[MSM_SDW_BOOST0_BOOST_CFG2] = 1,
[MSM_SDW_BOOST1_BOOST_PATH_CTL] = 1,
[MSM_SDW_BOOST1_BOOST_CTL] = 1,
[MSM_SDW_BOOST1_BOOST_CFG1] = 1,
[MSM_SDW_BOOST1_BOOST_CFG2] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_0] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_1] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_2] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_3] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_0] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_1] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_2] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_3] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_0] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_1] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_2] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_3] = 1,
[MSM_SDW_AHB_BRIDGE_RD_DATA_0] = 1,
[MSM_SDW_AHB_BRIDGE_RD_DATA_1] = 1,
[MSM_SDW_AHB_BRIDGE_RD_DATA_2] = 1,
[MSM_SDW_AHB_BRIDGE_RD_DATA_3] = 1,
[MSM_SDW_AHB_BRIDGE_ACCESS_CFG] = 1,
[MSM_SDW_AHB_BRIDGE_ACCESS_STATUS] = 1,
[MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL] = 1,
[MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL] = 1,
[MSM_SDW_CLK_RST_CTRL_SWR_CONTROL] = 1,
[MSM_SDW_TOP_TOP_CFG0] = 1,
[MSM_SDW_TOP_TOP_CFG1] = 1,
[MSM_SDW_TOP_RX_I2S_CTL] = 1,
[MSM_SDW_TOP_TX_I2S_CTL] = 1,
[MSM_SDW_TOP_RX7_PATH_INPUT0_MUX] = 1,
[MSM_SDW_TOP_RX7_PATH_INPUT1_MUX] = 1,
[MSM_SDW_TOP_RX8_PATH_INPUT0_MUX] = 1,
[MSM_SDW_TOP_RX8_PATH_INPUT1_MUX] = 1,
[MSM_SDW_TOP_FREQ_MCLK] = 1,
[MSM_SDW_TOP_DEBUG_BUS_SEL] = 1,
[MSM_SDW_TOP_DEBUG_EN] = 1,
[MSM_SDW_TOP_I2S_RESET] = 1,
[MSM_SDW_TOP_BLOCKS_RESET] = 1,
};
const u8 msm_sdw_reg_writeable[MSM_SDW_MAX_REGISTER] = {
[MSM_SDW_PAGE_REGISTER] = 1,
[MSM_SDW_TX9_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX9_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_TX10_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX10_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_TX11_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX11_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_TX12_SPKR_PROT_PATH_CTL] = 1,
[MSM_SDW_TX12_SPKR_PROT_PATH_CFG0] = 1,
[MSM_SDW_COMPANDER7_CTL0] = 1,
[MSM_SDW_COMPANDER7_CTL1] = 1,
[MSM_SDW_COMPANDER7_CTL2] = 1,
[MSM_SDW_COMPANDER7_CTL3] = 1,
[MSM_SDW_COMPANDER7_CTL4] = 1,
[MSM_SDW_COMPANDER7_CTL5] = 1,
[MSM_SDW_COMPANDER7_CTL7] = 1,
[MSM_SDW_COMPANDER8_CTL0] = 1,
[MSM_SDW_COMPANDER8_CTL1] = 1,
[MSM_SDW_COMPANDER8_CTL2] = 1,
[MSM_SDW_COMPANDER8_CTL3] = 1,
[MSM_SDW_COMPANDER8_CTL4] = 1,
[MSM_SDW_COMPANDER8_CTL5] = 1,
[MSM_SDW_COMPANDER8_CTL7] = 1,
[MSM_SDW_RX7_RX_PATH_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_CFG0] = 1,
[MSM_SDW_RX7_RX_PATH_CFG1] = 1,
[MSM_SDW_RX7_RX_PATH_CFG2] = 1,
[MSM_SDW_RX7_RX_VOL_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_CFG] = 1,
[MSM_SDW_RX7_RX_VOL_MIX_CTL] = 1,
[MSM_SDW_RX7_RX_PATH_SEC0] = 1,
[MSM_SDW_RX7_RX_PATH_SEC1] = 1,
[MSM_SDW_RX7_RX_PATH_SEC2] = 1,
[MSM_SDW_RX7_RX_PATH_SEC3] = 1,
[MSM_SDW_RX7_RX_PATH_SEC5] = 1,
[MSM_SDW_RX7_RX_PATH_SEC6] = 1,
[MSM_SDW_RX7_RX_PATH_SEC7] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_SEC0] = 1,
[MSM_SDW_RX7_RX_PATH_MIX_SEC1] = 1,
[MSM_SDW_RX8_RX_PATH_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_CFG0] = 1,
[MSM_SDW_RX8_RX_PATH_CFG1] = 1,
[MSM_SDW_RX8_RX_PATH_CFG2] = 1,
[MSM_SDW_RX8_RX_VOL_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_CFG] = 1,
[MSM_SDW_RX8_RX_VOL_MIX_CTL] = 1,
[MSM_SDW_RX8_RX_PATH_SEC0] = 1,
[MSM_SDW_RX8_RX_PATH_SEC1] = 1,
[MSM_SDW_RX8_RX_PATH_SEC2] = 1,
[MSM_SDW_RX8_RX_PATH_SEC3] = 1,
[MSM_SDW_RX8_RX_PATH_SEC5] = 1,
[MSM_SDW_RX8_RX_PATH_SEC6] = 1,
[MSM_SDW_RX8_RX_PATH_SEC7] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_SEC0] = 1,
[MSM_SDW_RX8_RX_PATH_MIX_SEC1] = 1,
[MSM_SDW_BOOST0_BOOST_PATH_CTL] = 1,
[MSM_SDW_BOOST0_BOOST_CTL] = 1,
[MSM_SDW_BOOST0_BOOST_CFG1] = 1,
[MSM_SDW_BOOST0_BOOST_CFG2] = 1,
[MSM_SDW_BOOST1_BOOST_PATH_CTL] = 1,
[MSM_SDW_BOOST1_BOOST_CTL] = 1,
[MSM_SDW_BOOST1_BOOST_CFG1] = 1,
[MSM_SDW_BOOST1_BOOST_CFG2] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_0] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_1] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_2] = 1,
[MSM_SDW_AHB_BRIDGE_WR_DATA_3] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_0] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_1] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_2] = 1,
[MSM_SDW_AHB_BRIDGE_WR_ADDR_3] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_0] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_1] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_2] = 1,
[MSM_SDW_AHB_BRIDGE_RD_ADDR_3] = 1,
[MSM_SDW_AHB_BRIDGE_ACCESS_CFG] = 1,
[MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL] = 1,
[MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL] = 1,
[MSM_SDW_CLK_RST_CTRL_SWR_CONTROL] = 1,
[MSM_SDW_TOP_TOP_CFG0] = 1,
[MSM_SDW_TOP_TOP_CFG1] = 1,
[MSM_SDW_TOP_RX_I2S_CTL] = 1,
[MSM_SDW_TOP_TX_I2S_CTL] = 1,
[MSM_SDW_TOP_RX7_PATH_INPUT0_MUX] = 1,
[MSM_SDW_TOP_RX7_PATH_INPUT1_MUX] = 1,
[MSM_SDW_TOP_RX8_PATH_INPUT0_MUX] = 1,
[MSM_SDW_TOP_RX8_PATH_INPUT1_MUX] = 1,
[MSM_SDW_TOP_FREQ_MCLK] = 1,
[MSM_SDW_TOP_DEBUG_BUS_SEL] = 1,
[MSM_SDW_TOP_DEBUG_EN] = 1,
[MSM_SDW_TOP_I2S_RESET] = 1,
[MSM_SDW_TOP_BLOCKS_RESET] = 1,
};

203
asoc/codecs/msm_sdw/msm_sdw.h
View File

@@ -1,203 +0,0 @@
/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MSM_SDW_H
#define MSM_SDW_H
#include <sound/soc.h>
#include <dsp/q6afe-v2.h>
#include "msm_sdw_registers.h"
#define MSM_SDW_MAX_REGISTER 0x400
#define MSM_SDW_CHILD_DEVICES_MAX 1
extern const struct regmap_config msm_sdw_regmap_config;
extern const u8 msm_sdw_page_map[MSM_SDW_MAX_REGISTER];
extern const u8 msm_sdw_reg_readable[MSM_SDW_MAX_REGISTER];
extern const u8 msm_sdw_reg_writeable[MSM_SDW_MAX_REGISTER];
enum {
MSM_SDW_RX4 = 0,
MSM_SDW_RX5,
MSM_SDW_RX_MAX,
};
enum {
MSM_SDW_TX0 = 0,
MSM_SDW_TX1,
MSM_SDW_TX_MAX,
};
enum {
COMP1, /* SPK_L */
COMP2, /* SPK_R */
COMP_MAX
};
/*
* Structure used to update codec
* register defaults after reset
*/
struct msm_sdw_reg_mask_val {
u16 reg;
u8 mask;
u8 val;
};
/*
* Selects compander and smart boost settings
* for a given speaker mode
*/
enum {
SPKR_MODE_DEFAULT,
SPKR_MODE_1, /* COMP Gain = 12dB, Smartboost Max = 5.5V */
};
/* Rx path gain offsets */
enum {
RX_GAIN_OFFSET_M1P5_DB,
RX_GAIN_OFFSET_0_DB,
};
struct msm_sdw_reg_val {
unsigned short reg; /* register address */
u8 *buf; /* buffer to be written to reg. addr */
int bytes; /* number of bytes to be written */
};
/* Hold instance to soundwire platform device */
struct msm_sdw_ctrl_data {
struct platform_device *sdw_pdev;
};
struct wcd_sdw_ctrl_platform_data {
void *handle; /* holds codec private data */
int (*read)(void *handle, int reg);
int (*write)(void *handle, int reg, int val);
int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
int (*clk)(void *handle, bool enable);
int (*handle_irq)(void *handle,
irqreturn_t (*swrm_irq_handler)(int irq,
void *data),
void *swrm_handle,
int action);
};
struct msm_sdw_priv {
struct device *dev;
struct mutex io_lock;
int (*read_dev)(struct msm_sdw_priv *msm_sdw, unsigned short reg,
int bytes, void *dest);
int (*write_dev)(struct msm_sdw_priv *msm_sdw, unsigned short reg,
int bytes, void *src);
int (*multi_reg_write)(struct msm_sdw_priv *msm_sdw, const void *data,
size_t count);
struct snd_soc_codec *codec;
struct device_node *sdw_gpio_p; /* used by pinctrl API */
/* SoundWire data structure */
struct msm_sdw_ctrl_data *sdw_ctrl_data;
int nr;
/* compander */
int comp_enabled[COMP_MAX];
int ear_spkr_gain;
/* to track the status */
unsigned long status_mask;
struct work_struct msm_sdw_add_child_devices_work;
struct wcd_sdw_ctrl_platform_data sdw_plat_data;
unsigned int vi_feed_value;
struct mutex sdw_read_lock;
struct mutex sdw_write_lock;
struct mutex sdw_clk_lock;
int sdw_clk_users;
int sdw_mclk_users;
int sdw_irq;
int int_mclk1_rsc_ref;
bool int_mclk1_enabled;
bool sdw_npl_clk_enabled;
struct mutex cdc_int_mclk1_mutex;
struct mutex sdw_npl_clk_mutex;
struct delayed_work disable_int_mclk1_work;
struct afe_clk_set sdw_cdc_core_clk;
struct afe_clk_set sdw_npl_clk;
struct notifier_block service_nb;
int (*sdw_cdc_gpio_fn)(bool enable, struct snd_soc_codec *codec);
bool dev_up;
int spkr_gain_offset;
int spkr_mode;
struct mutex codec_mutex;
int rx_4_count;
int rx_5_count;
u32 mclk_rate;
struct regmap *regmap;
bool prev_pg_valid;
u8 prev_pg;
u32 sdw_base_addr;
char __iomem *sdw_base;
u32 version;
/* Entry for version info */
struct snd_info_entry *entry;
struct snd_info_entry *version_entry;
struct platform_device *pdev_child_devices
[MSM_SDW_CHILD_DEVICES_MAX];
int child_count;
};
#if IS_ENABLED(CONFIG_SND_SOC_MSM_SDW)
extern int msm_sdw_set_spkr_mode(struct snd_soc_codec *codec, int mode);
extern int msm_sdw_set_spkr_gain_offset(struct snd_soc_codec *codec,
int offset);
extern void msm_sdw_gpio_cb(
int (*sdw_cdc_gpio_fn)(bool enable, struct snd_soc_codec *codec),
struct snd_soc_codec *codec);
extern struct regmap *msm_sdw_regmap_init(struct device *dev,
const struct regmap_config *config);
extern int msm_sdw_codec_info_create_codec_entry(
struct snd_info_entry *codec_root,
struct snd_soc_codec *codec);
#else /* CONFIG_SND_SOC_MSM_SDW */
static inline int msm_sdw_set_spkr_mode(struct snd_soc_codec *codec, int mode)
{
return 0;
}
static inline int msm_sdw_set_spkr_gain_offset(struct snd_soc_codec *codec,
int offset);
{
return 0;
}
static inline void msm_sdw_gpio_cb(
int (*sdw_cdc_gpio_fn)(bool enable, struct snd_soc_codec *codec),
struct snd_soc_codec *codec);
{
}
static inline struct regmap *msm_sdw_regmap_init(struct device *dev,
const struct regmap_config *config);
{
return NULL;
}
static inline int msm_sdw_codec_info_create_codec_entry(
struct snd_info_entry *codec_root,
struct snd_soc_codec *codec)
{
return 0;
}
#endif /* CONFIG_SND_SOC_MSM_SDW */
#endif

2097
asoc/codecs/msm_sdw/msm_sdw_cdc.c
View File

File diff suppressed because it is too large Load Diff

211
asoc/codecs/msm_sdw/msm_sdw_cdc_utils.c
View File

@@ -1,211 +0,0 @@
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/regmap.h>
#include "msm_sdw.h"
#define REG_BYTES 2
#define VAL_BYTES 1
/*
* Page Register Address that APP Proc uses to
* access WCD9335 Codec registers is identified
* as 0x00
*/
#define PAGE_REG_ADDR 0x00
/*
* msm_sdw_page_write:
* Retrieve page number from register and
* write that page number to the page address.
* Called under io_lock acquisition.
*
* @msm_sdw: pointer to msm_sdw
* @reg: Register address from which page number is retrieved
*
* Returns 0 for success and negative error code for failure.
*/
int msm_sdw_page_write(struct msm_sdw_priv *msm_sdw, unsigned short reg)
{
int ret = 0;
u8 pg_num, prev_pg_num;
pg_num = msm_sdw_page_map[reg];
if (msm_sdw->prev_pg_valid) {
prev_pg_num = msm_sdw->prev_pg;
if (prev_pg_num != pg_num) {
ret = msm_sdw->write_dev(msm_sdw, PAGE_REG_ADDR, 1,
(void *) &pg_num);
if (ret < 0) {
dev_err(msm_sdw->dev,
"page write error, pg_num: 0x%x\n",
pg_num);
} else {
msm_sdw->prev_pg = pg_num;
dev_dbg(msm_sdw->dev,
"%s: Page 0x%x Write to 0x00\n",
__func__, pg_num);
}
}
} else {
ret = msm_sdw->write_dev(msm_sdw, PAGE_REG_ADDR, 1,
(void *) &pg_num);
if (ret < 0) {
dev_err(msm_sdw->dev,
"page write error, pg_num: 0x%x\n", pg_num);
} else {
msm_sdw->prev_pg = pg_num;
msm_sdw->prev_pg_valid = true;
dev_dbg(msm_sdw->dev, "%s: Page 0x%x Write to 0x00\n",
__func__, pg_num);
}
}
return ret;
}
EXPORT_SYMBOL(msm_sdw_page_write);
static int regmap_bus_read(void *context, const void *reg, size_t reg_size,
void *val, size_t val_size)
{
struct device *dev = context;
struct msm_sdw_priv *msm_sdw = dev_get_drvdata(dev);
unsigned short c_reg;
int ret, i;
if (!msm_sdw) {
dev_err(dev, "%s: msm_sdw is NULL\n", __func__);
return -EINVAL;
}
if (!reg || !val) {
dev_err(dev, "%s: reg or val is NULL\n", __func__);
return -EINVAL;
}
if (reg_size != REG_BYTES) {
dev_err(dev, "%s: register size %zd bytes, not supported\n",
__func__, reg_size);
return -EINVAL;
}
if (!msm_sdw->dev_up) {
dev_dbg_ratelimited(dev, "%s: No read allowed. dev_up = %d\n",
__func__, msm_sdw->dev_up);
return 0;
}
mutex_lock(&msm_sdw->io_lock);
c_reg = *(u16 *)reg;
ret = msm_sdw_page_write(msm_sdw, c_reg);
if (ret)
goto err;
ret = msm_sdw->read_dev(msm_sdw, c_reg, val_size, val);
if (ret < 0)
dev_err(dev, "%s: Codec read failed (%d), reg: 0x%x, size:%zd\n",
__func__, ret, c_reg, val_size);
else {
for (i = 0; i < val_size; i++)
dev_dbg(dev, "%s: Read 0x%02x from 0x%x\n",
__func__, ((u8 *)val)[i], c_reg + i);
}
err:
mutex_unlock(&msm_sdw->io_lock);
return ret;
}
static int regmap_bus_gather_write(void *context,
const void *reg, size_t reg_size,
const void *val, size_t val_size)
{
struct device *dev = context;
struct msm_sdw_priv *msm_sdw = dev_get_drvdata(dev);
unsigned short c_reg;
int ret, i;
if (!msm_sdw) {
dev_err(dev, "%s: msm_sdw is NULL\n", __func__);
return -EINVAL;
}
if (!reg || !val) {
dev_err(dev, "%s: reg or val is NULL\n", __func__);
return -EINVAL;
}
if (reg_size != REG_BYTES) {
dev_err(dev, "%s: register size %zd bytes, not supported\n",
__func__, reg_size);
return -EINVAL;
}
if (!msm_sdw->dev_up) {
dev_dbg_ratelimited(dev, "%s: No write allowed. dev_up = %d\n",
__func__, msm_sdw->dev_up);
return 0;
}
mutex_lock(&msm_sdw->io_lock);
c_reg = *(u16 *)reg;
ret = msm_sdw_page_write(msm_sdw, c_reg);
if (ret)
goto err;
for (i = 0; i < val_size; i++)
dev_dbg(dev, "Write %02x to 0x%x\n", ((u8 *)val)[i],
c_reg + i*4);
ret = msm_sdw->write_dev(msm_sdw, c_reg, val_size, (void *) val);
if (ret < 0)
dev_err(dev,
"%s: Codec write failed (%d), reg:0x%x, size:%zd\n",
__func__, ret, c_reg, val_size);
err:
mutex_unlock(&msm_sdw->io_lock);
return ret;
}
static int regmap_bus_write(void *context, const void *data, size_t count)
{
struct device *dev = context;
struct msm_sdw_priv *msm_sdw = dev_get_drvdata(dev);
if (!msm_sdw)
return -EINVAL;
WARN_ON(count < REG_BYTES);
return regmap_bus_gather_write(context, data, REG_BYTES,
data + REG_BYTES,
count - REG_BYTES);
}
static struct regmap_bus regmap_bus_config = {
.write = regmap_bus_write,
.gather_write = regmap_bus_gather_write,
.read = regmap_bus_read,
.reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
.val_format_endian_default = REGMAP_ENDIAN_NATIVE,
};
/*
* msm_sdw_regmap_init:
* Initialize msm_sdw register map
*
* @dev: pointer to wcd device
* @config: pointer to register map config
*
* Returns pointer to regmap structure for success
* or NULL in case of failure.
*/
struct regmap *msm_sdw_regmap_init(struct device *dev,
const struct regmap_config *config)
{
return devm_regmap_init(dev, &regmap_bus_config, dev, config);
}
EXPORT_SYMBOL(msm_sdw_regmap_init);

126
asoc/codecs/msm_sdw/msm_sdw_registers.h
View File

@@ -1,126 +0,0 @@
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MSM_SDW_REGISTERS_H
#define MSM_SDW_REGISTERS_H
#define MSM_SDW_PAGE_REGISTER 0x0000
/* Page-A Registers */
#define MSM_SDW_TX9_SPKR_PROT_PATH_CTL 0x0308
#define MSM_SDW_TX9_SPKR_PROT_PATH_CFG0 0x030c
#define MSM_SDW_TX10_SPKR_PROT_PATH_CTL 0x0318
#define MSM_SDW_TX10_SPKR_PROT_PATH_CFG0 0x031c
#define MSM_SDW_TX11_SPKR_PROT_PATH_CTL 0x0328
#define MSM_SDW_TX11_SPKR_PROT_PATH_CFG0 0x032c
#define MSM_SDW_TX12_SPKR_PROT_PATH_CTL 0x0338
#define MSM_SDW_TX12_SPKR_PROT_PATH_CFG0 0x033c
/* Page-B Registers */
#define MSM_SDW_COMPANDER7_CTL0 0x0024
#define MSM_SDW_COMPANDER7_CTL1 0x0028
#define MSM_SDW_COMPANDER7_CTL2 0x002c
#define MSM_SDW_COMPANDER7_CTL3 0x0030
#define MSM_SDW_COMPANDER7_CTL4 0x0034
#define MSM_SDW_COMPANDER7_CTL5 0x0038
#define MSM_SDW_COMPANDER7_CTL6 0x003c
#define MSM_SDW_COMPANDER7_CTL7 0x0040
#define MSM_SDW_COMPANDER8_CTL0 0x0044
#define MSM_SDW_COMPANDER8_CTL1 0x0048
#define MSM_SDW_COMPANDER8_CTL2 0x004c
#define MSM_SDW_COMPANDER8_CTL3 0x0050
#define MSM_SDW_COMPANDER8_CTL4 0x0054
#define MSM_SDW_COMPANDER8_CTL5 0x0058
#define MSM_SDW_COMPANDER8_CTL6 0x005c
#define MSM_SDW_COMPANDER8_CTL7 0x0060
#define MSM_SDW_RX7_RX_PATH_CTL 0x01a4
#define MSM_SDW_RX7_RX_PATH_CFG0 0x01a8
#define MSM_SDW_RX7_RX_PATH_CFG1 0x01ac
#define MSM_SDW_RX7_RX_PATH_CFG2 0x01b0
#define MSM_SDW_RX7_RX_VOL_CTL 0x01b4
#define MSM_SDW_RX7_RX_PATH_MIX_CTL 0x01b8
#define MSM_SDW_RX7_RX_PATH_MIX_CFG 0x01bc
#define MSM_SDW_RX7_RX_VOL_MIX_CTL 0x01c0
#define MSM_SDW_RX7_RX_PATH_SEC0 0x01c4
#define MSM_SDW_RX7_RX_PATH_SEC1 0x01c8
#define MSM_SDW_RX7_RX_PATH_SEC2 0x01cc
#define MSM_SDW_RX7_RX_PATH_SEC3 0x01d0
#define MSM_SDW_RX7_RX_PATH_SEC5 0x01d8
#define MSM_SDW_RX7_RX_PATH_SEC6 0x01dc
#define MSM_SDW_RX7_RX_PATH_SEC7 0x01e0
#define MSM_SDW_RX7_RX_PATH_MIX_SEC0 0x01e4
#define MSM_SDW_RX7_RX_PATH_MIX_SEC1 0x01e8
#define MSM_SDW_RX8_RX_PATH_CTL 0x0384
#define MSM_SDW_RX8_RX_PATH_CFG0 0x0388
#define MSM_SDW_RX8_RX_PATH_CFG1 0x038c
#define MSM_SDW_RX8_RX_PATH_CFG2 0x0390
#define MSM_SDW_RX8_RX_VOL_CTL 0x0394
#define MSM_SDW_RX8_RX_PATH_MIX_CTL 0x0398
#define MSM_SDW_RX8_RX_PATH_MIX_CFG 0x039c
#define MSM_SDW_RX8_RX_VOL_MIX_CTL 0x03a0
#define MSM_SDW_RX8_RX_PATH_SEC0 0x03a4
#define MSM_SDW_RX8_RX_PATH_SEC1 0x03a8
#define MSM_SDW_RX8_RX_PATH_SEC2 0x03ac
#define MSM_SDW_RX8_RX_PATH_SEC3 0x03b0
#define MSM_SDW_RX8_RX_PATH_SEC5 0x03b8
#define MSM_SDW_RX8_RX_PATH_SEC6 0x03bc
#define MSM_SDW_RX8_RX_PATH_SEC7 0x03c0
#define MSM_SDW_RX8_RX_PATH_MIX_SEC0 0x03c4
#define MSM_SDW_RX8_RX_PATH_MIX_SEC1 0x03c8
/* Page-C Registers */
#define MSM_SDW_BOOST0_BOOST_PATH_CTL 0x0064
#define MSM_SDW_BOOST0_BOOST_CTL 0x0068
#define MSM_SDW_BOOST0_BOOST_CFG1 0x006c
#define MSM_SDW_BOOST0_BOOST_CFG2 0x0070
#define MSM_SDW_BOOST1_BOOST_PATH_CTL 0x0084
#define MSM_SDW_BOOST1_BOOST_CTL 0x0088
#define MSM_SDW_BOOST1_BOOST_CFG1 0x008c
#define MSM_SDW_BOOST1_BOOST_CFG2 0x0090
#define MSM_SDW_AHB_BRIDGE_WR_DATA_0 0x00a4
#define MSM_SDW_AHB_BRIDGE_WR_DATA_1 0x00a8
#define MSM_SDW_AHB_BRIDGE_WR_DATA_2 0x00ac
#define MSM_SDW_AHB_BRIDGE_WR_DATA_3 0x00b0
#define MSM_SDW_AHB_BRIDGE_WR_ADDR_0 0x00b4
#define MSM_SDW_AHB_BRIDGE_WR_ADDR_1 0x00b8
#define MSM_SDW_AHB_BRIDGE_WR_ADDR_2 0x00bc
#define MSM_SDW_AHB_BRIDGE_WR_ADDR_3 0x00c0
#define MSM_SDW_AHB_BRIDGE_RD_ADDR_0 0x00c4
#define MSM_SDW_AHB_BRIDGE_RD_ADDR_1 0x00c8
#define MSM_SDW_AHB_BRIDGE_RD_ADDR_2 0x00cc
#define MSM_SDW_AHB_BRIDGE_RD_ADDR_3 0x00d0
#define MSM_SDW_AHB_BRIDGE_RD_DATA_0 0x00d4
#define MSM_SDW_AHB_BRIDGE_RD_DATA_1 0x00d8
#define MSM_SDW_AHB_BRIDGE_RD_DATA_2 0x00dc
#define MSM_SDW_AHB_BRIDGE_RD_DATA_3 0x00e0
#define MSM_SDW_AHB_BRIDGE_ACCESS_CFG 0x00e4
#define MSM_SDW_AHB_BRIDGE_ACCESS_STATUS 0x00e8
/* Page-D Registers */
#define MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL 0x0104
#define MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL 0x0108
#define MSM_SDW_CLK_RST_CTRL_SWR_CONTROL 0x010c
#define MSM_SDW_TOP_TOP_CFG0 0x0204
#define MSM_SDW_TOP_TOP_CFG1 0x0208
#define MSM_SDW_TOP_RX_I2S_CTL 0x020c
#define MSM_SDW_TOP_TX_I2S_CTL 0x0210
#define MSM_SDW_TOP_I2S_CLK 0x0214
#define MSM_SDW_TOP_RX7_PATH_INPUT0_MUX 0x0218
#define MSM_SDW_TOP_RX7_PATH_INPUT1_MUX 0x021c
#define MSM_SDW_TOP_RX8_PATH_INPUT0_MUX 0x0220
#define MSM_SDW_TOP_RX8_PATH_INPUT1_MUX 0x0224
#define MSM_SDW_TOP_FREQ_MCLK 0x0228
#define MSM_SDW_TOP_DEBUG_BUS_SEL 0x022c
#define MSM_SDW_TOP_DEBUG_EN 0x0230
#define MSM_SDW_TOP_I2S_RESET 0x0234
#define MSM_SDW_TOP_BLOCKS_RESET 0x0238
#endif

161
asoc/codecs/msm_sdw/msm_sdw_regmap.c
View File

@@ -1,161 +0,0 @@
/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/regmap.h>
#include "msm_sdw.h"
static const struct reg_default msm_sdw_defaults[] = {
/* Page #10 registers */
{ MSM_SDW_PAGE_REGISTER, 0x00 },
{ MSM_SDW_TX9_SPKR_PROT_PATH_CTL, 0x02 },
{ MSM_SDW_TX9_SPKR_PROT_PATH_CFG0, 0x00 },
{ MSM_SDW_TX10_SPKR_PROT_PATH_CTL, 0x02 },
{ MSM_SDW_TX10_SPKR_PROT_PATH_CFG0, 0x00 },
{ MSM_SDW_TX11_SPKR_PROT_PATH_CTL, 0x02 },
{ MSM_SDW_TX11_SPKR_PROT_PATH_CFG0, 0x00 },
{ MSM_SDW_TX12_SPKR_PROT_PATH_CTL, 0x02 },
{ MSM_SDW_TX12_SPKR_PROT_PATH_CFG0, 0x00 },
/* Page #11 registers */
{ MSM_SDW_COMPANDER7_CTL0, 0x60 },
{ MSM_SDW_COMPANDER7_CTL1, 0xdb },
{ MSM_SDW_COMPANDER7_CTL2, 0xff },
{ MSM_SDW_COMPANDER7_CTL3, 0x35 },
{ MSM_SDW_COMPANDER7_CTL4, 0xff },
{ MSM_SDW_COMPANDER7_CTL5, 0x00 },
{ MSM_SDW_COMPANDER7_CTL6, 0x01 },
{ MSM_SDW_COMPANDER8_CTL0, 0x60 },
{ MSM_SDW_COMPANDER8_CTL1, 0xdb },
{ MSM_SDW_COMPANDER8_CTL2, 0xff },
{ MSM_SDW_COMPANDER8_CTL3, 0x35 },
{ MSM_SDW_COMPANDER8_CTL4, 0xff },
{ MSM_SDW_COMPANDER8_CTL5, 0x00 },
{ MSM_SDW_COMPANDER8_CTL6, 0x01 },
{ MSM_SDW_RX7_RX_PATH_CTL, 0x04 },
{ MSM_SDW_RX7_RX_PATH_CFG0, 0x00 },
{ MSM_SDW_RX7_RX_PATH_CFG2, 0x8f },
{ MSM_SDW_RX7_RX_VOL_CTL, 0x00 },
{ MSM_SDW_RX7_RX_PATH_MIX_CTL, 0x04 },
{ MSM_SDW_RX7_RX_VOL_MIX_CTL, 0x00 },
{ MSM_SDW_RX7_RX_PATH_SEC2, 0x00 },
{ MSM_SDW_RX7_RX_PATH_SEC3, 0x00 },
{ MSM_SDW_RX7_RX_PATH_SEC5, 0x00 },
{ MSM_SDW_RX7_RX_PATH_SEC6, 0x00 },
{ MSM_SDW_RX7_RX_PATH_SEC7, 0x00 },
{ MSM_SDW_RX7_RX_PATH_MIX_SEC1, 0x00 },
{ MSM_SDW_RX8_RX_PATH_CTL, 0x04 },
{ MSM_SDW_RX8_RX_PATH_CFG0, 0x00 },
{ MSM_SDW_RX8_RX_PATH_CFG2, 0x8f },
{ MSM_SDW_RX8_RX_VOL_CTL, 0x00 },
{ MSM_SDW_RX8_RX_PATH_MIX_CTL, 0x04 },
{ MSM_SDW_RX8_RX_VOL_MIX_CTL, 0x00 },
{ MSM_SDW_RX8_RX_PATH_SEC2, 0x00 },
{ MSM_SDW_RX8_RX_PATH_SEC3, 0x00 },
{ MSM_SDW_RX8_RX_PATH_SEC5, 0x00 },
{ MSM_SDW_RX8_RX_PATH_SEC6, 0x00 },
{ MSM_SDW_RX8_RX_PATH_SEC7, 0x00 },
{ MSM_SDW_RX8_RX_PATH_MIX_SEC1, 0x00 },
/* Page #12 registers */
{ MSM_SDW_BOOST0_BOOST_PATH_CTL, 0x00 },
{ MSM_SDW_BOOST0_BOOST_CTL, 0xb2 },
{ MSM_SDW_BOOST0_BOOST_CFG1, 0x00 },
{ MSM_SDW_BOOST0_BOOST_CFG2, 0x00 },
{ MSM_SDW_BOOST1_BOOST_PATH_CTL, 0x00 },
{ MSM_SDW_BOOST1_BOOST_CTL, 0xb2 },
{ MSM_SDW_BOOST1_BOOST_CFG1, 0x00 },
{ MSM_SDW_BOOST1_BOOST_CFG2, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_DATA_0, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_DATA_1, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_DATA_2, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_DATA_3, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_ADDR_0, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_ADDR_1, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_ADDR_2, 0x00 },
{ MSM_SDW_AHB_BRIDGE_WR_ADDR_3, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_ADDR_0, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_ADDR_1, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_ADDR_2, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_ADDR_3, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_DATA_0, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_DATA_1, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_DATA_2, 0x00 },
{ MSM_SDW_AHB_BRIDGE_RD_DATA_3, 0x00 },
{ MSM_SDW_AHB_BRIDGE_ACCESS_CFG, 0x0f },
{ MSM_SDW_AHB_BRIDGE_ACCESS_STATUS, 0x03 },
/* Page #13 registers */
{ MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
{ MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
{ MSM_SDW_CLK_RST_CTRL_SWR_CONTROL, 0x00 },
{ MSM_SDW_TOP_TOP_CFG0, 0x00 },
{ MSM_SDW_TOP_TOP_CFG1, 0x00 },
{ MSM_SDW_TOP_RX_I2S_CTL, 0x0C },
{ MSM_SDW_TOP_TX_I2S_CTL, 0x00 },
{ MSM_SDW_TOP_I2S_CLK, 0x00 },
{ MSM_SDW_TOP_RX7_PATH_INPUT0_MUX, 0x00 },
{ MSM_SDW_TOP_RX7_PATH_INPUT1_MUX, 0x00 },
{ MSM_SDW_TOP_RX8_PATH_INPUT0_MUX, 0x00 },
{ MSM_SDW_TOP_RX8_PATH_INPUT1_MUX, 0x00 },
{ MSM_SDW_TOP_FREQ_MCLK, 0x00 },
{ MSM_SDW_TOP_DEBUG_BUS_SEL, 0x00 },
{ MSM_SDW_TOP_DEBUG_EN, 0x00 },
{ MSM_SDW_TOP_I2S_RESET, 0x00 },
{ MSM_SDW_TOP_BLOCKS_RESET, 0x00 },
};
static bool msm_sdw_is_readable_register(struct device *dev, unsigned int reg)
{
return msm_sdw_reg_readable[reg];
}
static bool msm_sdw_is_writeable_register(struct device *dev, unsigned int reg)
{
return msm_sdw_reg_writeable[reg];
}
static bool msm_sdw_is_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MSM_SDW_AHB_BRIDGE_WR_DATA_0:
case MSM_SDW_AHB_BRIDGE_WR_DATA_1:
case MSM_SDW_AHB_BRIDGE_WR_DATA_2:
case MSM_SDW_AHB_BRIDGE_WR_DATA_3:
case MSM_SDW_AHB_BRIDGE_WR_ADDR_0:
case MSM_SDW_AHB_BRIDGE_WR_ADDR_1:
case MSM_SDW_AHB_BRIDGE_WR_ADDR_2:
case MSM_SDW_AHB_BRIDGE_WR_ADDR_3:
case MSM_SDW_AHB_BRIDGE_RD_DATA_0:
case MSM_SDW_AHB_BRIDGE_RD_DATA_1:
case MSM_SDW_AHB_BRIDGE_RD_DATA_2:
case MSM_SDW_AHB_BRIDGE_RD_DATA_3:
case MSM_SDW_AHB_BRIDGE_RD_ADDR_0:
case MSM_SDW_AHB_BRIDGE_RD_ADDR_1:
case MSM_SDW_AHB_BRIDGE_RD_ADDR_2:
case MSM_SDW_AHB_BRIDGE_RD_ADDR_3:
case MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL:
case MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL:
return true;
default:
return false;
}
}
const struct regmap_config msm_sdw_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.reg_stride = 4,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = msm_sdw_defaults,
.num_reg_defaults = ARRAY_SIZE(msm_sdw_defaults),
.max_register = MSM_SDW_MAX_REGISTER,
.writeable_reg = msm_sdw_is_writeable_register,
.volatile_reg = msm_sdw_is_volatile_register,
.readable_reg = msm_sdw_is_readable_register,
};

53
asoc/codecs/sdm660_cdc/Android.mk
View File

@@ -1,53 +0,0 @@
# Android makefile for audio kernel modules
# Assume no targets will be supported
AUDIO_CHIPSET := audio
# Build/Package only in case of supported target
ifeq ($(call is-board-platform-in-list,msm8953 sdm670 qcs605),true)
LOCAL_PATH := $(call my-dir)
# This makefile is only for DLKM
ifneq ($(findstring vendor,$(LOCAL_PATH)),)
ifneq ($(findstring opensource,$(LOCAL_PATH)),)
AUDIO_BLD_DIR := $(shell pwd)/vendor/qcom/opensource/audio-kernel
endif # opensource
DLKM_DIR := $(TOP)/device/qcom/common/dlkm
# Build audio.ko as $(AUDIO_CHIPSET)_audio.ko
###########################################################
# This is set once per LOCAL_PATH, not per (kernel) module
KBUILD_OPTIONS := AUDIO_ROOT=$(AUDIO_BLD_DIR)
# We are actually building audio.ko here, as per the
# requirement we are specifying <chipset>_audio.ko as LOCAL_MODULE.
# This means we need to rename the module to <chipset>_audio.ko
# after audio.ko is built.
KBUILD_OPTIONS += MODNAME=analog_cdc_dlkm
KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM)
KBUILD_OPTIONS += $(AUDIO_SELECT)
###########################################################
include $(CLEAR_VARS)
LOCAL_MODULE := $(AUDIO_CHIPSET)_analog_cdc.ko
LOCAL_MODULE_KBUILD_NAME := analog_cdc_dlkm.ko
LOCAL_MODULE_TAGS := optional
LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/AndroidKernelModule.mk
###########################################################
include $(CLEAR_VARS)
LOCAL_MODULE := $(AUDIO_CHIPSET)_digital_cdc.ko
LOCAL_MODULE_KBUILD_NAME := digital_cdc_dlkm.ko
LOCAL_MODULE_TAGS := optional
LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/AndroidKernelModule.mk
###########################################################
###########################################################
endif # DLKM check
endif # supported target check

121
asoc/codecs/sdm660_cdc/Kbuild
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@@ -1,121 +0,0 @@
# We can build either as part of a standalone Kernel build or as
# an external module. Determine which mechanism is being used
ifeq ($(MODNAME),)
KERNEL_BUILD := 1
else
KERNEL_BUILD := 0
endif
ifeq ($(KERNEL_BUILD), 1)
# These are configurable via Kconfig for kernel-based builds
# Need to explicitly configure for Android-based builds
AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-4.9
AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
endif
ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SDM845), y)
include $(AUDIO_ROOT)/config/sdm845auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm845autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM670), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM450), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
endif
# As per target team, build is done as follows:
# Defconfig : build with default flags
# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
# Perf : Using appropriate msmXXXX-perf_defconfig
#
# Shipment builds (user variants) should not have any debug feature
# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
# there is no other way to identify defconfig builds, QTI internal
# representation of perf builds (identified using the string 'perf'),
# is used to identify if the build is a slub or defconfig one. This
# way no critical debug feature will be enabled for perf and shipment
# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
# config.
############ UAPI ############
UAPI_DIR := uapi
UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
############ COMMON ############
COMMON_DIR := include
COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
############ SDM660_CDC ############
# for SDM660_CDC Codec
ifdef CONFIG_SND_SOC_ANALOG_CDC
ANALOG_CDC_OBJS += msm-analog-cdc.o
ANALOG_CDC_OBJS += sdm660-cdc-irq.o
endif
ifdef CONFIG_SND_SOC_DIGITAL_CDC
DIGITAL_CDC_OBJS += msm-digital-cdc.o
DIGITAL_CDC_OBJS += msm-digital-cdc-regmap.o
endif
LINUX_INC += -Iinclude/linux
INCS += $(COMMON_INC) \
$(UAPI_INC)
EXTRA_CFLAGS += $(INCS)
CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
-DANI_LITTLE_BIT_ENDIAN \
-DDOT11F_LITTLE_ENDIAN_HOST \
-DANI_COMPILER_TYPE_GCC \
-DANI_OS_TYPE_ANDROID=6 \
-DPTT_SOCK_SVC_ENABLE \
-Wall\
-Werror\
-D__linux__
KBUILD_CPPFLAGS += $(CDEFINES)
# Currently, for versions of gcc which support it, the kernel Makefile
# is disabling the maybe-uninitialized warning. Re-enable it for the
# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
# will override the kernel settings.
ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
EXTRA_CFLAGS += -Wmaybe-uninitialized
endif
#EXTRA_CFLAGS += -Wmissing-prototypes
ifeq ($(call cc-option-yn, -Wheader-guard),y)
EXTRA_CFLAGS += -Wheader-guard
endif
ifeq ($(KERNEL_BUILD), 0)
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
endif
# Module information used by KBuild framework
obj-$(CONFIG_SND_SOC_ANALOG_CDC) += analog_cdc_dlkm.o
analog_cdc_dlkm-y := $(ANALOG_CDC_OBJS)
obj-$(CONFIG_SND_SOC_DIGITAL_CDC) += digital_cdc_dlkm.o
digital_cdc_dlkm-y := $(DIGITAL_CDC_OBJS)
# inject some build related information
DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

186
asoc/codecs/sdm660_cdc/msm-analog-cdc-regmap.h
View File

@@ -1,186 +0,0 @@
/*
* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef ANALOG_CDC_REGMAP_H
#define ANALOG_CDC_REGMAP_H
#include <linux/regmap.h>
#include "sdm660-cdc-registers.h"
/*
* Default register reset values that are common across different versions
* are defined here. If a register reset value is changed based on version
* then remove it from this structure and add it in version specific
* structures.
*/
struct reg_default
msm89xx_pmic_cdc_defaults[MSM89XX_PMIC_CDC_CACHE_SIZE] = {
{MSM89XX_PMIC_DIGITAL_REVISION1, 0x00},
{MSM89XX_PMIC_DIGITAL_REVISION2, 0x00},
{MSM89XX_PMIC_DIGITAL_PERPH_TYPE, 0x23},
{MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE, 0x01},
{MSM89XX_PMIC_DIGITAL_INT_RT_STS, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_SET_TYPE, 0xFF},
{MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH, 0xFF},
{MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_EN_SET, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_EN_CLR, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_PENDING_STS, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_MID_SEL, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_PRIORITY, 0x00},
{MSM89XX_PMIC_DIGITAL_GPIO_MODE, 0x00},
{MSM89XX_PMIC_DIGITAL_PIN_CTL_OE, 0x01},
{MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA, 0x00},
{MSM89XX_PMIC_DIGITAL_PIN_STATUS, 0x00},
{MSM89XX_PMIC_DIGITAL_HDRIVE_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL, 0x02},
{MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL, 0x02},
{MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1, 0x7C},
{MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2, 0x7C},
{MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3, 0x7C},
{MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0, 0x00},
{MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1, 0x00},
{MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2, 0x00},
{MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3, 0x00},
{MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN, 0x00},
{MSM89XX_PMIC_DIGITAL_SPARE_0, 0x00},
{MSM89XX_PMIC_DIGITAL_SPARE_1, 0x00},
{MSM89XX_PMIC_DIGITAL_SPARE_2, 0x00},
{MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0x00},
{MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1, 0x00},
{MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2, 0x02},
{MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x05},
{MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_TEST1, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_TEST_VAL, 0x00},
{MSM89XX_PMIC_DIGITAL_TRIM_NUM, 0x00},
{MSM89XX_PMIC_DIGITAL_TRIM_CTRL, 0x00},
{MSM89XX_PMIC_ANALOG_REVISION1, 0x00},
{MSM89XX_PMIC_ANALOG_REVISION2, 0x00},
{MSM89XX_PMIC_ANALOG_REVISION3, 0x00},
{MSM89XX_PMIC_ANALOG_REVISION4, 0x00},
{MSM89XX_PMIC_ANALOG_PERPH_TYPE, 0x23},
{MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE, 0x09},
{MSM89XX_PMIC_ANALOG_INT_RT_STS, 0x00},
{MSM89XX_PMIC_ANALOG_INT_SET_TYPE, 0x3F},
{MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH, 0x3F},
{MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW, 0x00},
{MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR, 0x00},
{MSM89XX_PMIC_ANALOG_INT_EN_SET, 0x00},
{MSM89XX_PMIC_ANALOG_INT_EN_CLR, 0x00},
{MSM89XX_PMIC_ANALOG_INT_LATCHED_STS, 0x00},
{MSM89XX_PMIC_ANALOG_INT_PENDING_STS, 0x00},
{MSM89XX_PMIC_ANALOG_INT_MID_SEL, 0x00},
{MSM89XX_PMIC_ANALOG_INT_PRIORITY, 0x00},
{MSM89XX_PMIC_ANALOG_MICB_1_EN, 0x00},
{MSM89XX_PMIC_ANALOG_MICB_1_VAL, 0x20},
{MSM89XX_PMIC_ANALOG_MICB_1_CTL, 0x00},
{MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS, 0x49},
{MSM89XX_PMIC_ANALOG_MICB_2_EN, 0x20},
{MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2, 0x00},
{MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x00},
{MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x35},
{MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x08},
{MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, 0x00},
{MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, 0x98},
{MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, 0x00},
{MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL, 0x20},
{MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL, 0x40},
{MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL, 0x61},
{MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL, 0x80},
{MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT, 0x00},
{MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x00},
{MSM89XX_PMIC_ANALOG_TX_1_EN, 0x03},
{MSM89XX_PMIC_ANALOG_TX_2_EN, 0x03},
{MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1, 0xBF},
{MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2, 0x8C},
{MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL, 0x00},
{MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x6B},
{MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV, 0x51},
{MSM89XX_PMIC_ANALOG_TX_3_EN, 0x02},
{MSM89XX_PMIC_ANALOG_NCP_EN, 0x26},
{MSM89XX_PMIC_ANALOG_NCP_CLK, 0x23},
{MSM89XX_PMIC_ANALOG_NCP_DEGLITCH, 0x5B},
{MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0x08},
{MSM89XX_PMIC_ANALOG_NCP_BIAS, 0x29},
{MSM89XX_PMIC_ANALOG_NCP_VCTRL, 0x24},
{MSM89XX_PMIC_ANALOG_NCP_TEST, 0x00},
{MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR, 0xD5},
{MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER, 0xE8},
{MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL, 0xCF},
{MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT, 0x6E},
{MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x18},
{MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA, 0x5A},
{MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP, 0x69},
{MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP, 0x29},
{MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x80},
{MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL, 0xDA},
{MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0x16},
{MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x00},
{MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x20},
{MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x00},
{MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x20},
{MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x12},
{MSM89XX_PMIC_ANALOG_RX_ATEST, 0x00},
{MSM89XX_PMIC_ANALOG_RX_HPH_STATUS, 0x0C},
{MSM89XX_PMIC_ANALOG_RX_EAR_STATUS, 0x00},
{MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x00},
{MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x00},
{MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x83},
{MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET, 0x91},
{MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x29},
{MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET, 0x4D},
{MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1},
{MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x1E},
{MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC, 0xCB},
{MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x00},
{MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x02},
{MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE, 0x14},
{MSM89XX_PMIC_ANALOG_BYPASS_MODE, 0x00},
{MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, 0x1F},
{MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO, 0x8C},
{MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE, 0xC0},
{MSM89XX_PMIC_ANALOG_BOOST_TEST1_1, 0x00},
{MSM89XX_PMIC_ANALOG_BOOST_TEST_2, 0x00},
{MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS, 0x00},
{MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS, 0x00},
{MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR, 0x00},
{MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL, 0x00},
{MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0x00},
{MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1, 0x00},
{MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2, 0x01},
{MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x05},
{MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4, 0x00},
{MSM89XX_PMIC_ANALOG_INT_TEST1, 0x00},
{MSM89XX_PMIC_ANALOG_INT_TEST_VAL, 0x00},
{MSM89XX_PMIC_ANALOG_TRIM_NUM, 0x04},
{MSM89XX_PMIC_ANALOG_TRIM_CTRL1, 0x00},
{MSM89XX_PMIC_ANALOG_TRIM_CTRL2, 0x00},
{MSM89XX_PMIC_ANALOG_TRIM_CTRL3, 0x00},
{MSM89XX_PMIC_ANALOG_TRIM_CTRL4, 0x00},
};
#endif

4665
asoc/codecs/sdm660_cdc/msm-analog-cdc.c
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File diff suppressed because it is too large Load Diff

273
asoc/codecs/sdm660_cdc/msm-analog-cdc.h
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@@ -1,273 +0,0 @@
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MSM_ANALOG_CDC_H
#define MSM_ANALOG_CDC_H
#include <sound/soc.h>
#include <sound/jack.h>
#include <dsp/q6afe-v2.h>
#include "../wcd-mbhc-v2.h"
#include "../wcdcal-hwdep.h"
#include "sdm660-cdc-registers.h"
#define MICBIAS_EXT_BYP_CAP 0x00
#define MICBIAS_NO_EXT_BYP_CAP 0x01
#define ANLG_CDC_CHILD_DEVICES_MAX 1
#define MSM89XX_NUM_IRQ_REGS 2
#define MAX_REGULATOR 7
#define MSM89XX_REG_VAL(reg, val) {reg, 0, val}
#define MSM89XX_VDD_SPKDRV_NAME "cdc-vdd-spkdrv"
#define DEFAULT_MULTIPLIER 800
#define DEFAULT_GAIN 9
#define DEFAULT_OFFSET 100
extern const u8 msm89xx_pmic_cdc_reg_readable[MSM89XX_PMIC_CDC_CACHE_SIZE];
extern const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE];
extern struct regmap_config msm89xx_cdc_core_regmap_config;
extern struct regmap_config msm89xx_pmic_cdc_regmap_config;
enum wcd_curr_ref {
I_h4_UA = 0,
I_pt5_UA,
I_14_UA,
I_l4_UA,
I_1_UA,
};
enum wcd_mbhc_imp_det_pin {
WCD_MBHC_DET_NONE = 0,
WCD_MBHC_DET_HPHL,
WCD_MBHC_DET_HPHR,
WCD_MBHC_DET_BOTH,
};
/* Each micbias can be assigned to one of three cfilters
* Vbatt_min >= .15V + ldoh_v
* ldoh_v >= .15v + cfiltx_mv
* If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv
* If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv
* If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv
* If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv
*/
struct wcd_micbias_setting {
u8 ldoh_v;
u32 cfilt1_mv; /* in mv */
u32 cfilt2_mv; /* in mv */
u32 cfilt3_mv; /* in mv */
/* Different WCD9xxx series codecs may not
* have 4 mic biases. If a codec has fewer
* mic biases, some of these properties will
* not be used.
*/
u8 bias1_cfilt_sel;
u8 bias2_cfilt_sel;
u8 bias3_cfilt_sel;
u8 bias4_cfilt_sel;
u8 bias1_cap_mode;
u8 bias2_cap_mode;
u8 bias3_cap_mode;
u8 bias4_cap_mode;
bool bias2_is_headset_only;
};
enum sdm660_cdc_pid_current {
MSM89XX_PID_MIC_2P5_UA,
MSM89XX_PID_MIC_5_UA,
MSM89XX_PID_MIC_10_UA,
MSM89XX_PID_MIC_20_UA,
};
struct sdm660_cdc_reg_mask_val {
u16 reg;
u8 mask;
u8 val;
};
enum {
/* INTR_REG 0 - Digital Periph */
MSM89XX_IRQ_SPKR_CNP = 0,
MSM89XX_IRQ_SPKR_CLIP,
MSM89XX_IRQ_SPKR_OCP,
MSM89XX_IRQ_MBHC_INSREM_DET1,
MSM89XX_IRQ_MBHC_RELEASE,
MSM89XX_IRQ_MBHC_PRESS,
MSM89XX_IRQ_MBHC_INSREM_DET,
MSM89XX_IRQ_MBHC_HS_DET,
/* INTR_REG 1 - Analog Periph */
MSM89XX_IRQ_EAR_OCP,
MSM89XX_IRQ_HPHR_OCP,
MSM89XX_IRQ_HPHL_OCP,
MSM89XX_IRQ_EAR_CNP,
MSM89XX_IRQ_HPHR_CNP,
MSM89XX_IRQ_HPHL_CNP,
MSM89XX_NUM_IRQS,
};
enum {
ON_DEMAND_MICBIAS = 0,
ON_DEMAND_SPKDRV,
ON_DEMAND_SUPPLIES_MAX,
};
/*
* The delay list is per codec HW specification.
* Please add delay in the list in the future instead
* of magic number
*/
enum {
CODEC_DELAY_1_MS = 1000,
CODEC_DELAY_1_1_MS = 1100,
};
struct sdm660_cdc_regulator {
const char *name;
int min_uv;
int max_uv;
int optimum_ua;
bool ondemand;
struct regulator *regulator;
};
struct on_demand_supply {
struct regulator *supply;
atomic_t ref;
int min_uv;
int max_uv;
int optimum_ua;
};
struct wcd_imped_i_ref {
enum wcd_curr_ref curr_ref;
int min_val;
int multiplier;
int gain_adj;
int offset;
};
enum sdm660_cdc_micbias_num {
MSM89XX_MICBIAS1 = 0,
};
/* Hold instance to digital codec platform device */
struct msm_dig_ctrl_data {
struct platform_device *dig_pdev;
};
struct msm_dig_ctrl_platform_data {
void *handle;
void (*set_compander_mode)(void *handle, int val);
void (*update_clkdiv)(void *handle, int val);
int (*get_cdc_version)(void *handle);
int (*register_notifier)(void *handle,
struct notifier_block *nblock,
bool enable);
};
struct sdm660_cdc_priv {
struct device *dev;
u32 num_of_supplies;
struct regulator_bulk_data *supplies;
struct snd_soc_codec *codec;
struct work_struct msm_anlg_add_child_devices_work;
struct msm_dig_ctrl_platform_data dig_plat_data;
/* digital codec data structure */
struct msm_dig_ctrl_data *dig_ctrl_data;
struct blocking_notifier_head notifier;
u16 pmic_rev;
u16 codec_version;
u16 analog_major_rev;
u32 boost_voltage;
u32 adc_count;
u32 rx_bias_count;
bool int_mclk0_enabled;
u16 boost_option;
/* mode to select hd2 */
u32 hph_mode;
/* compander used for each rx chain */
bool spk_boost_set;
bool ear_pa_boost_set;
bool ext_spk_boost_set;
struct on_demand_supply on_demand_list[ON_DEMAND_SUPPLIES_MAX];
struct regulator *spkdrv_reg;
struct blocking_notifier_head notifier_mbhc;
/* mbhc module */
struct wcd_mbhc mbhc;
/* cal info for codec */
struct fw_info *fw_data;
struct notifier_block audio_ssr_nb;
int (*codec_spk_ext_pa_cb)(struct snd_soc_codec *codec, int enable);
unsigned long status_mask;
struct wcd_imped_i_ref imped_i_ref;
enum wcd_mbhc_imp_det_pin imped_det_pin;
/* Entry for version info */
struct snd_info_entry *entry;
struct snd_info_entry *version_entry;
struct platform_device *pdev_child_devices
[ANLG_CDC_CHILD_DEVICES_MAX];
int child_count;
};
struct sdm660_cdc_pdata {
struct wcd_micbias_setting micbias;
struct sdm660_cdc_regulator regulator[MAX_REGULATOR];
};
#if IS_ENABLED(CONFIG_SND_SOC_ANALOG_CDC)
extern int msm_anlg_cdc_mclk_enable(struct snd_soc_codec *codec,
int mclk_enable, bool dapm);
extern int msm_anlg_cdc_hs_detect(struct snd_soc_codec *codec,
struct wcd_mbhc_config *mbhc_cfg);
extern void msm_anlg_cdc_hs_detect_exit(struct snd_soc_codec *codec);
extern void sdm660_cdc_update_int_spk_boost(bool enable);
extern void msm_anlg_cdc_spk_ext_pa_cb(
int (*codec_spk_ext_pa)(struct snd_soc_codec *codec,
int enable), struct snd_soc_codec *codec);
int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
struct snd_soc_codec *codec);
#else /* CONFIG_SND_SOC_ANALOG_CDC */
static inline int msm_anlg_cdc_mclk_enable(struct snd_soc_codec *codec,
int mclk_enable, bool dapm)
{
return 0;
}
static inline int msm_anlg_cdc_hs_detect(struct snd_soc_codec *codec,
struct wcd_mbhc_config *mbhc_cfg)
{
return 0;
}
static inline void msm_anlg_cdc_hs_detect_exit(struct snd_soc_codec *codec)
{
}
static inline void sdm660_cdc_update_int_spk_boost(bool enable)
{
}
static inline void msm_anlg_cdc_spk_ext_pa_cb(
int (*codec_spk_ext_pa)(struct snd_soc_codec *codec,
int enable), struct snd_soc_codec *codec)
{
}
static inline int msm_anlg_codec_info_create_codec_entry(
struct snd_info_entry *codec_root,
struct snd_soc_codec *codec)
{
return 0;
}
#endif /* CONFIG_SND_SOC_ANALOG_CDC */
#endif

67
asoc/codecs/sdm660_cdc/msm-cdc-common.h
View File

@@ -1,67 +0,0 @@
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/regmap.h>
#include "sdm660-cdc-registers.h"
extern struct reg_default
msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE];
extern struct reg_default
msm89xx_pmic_cdc_defaults[MSM89XX_PMIC_CDC_CACHE_SIZE];
bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg);
bool msm89xx_cdc_core_writeable_reg(struct device *dev, unsigned int reg);
bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg);
enum {
AIF1_PB = 0,
AIF1_CAP,
AIF2_VIFEED,
AIF3_SVA,
NUM_CODEC_DAIS,
};
enum codec_versions {
TOMBAK_1_0,
TOMBAK_2_0,
CONGA,
CAJON,
CAJON_2_0,
DIANGU,
DRAX_CDC,
UNSUPPORTED,
};
/* Support different hph modes */
enum {
NORMAL_MODE = 0,
HD2_MODE,
};
enum dig_cdc_notify_event {
DIG_CDC_EVENT_INVALID,
DIG_CDC_EVENT_CLK_ON,
DIG_CDC_EVENT_CLK_OFF,
DIG_CDC_EVENT_RX1_MUTE_ON,
DIG_CDC_EVENT_RX1_MUTE_OFF,
DIG_CDC_EVENT_RX2_MUTE_ON,
DIG_CDC_EVENT_RX2_MUTE_OFF,
DIG_CDC_EVENT_RX3_MUTE_ON,
DIG_CDC_EVENT_RX3_MUTE_OFF,
DIG_CDC_EVENT_PRE_RX1_INT_ON,
DIG_CDC_EVENT_PRE_RX2_INT_ON,
DIG_CDC_EVENT_POST_RX1_INT_OFF,
DIG_CDC_EVENT_POST_RX2_INT_OFF,
DIG_CDC_EVENT_SSR_DOWN,
DIG_CDC_EVENT_SSR_UP,
DIG_CDC_EVENT_LAST,
};

452
asoc/codecs/sdm660_cdc/msm-digital-cdc-regmap.c
View File

@@ -1,452 +0,0 @@
/*
* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/regmap.h>
#include "msm-cdc-common.h"
#include "sdm660-cdc-registers.h"
/*
* Default register reset values that are common across different versions
* are defined here. If a register reset value is changed based on version
* then remove it from this structure and add it in version specific
* structures.
*/
struct reg_default
msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE] = {
{MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x13},
{MSM89XX_CDC_CORE_CLK_TX_I2S_CTL, 0x13},
{MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_OTHR_CTL, 0x04},
{MSM89XX_CDC_CORE_CLK_RX_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_SD_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL, 0x13},
{MSM89XX_CDC_CORE_RX1_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_RX2_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_RX3_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_RX1_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_RX2_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_RX3_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_RX1_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_RX2_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_RX3_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_RX1_B4_CTL, 0x00},
{MSM89XX_CDC_CORE_RX2_B4_CTL, 0x00},
{MSM89XX_CDC_CORE_RX3_B4_CTL, 0x00},
{MSM89XX_CDC_CORE_RX1_B5_CTL, 0x68},
{MSM89XX_CDC_CORE_RX2_B5_CTL, 0x68},
{MSM89XX_CDC_CORE_RX3_B5_CTL, 0x68},
{MSM89XX_CDC_CORE_RX1_B6_CTL, 0x00},
{MSM89XX_CDC_CORE_RX2_B6_CTL, 0x00},
{MSM89XX_CDC_CORE_RX3_B6_CTL, 0x00},
{MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_TOP_GAIN_UPDATE, 0x00},
{MSM89XX_CDC_CORE_TOP_CTL, 0x01},
{MSM89XX_CDC_CORE_COMP0_B1_CTL, 0x30},
{MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xB5},
{MSM89XX_CDC_CORE_COMP0_B3_CTL, 0x28},
{MSM89XX_CDC_CORE_COMP0_B4_CTL, 0x37},
{MSM89XX_CDC_CORE_COMP0_B5_CTL, 0x7F},
{MSM89XX_CDC_CORE_COMP0_B6_CTL, 0x00},
{MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS, 0x03},
{MSM89XX_CDC_CORE_COMP0_FS_CFG, 0x03},
{MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL, 0x02},
{MSM89XX_CDC_CORE_DEBUG_DESER1_CTL, 0x00},
{MSM89XX_CDC_CORE_DEBUG_DESER2_CTL, 0x00},
{MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_CTL, 0x40},
{MSM89XX_CDC_CORE_IIR2_CTL, 0x40},
{MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX1_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX1_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX2_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX2_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX3_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_TX_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_TX_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_TX_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER, 0x00},
{MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN, 0x00},
{MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_TX5_MUX_CTL, 0x00},
{MSM89XX_CDC_CORE_TX5_CLK_FS_CTL, 0x03},
{MSM89XX_CDC_CORE_TX5_DMIC_CTL, 0x00},
{MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER, 0x00},
{MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER, 0x00},
{MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER, 0x00},
{MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER, 0x00},
{MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, 0x00},
{MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, 0x00},
{MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, 0x00},
{MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, 0x00},
{MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_TX1_MUX_CTL, 0x00},
{MSM89XX_CDC_CORE_TX2_MUX_CTL, 0x00},
{MSM89XX_CDC_CORE_TX3_MUX_CTL, 0x00},
{MSM89XX_CDC_CORE_TX4_MUX_CTL, 0x00},
{MSM89XX_CDC_CORE_TX1_CLK_FS_CTL, 0x03},
{MSM89XX_CDC_CORE_TX2_CLK_FS_CTL, 0x03},
{MSM89XX_CDC_CORE_TX3_CLK_FS_CTL, 0x03},
{MSM89XX_CDC_CORE_TX4_CLK_FS_CTL, 0x03},
{MSM89XX_CDC_CORE_TX1_DMIC_CTL, 0x00},
{MSM89XX_CDC_CORE_TX2_DMIC_CTL, 0x00},
{MSM89XX_CDC_CORE_TX3_DMIC_CTL, 0x00},
{MSM89XX_CDC_CORE_TX4_DMIC_CTL, 0x00},
};
static const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE] = {
[MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_SD_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_RX_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B3_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B3_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B3_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B4_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B4_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B4_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B5_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B5_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B5_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B6_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B6_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B6_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1,
[MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1,
[MSM89XX_CDC_CORE_TOP_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B1_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B2_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B3_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B4_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B5_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B6_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS] = 1,
[MSM89XX_CDC_CORE_COMP0_FS_CFG] = 1,
[MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL] = 1,
[MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1,
[MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1,
[MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_B3_CTL] = 1,
[MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX5_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX5_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX5_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1,
};
static const u8 msm89xx_cdc_core_reg_writeable[MSM89XX_CDC_CORE_CACHE_SIZE] = {
[MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_SD_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_RX_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B3_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B3_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B3_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B4_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B4_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B4_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B5_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B5_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B5_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B6_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B6_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B6_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1,
[MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1,
[MSM89XX_CDC_CORE_TOP_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B1_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B2_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B3_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B4_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B5_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B6_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_FS_CFG] = 1,
[MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL] = 1,
[MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1,
[MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1,
[MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_B3_CTL] = 1,
[MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX5_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX5_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX5_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1,
};
bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg)
{
return msm89xx_cdc_core_reg_readable[reg];
}
bool msm89xx_cdc_core_writeable_reg(struct device *dev, unsigned int reg)
{
return msm89xx_cdc_core_reg_writeable[reg];
}
bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MSM89XX_CDC_CORE_RX1_B1_CTL:
case MSM89XX_CDC_CORE_RX2_B1_CTL:
case MSM89XX_CDC_CORE_RX3_B1_CTL:
case MSM89XX_CDC_CORE_RX1_B6_CTL:
case MSM89XX_CDC_CORE_RX2_B6_CTL:
case MSM89XX_CDC_CORE_RX3_B6_CTL:
case MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG:
case MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG:
case MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG:
case MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG:
case MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG:
case MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL:
case MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL:
case MSM89XX_CDC_CORE_CLK_MCLK_CTL:
case MSM89XX_CDC_CORE_CLK_PDM_CTL:
return true;
default:
return false;
}
}

2213
asoc/codecs/sdm660_cdc/msm-digital-cdc.c
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116
asoc/codecs/sdm660_cdc/msm-digital-cdc.h
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@@ -1,116 +0,0 @@
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MSM_DIGITAL_CDC_H
#define MSM_DIGITAL_CDC_H
#define HPHL_PA_DISABLE (0x01 << 1)
#define HPHR_PA_DISABLE (0x01 << 2)
#define SPKR_PA_DISABLE (0x01 << 3)
#define NUM_DECIMATORS 5
/* Codec supports 1 compander */
enum {
COMPANDER_NONE = 0,
COMPANDER_1, /* HPHL/R */
COMPANDER_MAX,
};
/* Number of output I2S port */
enum {
MSM89XX_RX1 = 0,
MSM89XX_RX2,
MSM89XX_RX3,
MSM89XX_RX_MAX,
};
struct tx_mute_work {
struct msm_dig_priv *dig_cdc;
u32 decimator;
struct delayed_work dwork;
};
struct msm_dig_priv {
struct snd_soc_codec *codec;
u32 comp_enabled[MSM89XX_RX_MAX];
int (*codec_hph_comp_gpio)(bool enable, struct snd_soc_codec *codec);
s32 dmic_1_2_clk_cnt;
s32 dmic_3_4_clk_cnt;
bool dec_active[NUM_DECIMATORS];
int version;
/* Entry for version info */
struct snd_info_entry *entry;
struct snd_info_entry *version_entry;
char __iomem *dig_base;
struct regmap *regmap;
struct notifier_block nblock;
u32 mute_mask;
int dapm_bias_off;
void *handle;
void (*set_compander_mode)(void *handle, int val);
void (*update_clkdiv)(void *handle, int val);
int (*get_cdc_version)(void *handle);
int (*register_notifier)(void *handle,
struct notifier_block *nblock,
bool enable);
struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS];
};
struct dig_ctrl_platform_data {
void *handle;
void (*set_compander_mode)(void *handle, int val);
void (*update_clkdiv)(void *handle, int val);
int (*get_cdc_version)(void *handle);
int (*register_notifier)(void *handle,
struct notifier_block *nblock,
bool enable);
};
struct hpf_work {
struct msm_dig_priv *dig_cdc;
u32 decimator;
u8 tx_hpf_cut_of_freq;
struct delayed_work dwork;
};
/* Codec supports 5 bands */
enum {
BAND1 = 0,
BAND2,
BAND3,
BAND4,
BAND5,
BAND_MAX,
};
#if IS_ENABLED(CONFIG_SND_SOC_DIGITAL_CDC)
extern void msm_dig_cdc_hph_comp_cb(
int (*codec_hph_comp_gpio)(
bool enable, struct snd_soc_codec *codec),
struct snd_soc_codec *codec);
int msm_dig_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
struct snd_soc_codec *codec);
#else /* CONFIG_SND_SOC_DIGITAL_CDC */
static inline void msm_dig_cdc_hph_comp_cb(
int (*codec_hph_comp_gpio)(
bool enable, struct snd_soc_codec *codec),
struct snd_soc_codec *codec)
{
}
static inline int msm_dig_codec_info_create_codec_entry(
struct snd_info_entry *codec_root,
struct snd_soc_codec *codec)
{
return 0;
}
#endif /* CONFIG_SND_SOC_DIGITAL_CDC */
#endif

418
asoc/codecs/sdm660_cdc/sdm660-cdc-irq.c
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@@ -1,418 +0,0 @@
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/of_irq.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/spmi.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/interrupt.h>
#include <linux/pm_qos.h>
#include <soc/qcom/pm.h>
#include <sound/soc.h>
#include "msm-analog-cdc.h"
#include "sdm660-cdc-irq.h"
#include "sdm660-cdc-registers.h"
#define MAX_NUM_IRQS 14
#define NUM_IRQ_REGS 2
#define WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS 700
#define BYTE_BIT_MASK(nr) (1UL << ((nr) % BITS_PER_BYTE))
#define BIT_BYTE(nr) ((nr) / BITS_PER_BYTE)
static irqreturn_t wcd9xxx_spmi_irq_handler(int linux_irq, void *data);
char *irq_names[MAX_NUM_IRQS] = {
"spk_cnp_int",
"spk_clip_int",
"spk_ocp_int",
"ins_rem_det1",
"but_rel_det",
"but_press_det",
"ins_rem_det",
"mbhc_int",
"ear_ocp_int",
"hphr_ocp_int",
"hphl_ocp_det",
"ear_cnp_int",
"hphr_cnp_int",
"hphl_cnp_int"
};
int order[MAX_NUM_IRQS] = {
MSM89XX_IRQ_SPKR_CNP,
MSM89XX_IRQ_SPKR_CLIP,
MSM89XX_IRQ_SPKR_OCP,
MSM89XX_IRQ_MBHC_INSREM_DET1,
MSM89XX_IRQ_MBHC_RELEASE,
MSM89XX_IRQ_MBHC_PRESS,
MSM89XX_IRQ_MBHC_INSREM_DET,
MSM89XX_IRQ_MBHC_HS_DET,
MSM89XX_IRQ_EAR_OCP,
MSM89XX_IRQ_HPHR_OCP,
MSM89XX_IRQ_HPHL_OCP,
MSM89XX_IRQ_EAR_CNP,
MSM89XX_IRQ_HPHR_CNP,
MSM89XX_IRQ_HPHL_CNP,
};
enum wcd9xxx_spmi_pm_state {
WCD9XXX_PM_SLEEPABLE,
WCD9XXX_PM_AWAKE,
WCD9XXX_PM_ASLEEP,
};
struct wcd9xxx_spmi_map {
uint8_t handled[NUM_IRQ_REGS];
uint8_t mask[NUM_IRQ_REGS];
int linuxirq[MAX_NUM_IRQS];
irq_handler_t handler[MAX_NUM_IRQS];
struct platform_device *spmi[NUM_IRQ_REGS];
struct snd_soc_codec *codec;
enum wcd9xxx_spmi_pm_state pm_state;
struct mutex pm_lock;
/* pm_wq notifies change of pm_state */
wait_queue_head_t pm_wq;
struct pm_qos_request pm_qos_req;
int wlock_holders;
};
struct wcd9xxx_spmi_map map;
void wcd9xxx_spmi_enable_irq(int irq)
{
pr_debug("%s: irqno =%d\n", __func__, irq);
if (!(map.mask[BIT_BYTE(irq)] & (BYTE_BIT_MASK(irq))))
return;
map.mask[BIT_BYTE(irq)] &=
~(BYTE_BIT_MASK(irq));
enable_irq(map.linuxirq[irq]);
}
void wcd9xxx_spmi_disable_irq(int irq)
{
pr_debug("%s: irqno =%d\n", __func__, irq);
if (map.mask[BIT_BYTE(irq)] & (BYTE_BIT_MASK(irq)))
return;
map.mask[BIT_BYTE(irq)] |=
(BYTE_BIT_MASK(irq));
disable_irq_nosync(map.linuxirq[irq]);
}
int wcd9xxx_spmi_request_irq(int irq, irq_handler_t handler,
const char *name, void *priv)
{
int rc;
unsigned long irq_flags;
map.linuxirq[irq] =
platform_get_irq_byname(map.spmi[BIT_BYTE(irq)],
irq_names[irq]);
if (strcmp(name, "mbhc sw intr"))
irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
IRQF_ONESHOT;
else
irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
IRQF_ONESHOT | IRQF_NO_SUSPEND;
pr_debug("%s: name:%s irq_flags = %lx\n", __func__, name, irq_flags);
rc = devm_request_threaded_irq(&map.spmi[BIT_BYTE(irq)]->dev,
map.linuxirq[irq], NULL,
wcd9xxx_spmi_irq_handler,
irq_flags,
name, priv);
if (rc < 0) {
dev_err(&map.spmi[BIT_BYTE(irq)]->dev,
"Can't request %d IRQ\n", irq);
return rc;
}
dev_dbg(&map.spmi[BIT_BYTE(irq)]->dev,
"irq %d linuxIRQ: %d\n", irq, map.linuxirq[irq]);
map.mask[BIT_BYTE(irq)] &= ~BYTE_BIT_MASK(irq);
map.handler[irq] = handler;
enable_irq_wake(map.linuxirq[irq]);
return 0;
}
int wcd9xxx_spmi_free_irq(int irq, void *priv)
{
devm_free_irq(&map.spmi[BIT_BYTE(irq)]->dev, map.linuxirq[irq],
priv);
map.mask[BIT_BYTE(irq)] |= BYTE_BIT_MASK(irq);
return 0;
}
static int get_irq_bit(int linux_irq)
{
int i = 0;
for (; i < MAX_NUM_IRQS; i++)
if (map.linuxirq[i] == linux_irq)
return i;
return i;
}
static int get_order_irq(int i)
{
return order[i];
}
static irqreturn_t wcd9xxx_spmi_irq_handler(int linux_irq, void *data)
{
int irq, i, j;
unsigned long status[NUM_IRQ_REGS] = {0};
if (unlikely(wcd9xxx_spmi_lock_sleep() == false)) {
pr_err("Failed to hold suspend\n");
return IRQ_NONE;
}
irq = get_irq_bit(linux_irq);
if (irq == MAX_NUM_IRQS)
return IRQ_HANDLED;
status[BIT_BYTE(irq)] |= BYTE_BIT_MASK(irq);
for (i = 0; i < NUM_IRQ_REGS; i++) {
status[i] |= snd_soc_read(map.codec,
BIT_BYTE(irq) * 0x100 +
MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS);
status[i] &= ~map.mask[i];
}
for (i = 0; i < MAX_NUM_IRQS; i++) {
j = get_order_irq(i);
if ((status[BIT_BYTE(j)] & BYTE_BIT_MASK(j)) &&
((map.handled[BIT_BYTE(j)] &
BYTE_BIT_MASK(j)) == 0)) {
map.handler[j](irq, data);
map.handled[BIT_BYTE(j)] |=
BYTE_BIT_MASK(j);
}
}
map.handled[BIT_BYTE(irq)] &= ~BYTE_BIT_MASK(irq);
wcd9xxx_spmi_unlock_sleep();
return IRQ_HANDLED;
}
enum wcd9xxx_spmi_pm_state wcd9xxx_spmi_pm_cmpxchg(
enum wcd9xxx_spmi_pm_state o,
enum wcd9xxx_spmi_pm_state n)
{
enum wcd9xxx_spmi_pm_state old;
mutex_lock(&map.pm_lock);
old = map.pm_state;
if (old == o)
map.pm_state = n;
pr_debug("%s: map.pm_state = %d\n", __func__, map.pm_state);
mutex_unlock(&map.pm_lock);
return old;
}
EXPORT_SYMBOL(wcd9xxx_spmi_pm_cmpxchg);
int wcd9xxx_spmi_suspend(pm_message_t pmesg)
{
int ret = 0;
pr_debug("%s: enter\n", __func__);
/*
* pm_qos_update_request() can be called after this suspend chain call
* started. thus suspend can be called while lock is being held
*/
mutex_lock(&map.pm_lock);
if (map.pm_state == WCD9XXX_PM_SLEEPABLE) {
pr_debug("%s: suspending system, state %d, wlock %d\n",
__func__, map.pm_state,
map.wlock_holders);
map.pm_state = WCD9XXX_PM_ASLEEP;
} else if (map.pm_state == WCD9XXX_PM_AWAKE) {
/*
* unlock to wait for pm_state == WCD9XXX_PM_SLEEPABLE
* then set to WCD9XXX_PM_ASLEEP
*/
pr_debug("%s: waiting to suspend system, state %d, wlock %d\n",
__func__, map.pm_state,
map.wlock_holders);
mutex_unlock(&map.pm_lock);
if (!(wait_event_timeout(map.pm_wq,
wcd9xxx_spmi_pm_cmpxchg(
WCD9XXX_PM_SLEEPABLE,
WCD9XXX_PM_ASLEEP) ==
WCD9XXX_PM_SLEEPABLE,
HZ))) {
pr_debug("%s: suspend failed state %d, wlock %d\n",
__func__, map.pm_state,
map.wlock_holders);
ret = -EBUSY;
} else {
pr_debug("%s: done, state %d, wlock %d\n", __func__,
map.pm_state,
map.wlock_holders);
}
mutex_lock(&map.pm_lock);
} else if (map.pm_state == WCD9XXX_PM_ASLEEP) {
pr_warn("%s: system is already suspended, state %d, wlock %dn",
__func__, map.pm_state,
map.wlock_holders);
}
mutex_unlock(&map.pm_lock);
return ret;
}
EXPORT_SYMBOL(wcd9xxx_spmi_suspend);
int wcd9xxx_spmi_resume(void)
{
int ret = 0;
pr_debug("%s: enter\n", __func__);
mutex_lock(&map.pm_lock);
if (map.pm_state == WCD9XXX_PM_ASLEEP) {
pr_debug("%s: resuming system, state %d, wlock %d\n", __func__,
map.pm_state,
map.wlock_holders);
map.pm_state = WCD9XXX_PM_SLEEPABLE;
} else {
pr_warn("%s: system is already awake, state %d wlock %d\n",
__func__, map.pm_state,
map.wlock_holders);
}
mutex_unlock(&map.pm_lock);
wake_up_all(&map.pm_wq);
return ret;
}
EXPORT_SYMBOL(wcd9xxx_spmi_resume);
bool wcd9xxx_spmi_lock_sleep(void)
{
/*
* wcd9xxx_spmi_{lock/unlock}_sleep will be called by
* wcd9xxx_spmi_irq_thread
* and its subroutines only motly.
* but btn0_lpress_fn is not wcd9xxx_spmi_irq_thread's subroutine and
* It can race with wcd9xxx_spmi_irq_thread.
* So need to embrace wlock_holders with mutex.
*/
mutex_lock(&map.pm_lock);
if (map.wlock_holders++ == 0) {
pr_debug("%s: holding wake lock\n", __func__);
pm_qos_update_request(&map.pm_qos_req,
msm_cpuidle_get_deep_idle_latency());
pm_stay_awake(&map.spmi[0]->dev);
}
mutex_unlock(&map.pm_lock);
pr_debug("%s: wake lock counter %d\n", __func__,
map.wlock_holders);
pr_debug("%s: map.pm_state = %d\n", __func__, map.pm_state);
if (!wait_event_timeout(map.pm_wq,
((wcd9xxx_spmi_pm_cmpxchg(
WCD9XXX_PM_SLEEPABLE,
WCD9XXX_PM_AWAKE)) ==
WCD9XXX_PM_SLEEPABLE ||
(wcd9xxx_spmi_pm_cmpxchg(
WCD9XXX_PM_SLEEPABLE,
WCD9XXX_PM_AWAKE) ==
WCD9XXX_PM_AWAKE)),
msecs_to_jiffies(
WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS))) {
pr_warn("%s: system didn't resume within %dms, s %d, w %d\n",
__func__,
WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS, map.pm_state,
map.wlock_holders);
wcd9xxx_spmi_unlock_sleep();
return false;
}
wake_up_all(&map.pm_wq);
pr_debug("%s: leaving pm_state = %d\n", __func__, map.pm_state);
return true;
}
EXPORT_SYMBOL(wcd9xxx_spmi_lock_sleep);
void wcd9xxx_spmi_unlock_sleep(void)
{
mutex_lock(&map.pm_lock);
if (--map.wlock_holders == 0) {
pr_debug("%s: releasing wake lock pm_state %d -> %d\n",
__func__, map.pm_state, WCD9XXX_PM_SLEEPABLE);
/*
* if wcd9xxx_spmi_lock_sleep failed, pm_state would be still
* WCD9XXX_PM_ASLEEP, don't overwrite
*/
if (likely(map.pm_state == WCD9XXX_PM_AWAKE))
map.pm_state = WCD9XXX_PM_SLEEPABLE;
pm_qos_update_request(&map.pm_qos_req,
PM_QOS_DEFAULT_VALUE);
pm_relax(&map.spmi[0]->dev);
}
mutex_unlock(&map.pm_lock);
pr_debug("%s: wake lock counter %d\n", __func__,
map.wlock_holders);
pr_debug("%s: map.pm_state = %d\n", __func__, map.pm_state);
wake_up_all(&map.pm_wq);
}
EXPORT_SYMBOL(wcd9xxx_spmi_unlock_sleep);
void wcd9xxx_spmi_set_codec(struct snd_soc_codec *codec)
{
map.codec = codec;
}
void wcd9xxx_spmi_set_dev(struct platform_device *spmi, int i)
{
if (i < NUM_IRQ_REGS)
map.spmi[i] = spmi;
}
int wcd9xxx_spmi_irq_init(void)
{
int i = 0;
for (; i < MAX_NUM_IRQS; i++)
map.mask[BIT_BYTE(i)] |= BYTE_BIT_MASK(i);
mutex_init(&map.pm_lock);
map.wlock_holders = 0;
map.pm_state = WCD9XXX_PM_SLEEPABLE;
init_waitqueue_head(&map.pm_wq);
pm_qos_add_request(&map.pm_qos_req,
PM_QOS_CPU_DMA_LATENCY,
PM_QOS_DEFAULT_VALUE);
return 0;
}
void wcd9xxx_spmi_irq_exit(void)
{
pm_qos_remove_request(&map.pm_qos_req);
mutex_destroy(&map.pm_lock);
}
MODULE_DESCRIPTION("MSM8x16 SPMI IRQ driver");
MODULE_LICENSE("GPL v2");

35
asoc/codecs/sdm660_cdc/sdm660-cdc-irq.h
View File

@@ -1,35 +0,0 @@
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __WCD9XXX_SPMI_IRQ_H__
#define __WCD9XXX_SPMI_IRQ_H__
#include <sound/soc.h>
#include <linux/spmi.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/pm_qos.h>
extern void wcd9xxx_spmi_enable_irq(int irq);
extern void wcd9xxx_spmi_disable_irq(int irq);
extern int wcd9xxx_spmi_request_irq(int irq, irq_handler_t handler,
const char *name, void *priv);
extern int wcd9xxx_spmi_free_irq(int irq, void *priv);
extern void wcd9xxx_spmi_set_codec(struct snd_soc_codec *codec);
extern void wcd9xxx_spmi_set_dev(struct platform_device *spmi, int i);
extern int wcd9xxx_spmi_irq_init(void);
extern void wcd9xxx_spmi_irq_exit(void);
extern int wcd9xxx_spmi_suspend(pm_message_t pmesg);
extern int wcd9xxx_spmi_resume(void);
bool wcd9xxx_spmi_lock_sleep(void);
void wcd9xxx_spmi_unlock_sleep(void);
#endif

603
asoc/codecs/sdm660_cdc/sdm660-cdc-registers.h
View File

@@ -1,603 +0,0 @@
/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SDM660_WCD_REGISTERS_H
#define SDM660_WCD_REGISTERS_H
#define CDC_DIG_BASE 0xF000
#define CDC_ANA_BASE 0xF100
#define MSM89XX_PMIC_DIGITAL_REVISION1 (CDC_DIG_BASE+0x000)
#define MSM89XX_PMIC_DIGITAL_REVISION1__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_REVISION2 (CDC_DIG_BASE+0x001)
#define MSM89XX_PMIC_DIGITAL_REVISION2__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_PERPH_TYPE (CDC_DIG_BASE+0x004)
#define MSM89XX_PMIC_DIGITAL_PERPH_TYPE__POR (0x23)
#define MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE (CDC_DIG_BASE+0x005)
#define MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE__POR (0x01)
#define MSM89XX_PMIC_DIGITAL_INT_RT_STS (CDC_DIG_BASE+0x010)
#define MSM89XX_PMIC_DIGITAL_INT_RT_STS__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_SET_TYPE (CDC_DIG_BASE+0x011)
#define MSM89XX_PMIC_DIGITAL_INT_SET_TYPE__POR (0xFF)
#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH (CDC_DIG_BASE+0x012)
#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH__POR (0xFF)
#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW (CDC_DIG_BASE+0x013)
#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR (CDC_DIG_BASE+0x014)
#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_EN_SET (CDC_DIG_BASE+0x015)
#define MSM89XX_PMIC_DIGITAL_INT_EN_SET__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_EN_CLR (CDC_DIG_BASE+0x016)
#define MSM89XX_PMIC_DIGITAL_INT_EN_CLR__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS (CDC_DIG_BASE+0x018)
#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_PENDING_STS (CDC_DIG_BASE+0x019)
#define MSM89XX_PMIC_DIGITAL_INT_PENDING_STS__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_MID_SEL (CDC_DIG_BASE+0x01A)
#define MSM89XX_PMIC_DIGITAL_INT_MID_SEL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_PRIORITY (CDC_DIG_BASE+0x01B)
#define MSM89XX_PMIC_DIGITAL_INT_PRIORITY__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_GPIO_MODE (CDC_DIG_BASE+0x040)
#define MSM89XX_PMIC_DIGITAL_GPIO_MODE__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_PIN_CTL_OE (CDC_DIG_BASE+0x041)
#define MSM89XX_PMIC_DIGITAL_PIN_CTL_OE__POR (0x01)
#define MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA (CDC_DIG_BASE+0x042)
#define MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_PIN_STATUS (CDC_DIG_BASE+0x043)
#define MSM89XX_PMIC_DIGITAL_PIN_STATUS__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_HDRIVE_CTL (CDC_DIG_BASE+0x044)
#define MSM89XX_PMIC_DIGITAL_HDRIVE_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_RST_CTL (CDC_DIG_BASE+0x046)
#define MSM89XX_PMIC_DIGITAL_CDC_RST_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL (CDC_DIG_BASE+0x048)
#define MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL (CDC_DIG_BASE+0x049)
#define MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL (CDC_DIG_BASE+0x04A)
#define MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL (CDC_DIG_BASE+0x050)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL__POR (0x02)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL (CDC_DIG_BASE+0x051)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL__POR (0x02)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL (CDC_DIG_BASE+0x052)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL (CDC_DIG_BASE+0x053)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL (CDC_DIG_BASE+0x054)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL (CDC_DIG_BASE+0x055)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL (CDC_DIG_BASE+0x056)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1 (CDC_DIG_BASE+0x058)
#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1__POR (0x7C)
#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2 (CDC_DIG_BASE+0x059)
#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2__POR (0x7C)
#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3 (CDC_DIG_BASE+0x05A)
#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3__POR (0x7C)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0 (CDC_DIG_BASE+0x05B)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1 (CDC_DIG_BASE+0x05C)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2 (CDC_DIG_BASE+0x05D)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3 (CDC_DIG_BASE+0x05E)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL (CDC_DIG_BASE+0x068)
#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN (CDC_DIG_BASE+0x069)
#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_SPARE_0 (CDC_DIG_BASE+0x070)
#define MSM89XX_PMIC_DIGITAL_SPARE_0__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_SPARE_1 (CDC_DIG_BASE+0x071)
#define MSM89XX_PMIC_DIGITAL_SPARE_1__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_SPARE_2 (CDC_DIG_BASE+0x072)
#define MSM89XX_PMIC_DIGITAL_SPARE_2__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_SEC_ACCESS (CDC_DIG_BASE+0x0D0)
#define MSM89XX_PMIC_DIGITAL_SEC_ACCESS__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1 (CDC_DIG_BASE+0x0D8)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2 (CDC_DIG_BASE+0x0D9)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2__POR (0x01)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3 (CDC_DIG_BASE+0x0DA)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3__POR (0x05)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4 (CDC_DIG_BASE+0x0DB)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_TEST1 (CDC_DIG_BASE+0x0E0)
#define MSM89XX_PMIC_DIGITAL_INT_TEST1__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_TEST_VAL (CDC_DIG_BASE+0x0E1)
#define MSM89XX_PMIC_DIGITAL_INT_TEST_VAL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_TRIM_NUM (CDC_DIG_BASE+0x0F0)
#define MSM89XX_PMIC_DIGITAL_TRIM_NUM__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_TRIM_CTRL (CDC_DIG_BASE+0x0F1)
#define MSM89XX_PMIC_DIGITAL_TRIM_CTRL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_REVISION1 (CDC_ANA_BASE+0x00)
#define MSM89XX_PMIC_ANALOG_REVISION1__POR (0x00)
#define MSM89XX_PMIC_ANALOG_REVISION2 (CDC_ANA_BASE+0x01)
#define MSM89XX_PMIC_ANALOG_REVISION2__POR (0x00)
#define MSM89XX_PMIC_ANALOG_REVISION3 (CDC_ANA_BASE+0x02)
#define MSM89XX_PMIC_ANALOG_REVISION3__POR (0x00)
#define MSM89XX_PMIC_ANALOG_REVISION4 (CDC_ANA_BASE+0x03)
#define MSM89XX_PMIC_ANALOG_REVISION4__POR (0x00)
#define MSM89XX_PMIC_ANALOG_PERPH_TYPE (CDC_ANA_BASE+0x04)
#define MSM89XX_PMIC_ANALOG_PERPH_TYPE__POR (0x23)
#define MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE (CDC_ANA_BASE+0x05)
#define MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE__POR (0x09)
#define MSM89XX_PMIC_ANALOG_INT_RT_STS (CDC_ANA_BASE+0x10)
#define MSM89XX_PMIC_ANALOG_INT_RT_STS__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_SET_TYPE (CDC_ANA_BASE+0x11)
#define MSM89XX_PMIC_ANALOG_INT_SET_TYPE__POR (0x3F)
#define MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH (CDC_ANA_BASE+0x12)
#define MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH__POR (0x3F)
#define MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW (CDC_ANA_BASE+0x13)
#define MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR (CDC_ANA_BASE+0x14)
#define MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_EN_SET (CDC_ANA_BASE+0x15)
#define MSM89XX_PMIC_ANALOG_INT_EN_SET__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_EN_CLR (CDC_ANA_BASE+0x16)
#define MSM89XX_PMIC_ANALOG_INT_EN_CLR__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_LATCHED_STS (CDC_ANA_BASE+0x18)
#define MSM89XX_PMIC_ANALOG_INT_LATCHED_STS__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_PENDING_STS (CDC_ANA_BASE+0x19)
#define MSM89XX_PMIC_ANALOG_INT_PENDING_STS__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_MID_SEL (CDC_ANA_BASE+0x1A)
#define MSM89XX_PMIC_ANALOG_INT_MID_SEL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_PRIORITY (CDC_ANA_BASE+0x1B)
#define MSM89XX_PMIC_ANALOG_INT_PRIORITY__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MICB_1_EN (CDC_ANA_BASE+0x40)
#define MSM89XX_PMIC_ANALOG_MICB_1_EN__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MICB_1_VAL (CDC_ANA_BASE+0x41)
#define MSM89XX_PMIC_ANALOG_MICB_1_VAL__POR (0x20)
#define MSM89XX_PMIC_ANALOG_MICB_1_CTL (CDC_ANA_BASE+0x42)
#define MSM89XX_PMIC_ANALOG_MICB_1_CTL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS (CDC_ANA_BASE+0x43)
#define MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS__POR (0x49)
#define MSM89XX_PMIC_ANALOG_MICB_2_EN (CDC_ANA_BASE+0x44)
#define MSM89XX_PMIC_ANALOG_MICB_2_EN__POR (0x20)
#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2 (CDC_ANA_BASE+0x45)
#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL (CDC_ANA_BASE+0x46)
#define MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1 (CDC_ANA_BASE+0x47)
#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1__POR (0x35)
#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2 (CDC_ANA_BASE+0x50)
#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2__POR (0x08)
#define MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL (CDC_ANA_BASE+0x51)
#define MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER (CDC_ANA_BASE+0x52)
#define MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER__POR (0x98)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL (CDC_ANA_BASE+0x53)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL (CDC_ANA_BASE+0x54)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL__POR (0x20)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL (CDC_ANA_BASE+0x55)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL__POR (0x40)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL (CDC_ANA_BASE+0x56)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL__POR (0x61)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL (CDC_ANA_BASE+0x57)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL__POR (0x80)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT (CDC_ANA_BASE+0x58)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT (CDC_ANA_BASE+0x59)
#define MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT__POR (0x00)
#define MSM89XX_PMIC_ANALOG_TX_1_EN (CDC_ANA_BASE+0x60)
#define MSM89XX_PMIC_ANALOG_TX_1_EN__POR (0x03)
#define MSM89XX_PMIC_ANALOG_TX_2_EN (CDC_ANA_BASE+0x61)
#define MSM89XX_PMIC_ANALOG_TX_2_EN__POR (0x03)
#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1 (CDC_ANA_BASE+0x62)
#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1__POR (0xBF)
#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2 (CDC_ANA_BASE+0x63)
#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2__POR (0x8C)
#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL (CDC_ANA_BASE+0x64)
#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS (CDC_ANA_BASE+0x65)
#define MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS__POR (0x6B)
#define MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV (CDC_ANA_BASE+0x66)
#define MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV__POR (0x51)
#define MSM89XX_PMIC_ANALOG_TX_3_EN (CDC_ANA_BASE+0x67)
#define MSM89XX_PMIC_ANALOG_TX_3_EN__POR (0x02)
#define MSM89XX_PMIC_ANALOG_NCP_EN (CDC_ANA_BASE+0x80)
#define MSM89XX_PMIC_ANALOG_NCP_EN__POR (0x26)
#define MSM89XX_PMIC_ANALOG_NCP_CLK (CDC_ANA_BASE+0x81)
#define MSM89XX_PMIC_ANALOG_NCP_CLK__POR (0x23)
#define MSM89XX_PMIC_ANALOG_NCP_DEGLITCH (CDC_ANA_BASE+0x82)
#define MSM89XX_PMIC_ANALOG_NCP_DEGLITCH__POR (0x5B)
#define MSM89XX_PMIC_ANALOG_NCP_FBCTRL (CDC_ANA_BASE+0x83)
#define MSM89XX_PMIC_ANALOG_NCP_FBCTRL__POR (0x08)
#define MSM89XX_PMIC_ANALOG_NCP_BIAS (CDC_ANA_BASE+0x84)
#define MSM89XX_PMIC_ANALOG_NCP_BIAS__POR (0x29)
#define MSM89XX_PMIC_ANALOG_NCP_VCTRL (CDC_ANA_BASE+0x85)
#define MSM89XX_PMIC_ANALOG_NCP_VCTRL__POR (0x24)
#define MSM89XX_PMIC_ANALOG_NCP_TEST (CDC_ANA_BASE+0x86)
#define MSM89XX_PMIC_ANALOG_NCP_TEST__POR (0x00)
#define MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR (CDC_ANA_BASE+0x87)
#define MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR__POR (0xD5)
#define MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER (CDC_ANA_BASE+0x90)
#define MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER__POR (0xE8)
#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL (CDC_ANA_BASE+0x91)
#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL__POR (0xCF)
#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT (CDC_ANA_BASE+0x92)
#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT__POR (0x6E)
#define MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC (CDC_ANA_BASE+0x93)
#define MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC__POR (0x18)
#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA (CDC_ANA_BASE+0x94)
#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA__POR (0x5A)
#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP (CDC_ANA_BASE+0x95)
#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP__POR (0x69)
#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP (CDC_ANA_BASE+0x96)
#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP__POR (0x29)
#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN (CDC_ANA_BASE+0x97)
#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN__POR (0x80)
#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL (CDC_ANA_BASE+0x98)
#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL__POR (0xDA)
#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME (CDC_ANA_BASE+0x99)
#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME__POR (0x16)
#define MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST (CDC_ANA_BASE+0x9A)
#define MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST__POR (0x00)
#define MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL (CDC_ANA_BASE+0x9B)
#define MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL__POR (0x20)
#define MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST (CDC_ANA_BASE+0x9C)
#define MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST__POR (0x00)
#define MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL (CDC_ANA_BASE+0x9D)
#define MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL__POR (0x20)
#define MSM89XX_PMIC_ANALOG_RX_EAR_CTL (CDC_ANA_BASE+0x9E)
#define MSM89XX_PMIC_ANALOG_RX_EAR_CTL___POR (0x12)
#define MSM89XX_PMIC_ANALOG_RX_ATEST (CDC_ANA_BASE+0x9F)
#define MSM89XX_PMIC_ANALOG_RX_ATEST__POR (0x00)
#define MSM89XX_PMIC_ANALOG_RX_HPH_STATUS (CDC_ANA_BASE+0xA0)
#define MSM89XX_PMIC_ANALOG_RX_HPH_STATUS__POR (0x0C)
#define MSM89XX_PMIC_ANALOG_RX_EAR_STATUS (CDC_ANA_BASE+0xA1)
#define MSM89XX_PMIC_ANALOG_RX_EAR_STATUS__POR (0x00)
#define MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL (CDC_ANA_BASE+0xAC)
#define MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL (CDC_ANA_BASE+0xAD)
#define MSM89XX_PMIC_ANALOG_RX_RX_LO_EN_CTL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL (CDC_ANA_BASE+0xB0)
#define MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL__POR (0x83)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET (CDC_ANA_BASE+0xB1)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET__POR (0x91)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL (CDC_ANA_BASE+0xB2)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL__POR (0x29)
#define MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET (CDC_ANA_BASE+0xB3)
#define MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET__POR (0x4D)
#define MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL (CDC_ANA_BASE+0xB4)
#define MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL__POR (0xE1)
#define MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL (CDC_ANA_BASE+0xB5)
#define MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL__POR (0x1E)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC (CDC_ANA_BASE+0xB6)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC__POR (0xCB)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG (CDC_ANA_BASE+0xB7)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG__POR (0x00)
#define MSM89XX_PMIC_ANALOG_CURRENT_LIMIT (CDC_ANA_BASE+0xC0)
#define MSM89XX_PMIC_ANALOG_CURRENT_LIMIT__POR (0x02)
#define MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE (CDC_ANA_BASE+0xC1)
#define MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE__POR (0x14)
#define MSM89XX_PMIC_ANALOG_BYPASS_MODE (CDC_ANA_BASE+0xC2)
#define MSM89XX_PMIC_ANALOG_BYPASS_MODE__POR (0x00)
#define MSM89XX_PMIC_ANALOG_BOOST_EN_CTL (CDC_ANA_BASE+0xC3)
#define MSM89XX_PMIC_ANALOG_BOOST_EN_CTL__POR (0x1F)
#define MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO (CDC_ANA_BASE+0xC4)
#define MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO__POR (0x8C)
#define MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE (CDC_ANA_BASE+0xC5)
#define MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE__POR (0xC0)
#define MSM89XX_PMIC_ANALOG_BOOST_TEST1_1 (CDC_ANA_BASE+0xC6)
#define MSM89XX_PMIC_ANALOG_BOOST_TEST1_1__POR (0x00)
#define MSM89XX_PMIC_ANALOG_BOOST_TEST_2 (CDC_ANA_BASE+0xC7)
#define MSM89XX_PMIC_ANALOG_BOOST_TEST_2__POR (0x00)
#define MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS (CDC_ANA_BASE+0xC8)
#define MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS__POR (0x00)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS (CDC_ANA_BASE+0xC9)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS__POR (0x00)
#define MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR (CDC_ANA_BASE+0xCE)
#define MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR__POR (0x00)
#define MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL (CDC_ANA_BASE+0xCF)
#define MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_SEC_ACCESS (CDC_ANA_BASE+0xD0)
#define MSM89XX_PMIC_ANALOG_SEC_ACCESS__POR (0x00)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1 (CDC_ANA_BASE+0xD8)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1__POR (0x00)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2 (CDC_ANA_BASE+0xD9)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2__POR (0x01)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3 (CDC_ANA_BASE+0xDA)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3__POR (0x05)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4 (CDC_ANA_BASE+0xDB)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_TEST1 (CDC_ANA_BASE+0xE0)
#define MSM89XX_PMIC_ANALOG_INT_TEST1__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_TEST_VAL (CDC_ANA_BASE+0xE1)
#define MSM89XX_PMIC_ANALOG_INT_TEST_VAL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_TRIM_NUM (CDC_ANA_BASE+0xF0)
#define MSM89XX_PMIC_ANALOG_TRIM_NUM__POR (0x04)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL1 (CDC_ANA_BASE+0xF1)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL1__POR (0x00)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL2 (CDC_ANA_BASE+0xF2)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL2__POR (0x00)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL3 (CDC_ANA_BASE+0xF3)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL3__POR (0x00)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL4 (CDC_ANA_BASE+0xF4)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL4__POR (0x00)
#define MSM89XX_PMIC_CDC_NUM_REGISTERS \
(MSM89XX_PMIC_ANALOG_TRIM_CTRL4+1)
#define MSM89XX_PMIC_CDC_MAX_REGISTER \
(MSM89XX_PMIC_CDC_NUM_REGISTERS-1)
#define MSM89XX_PMIC_CDC_CACHE_SIZE \
MSM89XX_PMIC_CDC_NUM_REGISTERS
#define MSM89XX_CDC_CORE_CLK_RX_RESET_CTL (0x00)
#define MSM89XX_CDC_CORE_CLK_RX_RESET_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL (0x04)
#define MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL (0x08)
#define MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_RX_I2S_CTL (0x0C)
#define MSM89XX_CDC_CORE_CLK_RX_I2S_CTL__POR (0x13)
#define MSM89XX_CDC_CORE_CLK_TX_I2S_CTL (0x10)
#define MSM89XX_CDC_CORE_CLK_TX_I2S_CTL__POR (0x13)
#define MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL (0x14)
#define MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL (0x18)
#define MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_OTHR_CTL (0x1C)
#define MSM89XX_CDC_CORE_CLK_OTHR_CTL__POR (0x04)
#define MSM89XX_CDC_CORE_CLK_RX_B1_CTL (0x20)
#define MSM89XX_CDC_CORE_CLK_RX_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_MCLK_CTL (0x24)
#define MSM89XX_CDC_CORE_CLK_MCLK_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_PDM_CTL (0x28)
#define MSM89XX_CDC_CORE_CLK_PDM_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_SD_CTL (0x2C)
#define MSM89XX_CDC_CORE_CLK_SD_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL (0x30)
#define MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_RX_B2_CTL (0x34)
#define MSM89XX_CDC_CORE_CLK_RX_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL (0x38)
#define MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL__POR (0x13)
#define MSM89XX_CDC_CORE_RX1_B1_CTL (0x40)
#define MSM89XX_CDC_CORE_RX1_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX2_B1_CTL (0x60)
#define MSM89XX_CDC_CORE_RX2_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX3_B1_CTL (0x80)
#define MSM89XX_CDC_CORE_RX3_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX1_B2_CTL (0x44)
#define MSM89XX_CDC_CORE_RX1_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX2_B2_CTL (0x64)
#define MSM89XX_CDC_CORE_RX2_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX3_B2_CTL (0x84)
#define MSM89XX_CDC_CORE_RX3_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX1_B3_CTL (0x48)
#define MSM89XX_CDC_CORE_RX1_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX2_B3_CTL (0x68)
#define MSM89XX_CDC_CORE_RX2_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX3_B3_CTL (0x88)
#define MSM89XX_CDC_CORE_RX3_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX1_B4_CTL (0x4C)
#define MSM89XX_CDC_CORE_RX1_B4_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX2_B4_CTL (0x6C)
#define MSM89XX_CDC_CORE_RX2_B4_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX3_B4_CTL (0x8C)
#define MSM89XX_CDC_CORE_RX3_B4_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX1_B5_CTL (0x50)
#define MSM89XX_CDC_CORE_RX1_B5_CTL__POR (0x68)
#define MSM89XX_CDC_CORE_RX2_B5_CTL (0x70)
#define MSM89XX_CDC_CORE_RX2_B5_CTL__POR (0x68)
#define MSM89XX_CDC_CORE_RX3_B5_CTL (0x90)
#define MSM89XX_CDC_CORE_RX3_B5_CTL__POR (0x68)
#define MSM89XX_CDC_CORE_RX1_B6_CTL (0x54)
#define MSM89XX_CDC_CORE_RX1_B6_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX2_B6_CTL (0x74)
#define MSM89XX_CDC_CORE_RX2_B6_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX3_B6_CTL (0x94)
#define MSM89XX_CDC_CORE_RX3_B6_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL (0x58)
#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL (0x78)
#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL (0x98)
#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL (0x5C)
#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL (0x7C)
#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL (0x9C)
#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TOP_GAIN_UPDATE (0xA0)
#define MSM89XX_CDC_CORE_TOP_GAIN_UPDATE__POR (0x00)
#define MSM89XX_CDC_CORE_TOP_CTL (0xA4)
#define MSM89XX_CDC_CORE_TOP_CTL__POR (0x01)
#define MSM89XX_CDC_CORE_COMP0_B1_CTL (0xB0)
#define MSM89XX_CDC_CORE_COMP0_B1_CTL__POR (0x30)
#define MSM89XX_CDC_CORE_COMP0_B2_CTL (0xB4)
#define MSM89XX_CDC_CORE_COMP0_B2_CTL__POR (0xB5)
#define MSM89XX_CDC_CORE_COMP0_B3_CTL (0xB8)
#define MSM89XX_CDC_CORE_COMP0_B3_CTL__POR (0x28)
#define MSM89XX_CDC_CORE_COMP0_B4_CTL (0xBC)
#define MSM89XX_CDC_CORE_COMP0_B4_CTL__POR (0x37)
#define MSM89XX_CDC_CORE_COMP0_B5_CTL (0xC0)
#define MSM89XX_CDC_CORE_COMP0_B5_CTL__POR (0x7F)
#define MSM89XX_CDC_CORE_COMP0_B6_CTL (0xC4)
#define MSM89XX_CDC_CORE_COMP0_B6_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS (0xC8)
#define MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS__POR (0x03)
#define MSM89XX_CDC_CORE_COMP0_FS_CFG (0xCC)
#define MSM89XX_CDC_CORE_COMP0_FS_CFG__POR (0x03)
#define MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL (0xD0)
#define MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL__POR (0x02)
#define MSM89XX_CDC_CORE_DEBUG_DESER1_CTL (0xE0)
#define MSM89XX_CDC_CORE_DEBUG_DESER1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_DEBUG_DESER2_CTL (0xE4)
#define MSM89XX_CDC_CORE_DEBUG_DESER2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG (0xE8)
#define MSM89XX_CDC_CORE_DEBUG_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG (0xEC)
#define MSM89XX_CDC_CORE_DEBUG_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG (0xF0)
#define MSM89XX_CDC_CORE_DEBUG_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL (0x100)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL (0x140)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL (0x104)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL (0x144)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL (0x108)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL (0x148)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL (0x10C)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL (0x14C)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL (0x110)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL (0x150)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL (0x114)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL (0x154)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL (0x118)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL (0x158)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL (0x11C)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL (0x15C)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_CTL (0x120)
#define MSM89XX_CDC_CORE_IIR1_CTL__POR (0x40)
#define MSM89XX_CDC_CORE_IIR2_CTL (0x160)
#define MSM89XX_CDC_CORE_IIR2_CTL__POR (0x40)
#define MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL (0x124)
#define MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL (0x164)
#define MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL (0x128)
#define MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL (0x168)
#define MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL (0x12C)
#define MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL (0x16C)
#define MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX1_B1_CTL (0x180)
#define MSM89XX_CDC_CORE_CONN_RX1_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX1_B2_CTL (0x184)
#define MSM89XX_CDC_CORE_CONN_RX1_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX1_B3_CTL (0x188)
#define MSM89XX_CDC_CORE_CONN_RX1_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX2_B1_CTL (0x18C)
#define MSM89XX_CDC_CORE_CONN_RX2_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX2_B2_CTL (0x190)
#define MSM89XX_CDC_CORE_CONN_RX2_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX2_B3_CTL (0x194)
#define MSM89XX_CDC_CORE_CONN_RX2_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX3_B1_CTL (0x198)
#define MSM89XX_CDC_CORE_CONN_RX3_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX3_B2_CTL (0x19C)
#define MSM89XX_CDC_CORE_CONN_RX3_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_TX_B1_CTL (0x1A0)
#define MSM89XX_CDC_CORE_CONN_TX_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_TX_B2_CTL (0x1A4)
#define MSM89XX_CDC_CORE_CONN_TX_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL (0x1A8)
#define MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL (0x1AC)
#define MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL (0x1B0)
#define MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL (0x1B4)
#define MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL (0x1B8)
#define MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL (0x1BC)
#define MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL (0x1C0)
#define MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL (0x1C4)
#define MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL (0x1C8)
#define MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_TX_B3_CTL (0x1CC)
#define MSM89XX_CDC_CORE_CONN_TX_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER (0x1E0)
#define MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER__POR (0x00)
#define MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN (0x1E4)
#define MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN__POR (0x00)
#define MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG (0x1E8)
#define MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG__POR (0x00)
#define MSM89XX_CDC_CORE_TX5_MUX_CTL (0x1EC)
#define MSM89XX_CDC_CORE_TX5_MUX_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX5_CLK_FS_CTL (0x1F0)
#define MSM89XX_CDC_CORE_TX5_CLK_FS_CTL__POR (0x03)
#define MSM89XX_CDC_CORE_TX5_DMIC_CTL (0x1F4)
#define MSM89XX_CDC_CORE_TX5_DMIC_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER (0x280)
#define MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER__POR (0x00)
#define MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER (0x2A0)
#define MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER__POR (0x00)
#define MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER (0x2C0)
#define MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER__POR (0x00)
#define MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER (0x2E0)
#define MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER__POR (0x00)
#define MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN (0x284)
#define MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN__POR (0x00)
#define MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN (0x2A4)
#define MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN__POR (0x00)
#define MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN (0x2C4)
#define MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN__POR (0x00)
#define MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN (0x2E4)
#define MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN__POR (0x00)
#define MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG (0x288)
#define MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG__POR (0x00)
#define MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG (0x2A8)
#define MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG__POR (0x00)
#define MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG (0x2C8)
#define MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG__POR (0x00)
#define MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG (0x2E8)
#define MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG__POR (0x00)
#define MSM89XX_CDC_CORE_TX1_MUX_CTL (0x28C)
#define MSM89XX_CDC_CORE_TX1_MUX_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX2_MUX_CTL (0x2AC)
#define MSM89XX_CDC_CORE_TX2_MUX_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX3_MUX_CTL (0x2CC)
#define MSM89XX_CDC_CORE_TX3_MUX_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX4_MUX_CTL (0x2EC)
#define MSM89XX_CDC_CORE_TX4_MUX_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX1_CLK_FS_CTL (0x290)
#define MSM89XX_CDC_CORE_TX1_CLK_FS_CTL__POR (0x03)
#define MSM89XX_CDC_CORE_TX2_CLK_FS_CTL (0x2B0)
#define MSM89XX_CDC_CORE_TX2_CLK_FS_CTL__POR (0x03)
#define MSM89XX_CDC_CORE_TX3_CLK_FS_CTL (0x2D0)
#define MSM89XX_CDC_CORE_TX3_CLK_FS_CTL__POR (0x03)
#define MSM89XX_CDC_CORE_TX4_CLK_FS_CTL (0x2F0)
#define MSM89XX_CDC_CORE_TX4_CLK_FS_CTL__POR (0x03)
#define MSM89XX_CDC_CORE_TX1_DMIC_CTL (0x294)
#define MSM89XX_CDC_CORE_TX1_DMIC_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX2_DMIC_CTL (0x2B4)
#define MSM89XX_CDC_CORE_TX2_DMIC_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX3_DMIC_CTL (0x2D4)
#define MSM89XX_CDC_CORE_TX3_DMIC_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX4_DMIC_CTL (0x2F4)
#define MSM89XX_CDC_CORE_TX4_DMIC_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_NUM_REGISTERS \
(MSM89XX_CDC_CORE_TX4_DMIC_CTL+1)
#define MSM89XX_CDC_CORE_MAX_REGISTER \
(MSM89XX_CDC_CORE_NUM_REGISTERS-1)
#define MSM89XX_CDC_CORE_CACHE_SIZE \
MSM89XX_CDC_CORE_NUM_REGISTERS
#endif

10
asoc/codecs/wcd934x/Android.mk
View File

@@ -3,10 +3,6 @@
# Assume no targets will be supported # Assume no targets will be supported
# Check if this driver needs be built for current target # Check if this driver needs be built for current target
ifeq ($(call is-board-platform,sdm845),true)
AUDIO_SELECT := CONFIG_SND_SOC_SDM845=m
endif
ifeq ($(call is-board-platform,msmnile),true) ifeq ($(call is-board-platform,msmnile),true)
AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m
endif endif
@@ -15,13 +11,9 @@ ifeq ($(call is-board-platform,$(MSMSTEPPE) $(TRINKET)),true)
AUDIO_SELECT := CONFIG_SND_SOC_SM6150=m AUDIO_SELECT := CONFIG_SND_SOC_SM6150=m
endif endif
ifeq ($(call is-board-platform-in-list,msm8953 sdm670 qcs605),true)
AUDIO_SELECT := CONFIG_SND_SOC_SDM670=m
endif
AUDIO_CHIPSET := audio AUDIO_CHIPSET := audio
# Build/Package only in case of supported target # Build/Package only in case of supported target
ifeq ($(call is-board-platform-in-list,msm8953 sdm845 sdm670 qcs605 msmnile $(MSMSTEPPE) $(TRINKET)),true) ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET)),true)
LOCAL_PATH := $(call my-dir) LOCAL_PATH := $(call my-dir)

15
asoc/codecs/wcd934x/Kbuild
View File

@@ -16,21 +16,6 @@ ifeq ($(KERNEL_BUILD), 1)
endif endif
ifeq ($(KERNEL_BUILD), 0) ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SDM845), y)
include $(AUDIO_ROOT)/config/sdm845auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm845autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM670), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM450), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SM6150), y) ifeq ($(CONFIG_ARCH_SM6150), y)
include $(AUDIO_ROOT)/config/sm6150auto.conf include $(AUDIO_ROOT)/config/sm6150auto.conf
export export

50
asoc/codecs/wcd9360/Android.mk
View File

@@ -1,50 +0,0 @@
# Android makefile for audio kernel modules
# Assume no targets will be supported
# Check if this driver needs be built for current target
ifeq ($(call is-board-platform,msmnile),true)
AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m
endif
AUDIO_CHIPSET := audio
# Build/Package only in case of supported target
ifeq ($(call is-board-platform-in-list,msmnile),true)
LOCAL_PATH := $(call my-dir)
# This makefile is only for DLKM
ifneq ($(findstring vendor,$(LOCAL_PATH)),)
ifneq ($(findstring opensource,$(LOCAL_PATH)),)
AUDIO_BLD_DIR := $(shell pwd)/vendor/qcom/opensource/audio-kernel
endif # opensource
DLKM_DIR := $(TOP)/device/qcom/common/dlkm
# Build audio.ko as $(AUDIO_CHIPSET)_audio.ko
###########################################################
# This is set once per LOCAL_PATH, not per (kernel) module
KBUILD_OPTIONS := AUDIO_ROOT=$(AUDIO_BLD_DIR)
# We are actually building audio.ko here, as per the
# requirement we are specifying <chipset>_audio.ko as LOCAL_MODULE.
# This means we need to rename the module to <chipset>_audio.ko
# after audio.ko is built.
KBUILD_OPTIONS += MODNAME=wcd9360_dlkm
KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM)
KBUILD_OPTIONS += $(AUDIO_SELECT)
###########################################################
include $(CLEAR_VARS)
LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd9360.ko
LOCAL_MODULE_KBUILD_NAME := wcd9360_dlkm.ko
LOCAL_MODULE_TAGS := optional
LOCAL_MODULE_DEBUG_ENABLE := true
LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
include $(DLKM_DIR)/AndroidKernelModule.mk
###########################################################
###########################################################
endif # DLKM check
endif # supported target check

110
asoc/codecs/wcd9360/Kbuild
View File

@@ -1,110 +0,0 @@
# We can build either as part of a standalone Kernel build or as
# an external module. Determine which mechanism is being used
ifeq ($(MODNAME),)
KERNEL_BUILD := 1
else
KERNEL_BUILD := 0
endif
ifeq ($(KERNEL_BUILD), 1)
# These are configurable via Kconfig for kernel-based builds
# Need to explicitly configure for Android-based builds
AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-4.14
AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
endif
ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SM8150), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDMSHRIKE), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sm8150autoconf.h
endif
endif
# As per target team, build is done as follows:
# Defconfig : build with default flags
# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
# Perf : Using appropriate msmXXXX-perf_defconfig
#
# Shipment builds (user variants) should not have any debug feature
# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
# there is no other way to identify defconfig builds, QTI internal
# representation of perf builds (identified using the string 'perf'),
# is used to identify if the build is a slub or defconfig one. This
# way no critical debug feature will be enabled for perf and shipment
# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
# config.
############ UAPI ############
UAPI_DIR := uapi
UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
############ COMMON ############
COMMON_DIR := include
COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
############ WCD934X ############
# for WCD9360 Codec
ifdef CONFIG_SND_SOC_WCD9360
WCD9360_OBJS += wcd9360.o
WCD9360_OBJS += wcd9360-dsp-cntl.o
endif
LINUX_INC += -Iinclude/linux
INCS += $(COMMON_INC) \
$(UAPI_INC)
EXTRA_CFLAGS += $(INCS)
CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
-DANI_LITTLE_BIT_ENDIAN \
-DDOT11F_LITTLE_ENDIAN_HOST \
-DANI_COMPILER_TYPE_GCC \
-DANI_OS_TYPE_ANDROID=6 \
-DPTT_SOCK_SVC_ENABLE \
-Wall\
-Werror\
-D__linux__
KBUILD_CPPFLAGS += $(CDEFINES)
# Currently, for versions of gcc which support it, the kernel Makefile
# is disabling the maybe-uninitialized warning. Re-enable it for the
# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
# will override the kernel settings.
ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
EXTRA_CFLAGS += -Wmaybe-uninitialized
endif
#EXTRA_CFLAGS += -Wmissing-prototypes
ifeq ($(call cc-option-yn, -Wheader-guard),y)
EXTRA_CFLAGS += -Wheader-guard
endif
ifeq ($(KERNEL_BUILD), 0)
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
endif
# Module information used by KBuild framework
obj-$(CONFIG_SND_SOC_WCD9360) += wcd9360_dlkm.o
wcd9360_dlkm-y := $(WCD9360_OBJS)
# inject some build related information
DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

2231
asoc/codecs/wcd9360/wcd9360-defaults.h
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File diff suppressed because it is too large Load Diff

1357
asoc/codecs/wcd9360/wcd9360-dsp-cntl.c
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File diff suppressed because it is too large Load Diff

120
asoc/codecs/wcd9360/wcd9360-dsp-cntl.h
View File

@@ -1,120 +0,0 @@
/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __WCD9360_DSP_CNTL_H__
#define __WCD9360_DSP_CNTL_H__
#include <linux/miscdevice.h>
#include <sound/soc.h>
#include <sound/wcd-dsp-mgr.h>
enum cdc_ssr_event {
WCD_CDC_DOWN_EVENT,
WCD_CDC_UP_EVENT,
};
struct wcd_dsp_cdc_cb {
/* Callback to enable codec clock */
int (*cdc_clk_en)(struct snd_soc_codec *, bool);
/* Callback to vote and unvote for SVS2 mode */
void (*cdc_vote_svs)(struct snd_soc_codec *, bool);
};
struct wcd_dsp_irq_info {
/* IPC interrupt */
int cpe_ipc1_irq;
/* CPE error summary interrupt */
int cpe_err_irq;
/*
* Bit mask to indicate which of the
* error interrupts are to be considered
* as fatal.
*/
u16 fatal_irqs;
};
struct wcd_dsp_params {
struct wcd_dsp_cdc_cb *cb;
struct wcd_dsp_irq_info irqs;
/* Rate at which the codec clock operates */
u32 clk_rate;
/*
* Represents the dsp instance, will be used
* to create sysfs and debugfs entries with
* directory wdsp<dsp-instance>
*/
u32 dsp_instance;
};
struct wdsp_ssr_entry {
u8 offline;
u8 offline_change;
wait_queue_head_t offline_poll_wait;
struct snd_info_entry *entry;
};
struct wcd_dsp_cntl {
/* Handle to codec */
struct snd_soc_codec *codec;
/* Clk rate of the codec clock */
u32 clk_rate;
/* Callbacks to codec driver */
const struct wcd_dsp_cdc_cb *cdc_cb;
/* Completion to indicate WDSP boot done */
struct completion boot_complete;
struct wcd_dsp_irq_info irqs;
u32 dsp_instance;
/* Sysfs entries related */
int boot_reqs;
struct kobject wcd_kobj;
/* Debugfs related */
struct dentry *entry;
u32 debug_mode;
bool ramdump_enable;
/* WDSP manager drivers data */
struct device *m_dev;
struct wdsp_mgr_ops *m_ops;
/* clk related */
struct mutex clk_mutex;
bool is_clk_enabled;
/* Keep track of WDSP boot status */
bool is_wdsp_booted;
/* SSR related */
struct wdsp_ssr_entry ssr_entry;
struct mutex ssr_mutex;
/* Misc device related */
char miscdev_name[256];
struct miscdevice miscdev;
};
void wcd9360_dsp_cntl_init(struct snd_soc_codec *codec,
struct wcd_dsp_params *params,
struct wcd_dsp_cntl **cntl);
void wcd9360_dsp_cntl_deinit(struct wcd_dsp_cntl **cntl);
int wcd9360_dsp_ssr_event(struct wcd_dsp_cntl *cntl, enum cdc_ssr_event event);
#endif /* end __WCD_DSP_CONTROL_H__ */

56
asoc/codecs/wcd9360/wcd9360-irq.h
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@@ -1,56 +0,0 @@
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __WCD9360_IRQ_H_
#define __WCD9360_IRQ_H_
enum {
/* INTR_REG 0 */
WCD9360_IRQ_MISC = 1,
WCD9360_IRQ_RESERVED_0,
WCD9360_IRQ_LDO_RXTX_SCD,
WCD9360_IRQ_EAR_PA_SCD,
WCD9360_IRQ_AUX_PA_SCD,
WCD9360_IRQ_AUX_PA_CNP_COMPLETE,
WCD9360_IRQ_EAR_PA_CNP_COMPLETE,
/* INTR_REG 1 */
WCD9360_IRQ_RESERVED_1,
WCD9360_IRQ_RESERVED_2,
WCD9360_IRQ_RESERVED_3,
WCD9360_IRQ_RESERVED_4,
WCD9360_IRQ_RESERVED_5,
WCD9360_IRQ_RESERVED_6,
WCD9360_IRQ_RESERVED_7,
WCD9360_IRQ_RESERVED_8,
/* INTR_REG 2 */
WCD9360_IRQ_RESERVED_9,
WCD9360_IRQ_RESERVED_10,
WCD9360_IRQ_RESERVED_11,
WCD9360_IRQ_RESERVED_12,
WCD9360_IRQ_SOUNDWIRE,
WCD9360_IRQ_RESERVED_13,
WCD9360_IRQ_RCO_ERROR,
WCD9360_IRQ_CPE_ERROR,
/* INTR_REG 3 */
WCD9360_IRQ_MAD_AUDIO,
WCD9360_IRQ_MAD_BEACON,
WCD9360_IRQ_MAD_ULTRASOUND,
WCD9360_IRQ_RESERVED_14,
WCD9360_IRQ_RESERVED_15,
WCD9360_IRQ_CPE1_INTR,
WCD9360_IRQ_CPE2_INTR,
WCD9360_IRQ_CPE_LPASS_ACK,
WCD9360_NUM_IRQS,
};
#endif

110
asoc/codecs/wcd9360/wcd9360-regmap.c
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@@ -1,110 +0,0 @@
/*
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/regmap.h>
#include <linux/device.h>
#include <asoc/wcd9360-registers.h>
#include "../core.h"
#include "../wcd9xxx-regmap.h"
#include "wcd9360-defaults.h"
static bool wcd9360_is_readable_register(struct device *dev, unsigned int reg)
{
u8 pg_num, reg_offset;
const u8 *reg_tbl = NULL;
/*
* Get the page number from MSB of codec register. If its 0x80, assign
* the corresponding page index PAGE_0x80.
*/
pg_num = reg >> 8;
if (pg_num == 128)
pg_num = WCD9360_PAGE_128;
else if (pg_num == 80)
pg_num = WCD9360_PAGE_80;
else if (pg_num > 15)
return false;
reg_tbl = wcd9360_reg[pg_num];
reg_offset = reg & 0xFF;
if (reg_tbl && reg_tbl[reg_offset])
return true;
else
return false;
}
static bool wcd9360_is_volatile_register(struct device *dev, unsigned int reg)
{
u8 pg_num, reg_offset;
const u8 *reg_tbl = NULL;
pg_num = reg >> 8;
if (pg_num == 1 || pg_num == 2 ||
pg_num == 6 || pg_num == 7)
return true;
else if (pg_num == 128)
pg_num = WCD9360_PAGE_128;
else if (pg_num == 80)
pg_num = WCD9360_PAGE_80;
else if (pg_num > 15)
return false;
reg_tbl = wcd9360_reg[pg_num];
reg_offset = reg & 0xFF;
if (reg_tbl && reg_tbl[reg_offset] == WCD9360_RO)
return true;
if ((reg >= WCD9360_CODEC_RPM_RST_CTL) &&
(reg <= WCD9360_CHIP_TIER_CTRL_ALT_FUNC_EN))
return true;
if ((reg >= WCD9360_CDC_ANC0_IIR_COEFF_1_CTL) &&
(reg <= WCD9360_CDC_ANC0_FB_GAIN_CTL))
return true;
if ((reg >= WCD9360_CODEC_CPR_WR_DATA_0) &&
(reg <= WCD9360_CODEC_CPR_RD_DATA_3))
return true;
/*
* Need to mark volatile for registers that are writable but
* only few bits are read-only
*/
switch (reg) {
case WCD9360_CODEC_RPM_CLK_BYPASS:
case WCD9360_CODEC_RPM_CLK_GATE:
case WCD9360_CODEC_RPM_CLK_MCLK_CFG:
case WCD9360_CODEC_CPR_SVS_CX_VDD:
case WCD9360_CODEC_CPR_SVS2_CX_VDD:
case WCD9360_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL:
case WCD9360_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL:
return true;
}
return false;
}
struct regmap_config wcd9360_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = wcd9360_defaults,
.num_reg_defaults = ARRAY_SIZE(wcd9360_defaults),
.max_register = WCD9360_MAX_REGISTER,
.volatile_reg = wcd9360_is_volatile_register,
.readable_reg = wcd9360_is_readable_register,
.can_multi_write = true,
};

882
asoc/codecs/wcd9360/wcd9360-routing.h
View File

@@ -1,882 +0,0 @@
/*
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __WCD9360_ROUTING_H__
#define __WCD9360_ROUTING_H__
#include <sound/soc-dapm.h>
const struct snd_soc_dapm_route pahu_slim_audio_map[] = {
{"AIF4 MAD", NULL, "AIF4_MAD Mixer"},
/* Virtual input widget Mixer SLIMBUS */
{"AIF1_CAP Mixer", "SLIM TX0", "SLIM TX0"},
{"AIF1_CAP Mixer", "SLIM TX1", "SLIM TX1"},
{"AIF1_CAP Mixer", "SLIM TX2", "SLIM TX2"},
{"AIF1_CAP Mixer", "SLIM TX3", "SLIM TX3"},
{"AIF1_CAP Mixer", "SLIM TX4", "SLIM TX4"},
{"AIF1_CAP Mixer", "SLIM TX5", "SLIM TX5"},
{"AIF1_CAP Mixer", "SLIM TX6", "SLIM TX6"},
{"AIF1_CAP Mixer", "SLIM TX7", "SLIM TX7"},
{"AIF1_CAP Mixer", "SLIM TX8", "SLIM TX8"},
{"AIF1_CAP Mixer", "SLIM TX9", "SLIM TX9"},
{"AIF1_CAP Mixer", "SLIM TX10", "SLIM TX10"},
{"AIF1_CAP Mixer", "SLIM TX11", "SLIM TX11"},
{"AIF1_CAP Mixer", "SLIM TX13", "SLIM TX13"},
{"AIF2_CAP Mixer", "SLIM TX0", "SLIM TX0"},
{"AIF2_CAP Mixer", "SLIM TX1", "SLIM TX1"},
{"AIF2_CAP Mixer", "SLIM TX2", "SLIM TX2"},
{"AIF2_CAP Mixer", "SLIM TX3", "SLIM TX3"},
{"AIF2_CAP Mixer", "SLIM TX4", "SLIM TX4"},
{"AIF2_CAP Mixer", "SLIM TX5", "SLIM TX5"},
{"AIF2_CAP Mixer", "SLIM TX6", "SLIM TX6"},
{"AIF2_CAP Mixer", "SLIM TX7", "SLIM TX7"},
{"AIF2_CAP Mixer", "SLIM TX8", "SLIM TX8"},
{"AIF2_CAP Mixer", "SLIM TX9", "SLIM TX9"},
{"AIF2_CAP Mixer", "SLIM TX10", "SLIM TX10"},
{"AIF2_CAP Mixer", "SLIM TX11", "SLIM TX11"},
{"AIF2_CAP Mixer", "SLIM TX13", "SLIM TX13"},
{"AIF3_CAP Mixer", "SLIM TX0", "SLIM TX0"},
{"AIF3_CAP Mixer", "SLIM TX1", "SLIM TX1"},
{"AIF3_CAP Mixer", "SLIM TX2", "SLIM TX2"},
{"AIF3_CAP Mixer", "SLIM TX3", "SLIM TX3"},
{"AIF3_CAP Mixer", "SLIM TX4", "SLIM TX4"},
{"AIF3_CAP Mixer", "SLIM TX5", "SLIM TX5"},
{"AIF3_CAP Mixer", "SLIM TX6", "SLIM TX6"},
{"AIF3_CAP Mixer", "SLIM TX7", "SLIM TX7"},
{"AIF3_CAP Mixer", "SLIM TX8", "SLIM TX8"},
{"AIF3_CAP Mixer", "SLIM TX9", "SLIM TX9"},
{"AIF3_CAP Mixer", "SLIM TX10", "SLIM TX10"},
{"AIF3_CAP Mixer", "SLIM TX11", "SLIM TX11"},
{"AIF3_CAP Mixer", "SLIM TX13", "SLIM TX13"},
{"AIF4_MAD Mixer", "SLIM TX13", "SLIM TX13"},
/* CDC Tx interface with SLIMBUS */
{"SLIM TX0", NULL, "CDC_IF TX0 MUX"},
{"SLIM TX1", NULL, "CDC_IF TX1 MUX"},
{"SLIM TX2", NULL, "CDC_IF TX2 MUX"},
{"SLIM TX3", NULL, "CDC_IF TX3 MUX"},
{"SLIM TX4", NULL, "CDC_IF TX4 MUX"},
{"SLIM TX5", NULL, "CDC_IF TX5 MUX"},
{"SLIM TX6", NULL, "CDC_IF TX6 MUX"},
{"SLIM TX7", NULL, "CDC_IF TX7 MUX"},
{"SLIM TX8", NULL, "CDC_IF TX8 MUX"},
{"SLIM TX9", NULL, "CDC_IF TX9 MUX"},
{"SLIM TX10", NULL, "CDC_IF TX10 MUX2"},
{"SLIM TX11", NULL, "CDC_IF TX11 MUX2"},
{"SLIM TX13", NULL, "CDC_IF TX13 MUX"},
{"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
{"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
{"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
{"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
{"SLIM RX0", NULL, "SLIM RX0 MUX"},
{"SLIM RX1", NULL, "SLIM RX1 MUX"},
{"SLIM RX2", NULL, "SLIM RX2 MUX"},
{"SLIM RX3", NULL, "SLIM RX3 MUX"},
{"SLIM RX4", NULL, "SLIM RX4 MUX"},
{"SLIM RX5", NULL, "SLIM RX5 MUX"},
{"SLIM RX6", NULL, "SLIM RX6 MUX"},
{"SLIM RX7", NULL, "SLIM RX7 MUX"},
/* CDC Rx interface with SLIMBUS */
{"CDC_IF RX0 MUX", "SLIM RX0", "SLIM RX0"},
{"CDC_IF RX1 MUX", "SLIM RX1", "SLIM RX1"},
{"CDC_IF RX2 MUX", "SLIM RX2", "SLIM RX2"},
{"CDC_IF RX3 MUX", "SLIM RX3", "SLIM RX3"},
{"CDC_IF RX4 MUX", "SLIM RX4", "SLIM RX4"},
{"CDC_IF RX5 MUX", "SLIM RX5", "SLIM RX5"},
{"CDC_IF RX6 MUX", "SLIM RX6", "SLIM RX6"},
{"CDC_IF RX7 MUX", "SLIM RX7", "SLIM RX7"},
/* VI Feedback */
{"AIF4_VI Mixer", "SPKR_VI_1", "VIINPUT"},
{"AIF4_VI Mixer", "SPKR_VI_2", "VIINPUT"},
{"AIF4 VI", NULL, "AIF4_VI Mixer"},
};
const struct snd_soc_dapm_route pahu_audio_map[] = {
/* Virtual input widgets */
{"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
{"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
{"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
/* WDMA3 */
{"WDMA3 PORT0 MUX", "DEC0", "ADC MUX0"},
{"WDMA3 PORT0 MUX", "RX_MIX_TX0", "RX MIX TX0 MUX"},
{"WDMA3 PORT1 MUX", "DEC1", "ADC MUX1"},
{"WDMA3 PORT1 MUX", "RX_MIX_TX1", "RX MIX TX1 MUX"},
{"WDMA3 PORT2 MUX", "DEC2", "ADC MUX2"},
{"WDMA3 PORT2 MUX", "RX_MIX_TX2", "RX MIX TX2 MUX"},
{"WDMA3 PORT3 MUX", "DEC3", "ADC MUX3"},
{"WDMA3 PORT3 MUX", "RX_MIX_TX3", "RX MIX TX3 MUX"},
{"WDMA3 PORT4 MUX", "DEC4", "ADC MUX4"},
{"WDMA3 PORT4 MUX", "RX_MIX_TX4", "RX MIX TX4 MUX"},
{"WDMA3 PORT5 MUX", "DEC5", "ADC MUX5"},
{"WDMA3 PORT5 MUX", "RX_MIX_TX5", "RX MIX TX5 MUX"},
{"WDMA3 PORT6 MUX", "DEC6", "ADC MUX6"},
{"WDMA3 PORT6 MUX", "RX_MIX_TX6", "RX MIX TX6 MUX"},
{"WDMA3 CH0 MUX", "PORT_0", "WDMA3 PORT0 MUX"},
{"WDMA3 CH0 MUX", "PORT_1", "WDMA3 PORT1 MUX"},
{"WDMA3 CH0 MUX", "PORT_2", "WDMA3 PORT2 MUX"},
{"WDMA3 CH0 MUX", "PORT_3", "WDMA3 PORT3 MUX"},
{"WDMA3 CH0 MUX", "PORT_4", "WDMA3 PORT4 MUX"},
{"WDMA3 CH0 MUX", "PORT_5", "WDMA3 PORT5 MUX"},
{"WDMA3 CH0 MUX", "PORT_6", "WDMA3 PORT6 MUX"},
{"WDMA3 CH0 MUX", "PORT_7", "ADC MUX7"},
{"WDMA3 CH0 MUX", "PORT_8", "ADC MUX8"},
{"WDMA3 CH1 MUX", "PORT_0", "WDMA3 PORT0 MUX"},
{"WDMA3 CH1 MUX", "PORT_1", "WDMA3 PORT1 MUX"},
{"WDMA3 CH1 MUX", "PORT_2", "WDMA3 PORT2 MUX"},
{"WDMA3 CH1 MUX", "PORT_3", "WDMA3 PORT3 MUX"},
{"WDMA3 CH1 MUX", "PORT_4", "WDMA3 PORT4 MUX"},
{"WDMA3 CH1 MUX", "PORT_5", "WDMA3 PORT5 MUX"},
{"WDMA3 CH1 MUX", "PORT_6", "WDMA3 PORT6 MUX"},
{"WDMA3 CH1 MUX", "PORT_7", "ADC MUX7"},
{"WDMA3 CH1 MUX", "PORT_8", "ADC MUX8"},
{"WDMA3 CH2 MUX", "PORT_0", "WDMA3 PORT0 MUX"},
{"WDMA3 CH2 MUX", "PORT_1", "WDMA3 PORT1 MUX"},
{"WDMA3 CH2 MUX", "PORT_2", "WDMA3 PORT2 MUX"},
{"WDMA3 CH2 MUX", "PORT_3", "WDMA3 PORT3 MUX"},
{"WDMA3 CH2 MUX", "PORT_4", "WDMA3 PORT4 MUX"},
{"WDMA3 CH2 MUX", "PORT_5", "WDMA3 PORT5 MUX"},
{"WDMA3 CH2 MUX", "PORT_6", "WDMA3 PORT6 MUX"},
{"WDMA3 CH2 MUX", "PORT_7", "ADC MUX7"},
{"WDMA3 CH2 MUX", "PORT_8", "ADC MUX8"},
{"WDMA3 CH3 MUX", "PORT_0", "WDMA3 PORT0 MUX"},
{"WDMA3 CH3 MUX", "PORT_1", "WDMA3 PORT1 MUX"},
{"WDMA3 CH3 MUX", "PORT_2", "WDMA3 PORT2 MUX"},
{"WDMA3 CH3 MUX", "PORT_3", "WDMA3 PORT3 MUX"},
{"WDMA3 CH3 MUX", "PORT_4", "WDMA3 PORT4 MUX"},
{"WDMA3 CH3 MUX", "PORT_5", "WDMA3 PORT5 MUX"},
{"WDMA3 CH3 MUX", "PORT_6", "WDMA3 PORT6 MUX"},
{"WDMA3 CH3 MUX", "PORT_7", "ADC MUX7"},
{"WDMA3 CH3 MUX", "PORT_8", "ADC MUX8"},
{"WDMA3_CH_MIXER", NULL, "WDMA3 CH0 MUX"},
{"WDMA3_CH_MIXER", NULL, "WDMA3 CH1 MUX"},
{"WDMA3_CH_MIXER", NULL, "WDMA3 CH2 MUX"},
{"WDMA3_CH_MIXER", NULL, "WDMA3 CH3 MUX"},
{"WDMA3_ON_OFF", "Switch", "WDMA3_CH_MIXER"},
{"WDMA3_OUT", NULL, "WDMA3_ON_OFF"},
/* MAD */
{"MAD_SEL MUX", "SPE", "MAD_CPE_INPUT"},
{"MAD_SEL MUX", "MSM", "MADINPUT"},
{"MAD_INP MUX", "MAD", "MAD_SEL MUX"},
{"MAD_INP MUX", "DEC1", "ADC MUX1"},
{"MAD_BROADCAST", "Switch", "MAD_INP MUX"},
{"MAD_CPE1", "Switch", "MAD_INP MUX"},
{"MAD_CPE2", "Switch", "MAD_INP MUX"},
{"MAD_CPE_OUT1", NULL, "MAD_CPE1"},
{"MAD_CPE_OUT2", NULL, "MAD_CPE2"},
{"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
{"CDC_IF TX0 MUX", "RX_MIX_TX0", "RX MIX TX0 MUX"},
{"CDC_IF TX0 MUX", "DEC0_192", "ADC US MUX0"},
{"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
{"CDC_IF TX1 MUX", "RX_MIX_TX1", "RX MIX TX1 MUX"},
{"CDC_IF TX1 MUX", "DEC1_192", "ADC US MUX1"},
{"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
{"CDC_IF TX2 MUX", "RX_MIX_TX2", "RX MIX TX2 MUX"},
{"CDC_IF TX2 MUX", "DEC2_192", "ADC US MUX2"},
{"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
{"CDC_IF TX3 MUX", "RX_MIX_TX3", "RX MIX TX3 MUX"},
{"CDC_IF TX3 MUX", "DEC3_192", "ADC US MUX3"},
{"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
{"CDC_IF TX4 MUX", "RX_MIX_TX4", "RX MIX TX4 MUX"},
{"CDC_IF TX4 MUX", "DEC4_192", "ADC US MUX4"},
{"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
{"CDC_IF TX5 MUX", "RX_MIX_TX5", "RX MIX TX5 MUX"},
{"CDC_IF TX5 MUX", "DEC5_192", "ADC US MUX5"},
{"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
{"CDC_IF TX6 MUX", "RX_MIX_TX6", "RX MIX TX6 MUX"},
{"CDC_IF TX6 MUX", "DEC6_192", "ADC US MUX6"},
{"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
{"CDC_IF TX7 MUX", "RX_MIX_TX7", "RX MIX TX7 MUX"},
{"CDC_IF TX7 MUX", "DEC7_192", "ADC US MUX7"},
{"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
{"CDC_IF TX8 MUX", "RX_MIX_TX8", "RX MIX TX8 MUX"},
{"CDC_IF TX8 MUX", "DEC8_192", "ADC US MUX8"},
{"CDC_IF TX9 MUX", "DEC7", "ADC MUX7"},
{"CDC_IF TX9 MUX", "DEC7_192", "ADC US MUX7"},
{"CDC_IF TX10 MUX", "DEC6", "ADC MUX6"},
{"CDC_IF TX10 MUX", "DEC6_192", "ADC US MUX6"},
{"CDC_IF TX10 MUX2", "TX10_MUX1", "CDC_IF TX10 MUX"},
{"CDC_IF TX11 MUX2", "TX11_MUX1", "CDC_IF TX11 MUX"},
{"CDC_IF TX11 MUX", "DEC_0_5", "CDC_IF TX11 INP1 MUX"},
{"CDC_IF TX11 MUX", "DEC_9_12", "CDC_IF TX11 INP1 MUX"},
{"CDC_IF TX11 INP1 MUX", "DEC0", "ADC MUX0"},
{"CDC_IF TX11 INP1 MUX", "DEC1", "ADC MUX1"},
{"CDC_IF TX11 INP1 MUX", "DEC2", "ADC MUX2"},
{"CDC_IF TX11 INP1 MUX", "DEC3", "ADC MUX3"},
{"CDC_IF TX11 INP1 MUX", "DEC4", "ADC MUX4"},
{"CDC_IF TX11 INP1 MUX", "DEC5", "ADC MUX5"},
{"CDC_IF TX11 INP1 MUX", "RX_MIX_TX5", "RX MIX TX5 MUX"},
{"CDC_IF TX13 MUX", "MAD_BRDCST", "MAD_BROADCAST"},
{"CDC_IF TX13 MUX", "CDC_DEC_5", "CDC_IF TX13 INP1 MUX"},
{"CDC_IF TX13 INP1 MUX", "DEC5", "ADC MUX5"},
{"CDC_IF TX13 INP1 MUX", "DEC5_192", "ADC US MUX5"},
{"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
{"RX MIX TX0 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
{"RX MIX TX0 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
{"RX MIX TX0 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
{"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
{"RX MIX TX1 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
{"RX MIX TX1 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
{"RX MIX TX1 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
{"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
{"RX MIX TX2 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
{"RX MIX TX2 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
{"RX MIX TX2 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
{"RX MIX TX3 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
{"RX MIX TX3 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
{"RX MIX TX3 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
{"RX MIX TX3 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
{"RX MIX TX4 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
{"RX MIX TX4 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
{"RX MIX TX4 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
{"RX MIX TX4 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
{"RX MIX TX5 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
{"RX MIX TX5 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
{"RX MIX TX5 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
{"RX MIX TX5 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
{"RX MIX TX6 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
{"RX MIX TX6 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
{"RX MIX TX6 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
{"RX MIX TX6 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
{"RX MIX TX7 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
{"RX MIX TX7 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
{"RX MIX TX7 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
{"RX MIX TX7 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
{"RX MIX TX8 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
{"RX MIX TX8 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
{"RX MIX TX8 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
{"RX MIX TX8 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
{"ADC US MUX0", "US_Switch", "ADC MUX0"},
{"ADC US MUX1", "US_Switch", "ADC MUX1"},
{"ADC US MUX2", "US_Switch", "ADC MUX2"},
{"ADC US MUX3", "US_Switch", "ADC MUX3"},
{"ADC US MUX4", "US_Switch", "ADC MUX4"},
{"ADC US MUX5", "US_Switch", "ADC MUX5"},
{"ADC US MUX6", "US_Switch", "ADC MUX6"},
{"ADC US MUX7", "US_Switch", "ADC MUX7"},
{"ADC US MUX8", "US_Switch", "ADC MUX8"},
{"ADC MUX0", "DMIC", "DMIC MUX0"},
{"ADC MUX0", "AMIC", "AMIC MUX0"},
{"ADC MUX1", "DMIC", "DMIC MUX1"},
{"ADC MUX1", "AMIC", "AMIC MUX1"},
{"ADC MUX2", "DMIC", "DMIC MUX2"},
{"ADC MUX2", "AMIC", "AMIC MUX2"},
{"ADC MUX3", "DMIC", "DMIC MUX3"},
{"ADC MUX3", "AMIC", "AMIC MUX3"},
{"ADC MUX4", "DMIC", "DMIC MUX4"},
{"ADC MUX4", "AMIC", "AMIC MUX4"},
{"ADC MUX5", "DMIC", "DMIC MUX5"},
{"ADC MUX5", "AMIC", "AMIC MUX5"},
{"ADC MUX6", "DMIC", "DMIC MUX6"},
{"ADC MUX6", "AMIC", "AMIC MUX6"},
{"ADC MUX7", "DMIC", "DMIC MUX7"},
{"ADC MUX7", "AMIC", "AMIC MUX7"},
{"ADC MUX8", "DMIC", "DMIC MUX8"},
{"ADC MUX8", "AMIC", "AMIC MUX8"},
{"ADC MUX10", "DMIC", "DMIC MUX10"},
{"ADC MUX10", "AMIC", "AMIC MUX10"},
{"ADC MUX11", "DMIC", "DMIC MUX11"},
{"ADC MUX11", "AMIC", "AMIC MUX11"},
{"ADC MUX0", "ANC_FB_TUNE1", "ADC MUX10"},
{"ADC MUX0", "ANC_FB_TUNE1", "ADC MUX11"},
{"ADC MUX1", "ANC_FB_TUNE1", "ADC MUX10"},
{"ADC MUX1", "ANC_FB_TUNE1", "ADC MUX11"},
{"ADC MUX2", "ANC_FB_TUNE1", "ADC MUX10"},
{"ADC MUX2", "ANC_FB_TUNE1", "ADC MUX11"},
{"ADC MUX3", "ANC_FB_TUNE1", "ADC MUX10"},
{"ADC MUX3", "ANC_FB_TUNE1", "ADC MUX11"},
{"ADC MUX4", "ANC_FB_TUNE1", "ADC MUX10"},
{"ADC MUX4", "ANC_FB_TUNE1", "ADC MUX11"},
{"ADC MUX5", "ANC_FB_TUNE1", "ADC MUX10"},
{"ADC MUX5", "ANC_FB_TUNE1", "ADC MUX11"},
{"ADC MUX6", "ANC_FB_TUNE1", "ADC MUX10"},
{"ADC MUX6", "ANC_FB_TUNE1", "ADC MUX11"},
{"ADC MUX7", "ANC_FB_TUNE1", "ADC MUX10"},
{"ADC MUX7", "ANC_FB_TUNE1", "ADC MUX11"},
{"ADC MUX8", "ANC_FB_TUNE1", "ADC MUX10"},
{"ADC MUX8", "ANC_FB_TUNE1", "ADC MUX11"},
{"DMIC MUX0", "DMIC0", "DMIC0"},
{"DMIC MUX0", "DMIC1", "DMIC1"},
{"DMIC MUX0", "DMIC2", "DMIC2"},
{"DMIC MUX0", "DMIC3", "DMIC3"},
{"DMIC MUX0", "DMIC4", "DMIC4"},
{"DMIC MUX0", "DMIC5", "DMIC5"},
{"DMIC MUX0", "DMIC6", "DMIC6"},
{"DMIC MUX0", "DMIC7", "DMIC7"},
{"AMIC MUX0", "ADC1", "ADC1"},
{"AMIC MUX0", "ADC2", "ADC2"},
{"AMIC MUX0", "ADC3", "ADC3"},
{"AMIC MUX0", "ADC4", "ADC4"},
{"DMIC MUX1", "DMIC0", "DMIC0"},
{"DMIC MUX1", "DMIC1", "DMIC1"},
{"DMIC MUX1", "DMIC2", "DMIC2"},
{"DMIC MUX1", "DMIC3", "DMIC3"},
{"DMIC MUX1", "DMIC4", "DMIC4"},
{"DMIC MUX1", "DMIC5", "DMIC5"},
{"DMIC MUX1", "DMIC6", "DMIC6"},
{"DMIC MUX1", "DMIC7", "DMIC7"},
{"AMIC MUX1", "ADC1", "ADC1"},
{"AMIC MUX1", "ADC2", "ADC2"},
{"AMIC MUX1", "ADC3", "ADC3"},
{"AMIC MUX1", "ADC4", "ADC4"},
{"DMIC MUX2", "DMIC0", "DMIC0"},
{"DMIC MUX2", "DMIC1", "DMIC1"},
{"DMIC MUX2", "DMIC2", "DMIC2"},
{"DMIC MUX2", "DMIC3", "DMIC3"},
{"DMIC MUX2", "DMIC4", "DMIC4"},
{"DMIC MUX2", "DMIC5", "DMIC5"},
{"DMIC MUX2", "DMIC6", "DMIC6"},
{"DMIC MUX2", "DMIC7", "DMIC7"},
{"AMIC MUX2", "ADC1", "ADC1"},
{"AMIC MUX2", "ADC2", "ADC2"},
{"AMIC MUX2", "ADC3", "ADC3"},
{"AMIC MUX2", "ADC4", "ADC4"},
{"DMIC MUX3", "DMIC0", "DMIC0"},
{"DMIC MUX3", "DMIC1", "DMIC1"},
{"DMIC MUX3", "DMIC2", "DMIC2"},
{"DMIC MUX3", "DMIC3", "DMIC3"},
{"DMIC MUX3", "DMIC4", "DMIC4"},
{"DMIC MUX3", "DMIC5", "DMIC5"},
{"DMIC MUX3", "DMIC6", "DMIC6"},
{"DMIC MUX3", "DMIC7", "DMIC7"},
{"AMIC MUX3", "ADC1", "ADC1"},
{"AMIC MUX3", "ADC2", "ADC2"},
{"AMIC MUX3", "ADC3", "ADC3"},
{"AMIC MUX3", "ADC4", "ADC4"},
{"DMIC MUX4", "DMIC0", "DMIC0"},
{"DMIC MUX4", "DMIC1", "DMIC1"},
{"DMIC MUX4", "DMIC2", "DMIC2"},
{"DMIC MUX4", "DMIC3", "DMIC3"},
{"DMIC MUX4", "DMIC4", "DMIC4"},
{"DMIC MUX4", "DMIC5", "DMIC5"},
{"DMIC MUX4", "DMIC6", "DMIC6"},
{"DMIC MUX4", "DMIC7", "DMIC7"},
{"AMIC MUX4", "ADC1", "ADC1"},
{"AMIC MUX4", "ADC2", "ADC2"},
{"AMIC MUX4", "ADC3", "ADC3"},
{"AMIC MUX4", "ADC4", "ADC4"},
{"DMIC MUX5", "DMIC0", "DMIC0"},
{"DMIC MUX5", "DMIC1", "DMIC1"},
{"DMIC MUX5", "DMIC2", "DMIC2"},
{"DMIC MUX5", "DMIC3", "DMIC3"},
{"DMIC MUX5", "DMIC4", "DMIC4"},
{"DMIC MUX5", "DMIC5", "DMIC5"},
{"DMIC MUX5", "DMIC6", "DMIC6"},
{"DMIC MUX5", "DMIC7", "DMIC7"},
{"AMIC MUX5", "ADC1", "ADC1"},
{"AMIC MUX5", "ADC2", "ADC2"},
{"AMIC MUX5", "ADC3", "ADC3"},
{"AMIC MUX5", "ADC4", "ADC4"},
{"DMIC MUX6", "DMIC0", "DMIC0"},
{"DMIC MUX6", "DMIC1", "DMIC1"},
{"DMIC MUX6", "DMIC2", "DMIC2"},
{"DMIC MUX6", "DMIC3", "DMIC3"},
{"DMIC MUX6", "DMIC4", "DMIC4"},
{"DMIC MUX6", "DMIC5", "DMIC5"},
{"DMIC MUX6", "DMIC6", "DMIC6"},
{"DMIC MUX6", "DMIC7", "DMIC7"},
{"AMIC MUX6", "ADC1", "ADC1"},
{"AMIC MUX6", "ADC2", "ADC2"},
{"AMIC MUX6", "ADC3", "ADC3"},
{"AMIC MUX6", "ADC4", "ADC4"},
{"DMIC MUX7", "DMIC0", "DMIC0"},
{"DMIC MUX7", "DMIC1", "DMIC1"},
{"DMIC MUX7", "DMIC2", "DMIC2"},
{"DMIC MUX7", "DMIC3", "DMIC3"},
{"DMIC MUX7", "DMIC4", "DMIC4"},
{"DMIC MUX7", "DMIC5", "DMIC5"},
{"DMIC MUX7", "DMIC6", "DMIC6"},
{"DMIC MUX7", "DMIC7", "DMIC7"},
{"AMIC MUX7", "ADC1", "ADC1"},
{"AMIC MUX7", "ADC2", "ADC2"},
{"AMIC MUX7", "ADC3", "ADC3"},
{"AMIC MUX7", "ADC4", "ADC4"},
{"DMIC MUX8", "DMIC0", "DMIC0"},
{"DMIC MUX8", "DMIC1", "DMIC1"},
{"DMIC MUX8", "DMIC2", "DMIC2"},
{"DMIC MUX8", "DMIC3", "DMIC3"},
{"DMIC MUX8", "DMIC4", "DMIC4"},
{"DMIC MUX8", "DMIC5", "DMIC5"},
{"DMIC MUX8", "DMIC6", "DMIC6"},
{"DMIC MUX8", "DMIC7", "DMIC7"},
{"AMIC MUX8", "ADC1", "ADC1"},
{"AMIC MUX8", "ADC2", "ADC2"},
{"AMIC MUX8", "ADC3", "ADC3"},
{"AMIC MUX8", "ADC4", "ADC4"},
{"DMIC MUX10", "DMIC0", "DMIC0"},
{"DMIC MUX10", "DMIC1", "DMIC1"},
{"DMIC MUX10", "DMIC2", "DMIC2"},
{"DMIC MUX10", "DMIC3", "DMIC3"},
{"DMIC MUX10", "DMIC4", "DMIC4"},
{"DMIC MUX10", "DMIC5", "DMIC5"},
{"DMIC MUX10", "DMIC6", "DMIC6"},
{"DMIC MUX10", "DMIC7", "DMIC7"},
{"AMIC MUX10", "ADC1", "ADC1"},
{"AMIC MUX10", "ADC2", "ADC2"},
{"AMIC MUX10", "ADC3", "ADC3"},
{"AMIC MUX10", "ADC4", "ADC4"},
{"DMIC MUX11", "DMIC0", "DMIC0"},
{"DMIC MUX11", "DMIC1", "DMIC1"},
{"DMIC MUX11", "DMIC2", "DMIC2"},
{"DMIC MUX11", "DMIC3", "DMIC3"},
{"DMIC MUX11", "DMIC4", "DMIC4"},
{"DMIC MUX11", "DMIC5", "DMIC5"},
{"DMIC MUX11", "DMIC6", "DMIC6"},
{"DMIC MUX11", "DMIC7", "DMIC7"},
{"AMIC MUX11", "ADC1", "ADC1"},
{"AMIC MUX11", "ADC2", "ADC2"},
{"AMIC MUX11", "ADC3", "ADC3"},
{"AMIC MUX11", "ADC4", "ADC4"},
{"ADC2_IN", "AMIC1", "AMIC1"},
{"ADC2_IN", "AMIC2", "AMIC2"},
{"ADC4_IN", "AMIC3", "AMIC3"},
{"ADC4_IN", "AMIC4", "AMIC4"},
{"ADC1", NULL, "AMIC1"},
{"ADC2", NULL, "ADC2_IN"},
{"ADC3", NULL, "AMIC3"},
{"ADC4", NULL, "ADC4_IN"},
{"ADC1", NULL, "LDO_RXTX"},
{"ADC2", NULL, "LDO_RXTX"},
{"ADC3", NULL, "LDO_RXTX"},
{"ADC4", NULL, "LDO_RXTX"},
{"RX INT0_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
{"RX INT0_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
{"RX INT0_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
{"RX INT0_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
{"RX INT0_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
{"RX INT0_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
{"RX INT0_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
{"RX INT0_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
{"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
{"RX INT0_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
{"RX INT0_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
{"RX INT0_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
{"RX INT0_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
{"RX INT0_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
{"RX INT0_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
{"RX INT0_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
{"RX INT0_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
{"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
{"RX INT0_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
{"RX INT0_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
{"RX INT0_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
{"RX INT0_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
{"RX INT0_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
{"RX INT0_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
{"RX INT0_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
{"RX INT0_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
{"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
{"RX INT7_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
{"RX INT7_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
{"RX INT7_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
{"RX INT7_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
{"RX INT7_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
{"RX INT7_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
{"RX INT7_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
{"RX INT7_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
{"RX INT7_1 MIX1 INP0", "IIR0", "IIR0"},
{"RX INT7_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
{"RX INT7_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
{"RX INT7_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
{"RX INT7_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
{"RX INT7_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
{"RX INT7_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
{"RX INT7_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
{"RX INT7_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
{"RX INT7_1 MIX1 INP1", "IIR0", "IIR0"},
{"RX INT7_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
{"RX INT7_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
{"RX INT7_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
{"RX INT7_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
{"RX INT7_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
{"RX INT7_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
{"RX INT7_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
{"RX INT7_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
{"RX INT7_1 MIX1 INP2", "IIR0", "IIR0"},
{"RX INT8_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
{"RX INT8_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
{"RX INT8_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
{"RX INT8_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
{"RX INT8_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
{"RX INT8_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
{"RX INT8_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
{"RX INT8_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
{"RX INT8_1 MIX1 INP0", "IIR0", "IIR0"},
{"RX INT8_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
{"RX INT8_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
{"RX INT8_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
{"RX INT8_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
{"RX INT8_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
{"RX INT8_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
{"RX INT8_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
{"RX INT8_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
{"RX INT8_1 MIX1 INP1", "IIR0", "IIR0"},
{"RX INT8_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
{"RX INT8_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
{"RX INT8_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
{"RX INT8_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
{"RX INT8_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
{"RX INT8_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
{"RX INT8_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
{"RX INT8_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
{"RX INT8_1 MIX1 INP2", "IIR0", "IIR0"},
{"RX INT9_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
{"RX INT9_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
{"RX INT9_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
{"RX INT9_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
{"RX INT9_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
{"RX INT9_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
{"RX INT9_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
{"RX INT9_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
{"RX INT9_1 MIX1 INP0", "IIR0", "IIR0"},
{"RX INT9_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
{"RX INT9_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
{"RX INT9_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
{"RX INT9_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
{"RX INT9_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
{"RX INT9_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
{"RX INT9_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
{"RX INT9_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
{"RX INT9_1 MIX1 INP1", "IIR0", "IIR0"},
{"RX INT9_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
{"RX INT9_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
{"RX INT9_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
{"RX INT9_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
{"RX INT9_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
{"RX INT9_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
{"RX INT9_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
{"RX INT9_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
{"RX INT9_1 MIX1 INP2", "IIR0", "IIR0"},
{"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"},
{"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"},
{"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"},
{"RX INT7_1 MIX1", NULL, "RX INT7_1 MIX1 INP0"},
{"RX INT7_1 MIX1", NULL, "RX INT7_1 MIX1 INP1"},
{"RX INT7_1 MIX1", NULL, "RX INT7_1 MIX1 INP2"},
{"RX INT8_1 MIX1", NULL, "RX INT8_1 MIX1 INP0"},
{"RX INT8_1 MIX1", NULL, "RX INT8_1 MIX1 INP1"},
{"RX INT8_1 MIX1", NULL, "RX INT8_1 MIX1 INP2"},
{"RX INT9_1 MIX1", NULL, "RX INT9_1 MIX1 INP0"},
{"RX INT9_1 MIX1", NULL, "RX INT9_1 MIX1 INP1"},
{"RX INT9_1 MIX1", NULL, "RX INT9_1 MIX1 INP2"},
/* Mixing path INT0 */
{"RX INT0_2 MUX", "RX0", "CDC_IF RX0 MUX"},
{"RX INT0_2 MUX", "RX1", "CDC_IF RX1 MUX"},
{"RX INT0_2 MUX", "RX2", "CDC_IF RX2 MUX"},
{"RX INT0_2 MUX", "RX3", "CDC_IF RX3 MUX"},
{"RX INT0_2 MUX", "RX4", "CDC_IF RX4 MUX"},
{"RX INT0_2 MUX", "RX5", "CDC_IF RX5 MUX"},
{"RX INT0_2 MUX", "RX6", "CDC_IF RX6 MUX"},
{"RX INT0_2 MUX", "RX7", "CDC_IF RX7 MUX"},
{"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"},
{"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"},
/* Mixing path INT7 */
{"RX INT7_2 MUX", "RX0", "CDC_IF RX0 MUX"},
{"RX INT7_2 MUX", "RX1", "CDC_IF RX1 MUX"},
{"RX INT7_2 MUX", "RX2", "CDC_IF RX2 MUX"},
{"RX INT7_2 MUX", "RX3", "CDC_IF RX3 MUX"},
{"RX INT7_2 MUX", "RX4", "CDC_IF RX4 MUX"},
{"RX INT7_2 MUX", "RX5", "CDC_IF RX5 MUX"},
{"RX INT7_2 MUX", "RX6", "CDC_IF RX6 MUX"},
{"RX INT7_2 MUX", "RX7", "CDC_IF RX7 MUX"},
{"RX INT7_2 INTERP", NULL, "RX INT7_2 MUX"},
{"RX INT7 SEC MIX", NULL, "RX INT7_2 INTERP"},
/* Mixing path INT8 */
{"RX INT8_2 MUX", "RX0", "CDC_IF RX0 MUX"},
{"RX INT8_2 MUX", "RX1", "CDC_IF RX1 MUX"},
{"RX INT8_2 MUX", "RX2", "CDC_IF RX2 MUX"},
{"RX INT8_2 MUX", "RX3", "CDC_IF RX3 MUX"},
{"RX INT8_2 MUX", "RX4", "CDC_IF RX4 MUX"},
{"RX INT8_2 MUX", "RX5", "CDC_IF RX5 MUX"},
{"RX INT8_2 MUX", "RX6", "CDC_IF RX6 MUX"},
{"RX INT8_2 MUX", "RX7", "CDC_IF RX7 MUX"},
{"RX INT8_2 INTERP", NULL, "RX INT8_2 MUX"},
{"RX INT8 SEC MIX", NULL, "RX INT8_2 INTERP"},
/* Mixing path INT9 */
{"RX INT9_2 MUX", "RX0", "CDC_IF RX0 MUX"},
{"RX INT9_2 MUX", "RX1", "CDC_IF RX1 MUX"},
{"RX INT9_2 MUX", "RX2", "CDC_IF RX2 MUX"},
{"RX INT9_2 MUX", "RX3", "CDC_IF RX3 MUX"},
{"RX INT9_2 MUX", "RX4", "CDC_IF RX4 MUX"},
{"RX INT9_2 MUX", "RX5", "CDC_IF RX5 MUX"},
{"RX INT9_2 MUX", "RX6", "CDC_IF RX6 MUX"},
{"RX INT9_2 MUX", "RX7", "CDC_IF RX7 MUX"},
{"RX INT9_2 INTERP", NULL, "RX INT9_2 MUX"},
{"RX INT9 SEC MIX", NULL, "RX INT9_2 INTERP"},
{"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"},
{"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"},
{"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"},
{"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"},
{"RX INT0 DEM MUX", NULL, "RX INT0 MIX2"},
{"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
{"RX INT0 DAC", NULL, "LDO_RXTX"},
{"EAR PA", NULL, "RX INT0 DAC"},
{"EAR", NULL, "EAR PA"},
{"RX INT7_1 INTERP", NULL, "RX INT7_1 MIX1"},
{"RX INT7 SEC MIX", NULL, "RX INT7_1 INTERP"},
{"RX INT7 MIX2", NULL, "RX INT7 SEC MIX"},
{"RX INT7 MIX2", NULL, "RX INT7 MIX2 INP"},
{"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
{"SPK1 OUT", NULL, "RX INT7 CHAIN"},
{"RX INT8_1 INTERP", NULL, "RX INT8_1 MIX1"},
{"RX INT8 SEC MIX", NULL, "RX INT8_1 INTERP"},
{"RX INT8 SEC MIX", NULL, "RX INT8_1 MIX1"},
{"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
{"SPK2 OUT", NULL, "RX INT8 CHAIN"},
{"RX INT9_1 INTERP", NULL, "RX INT9_1 MIX1"},
{"RX INT9 SEC MIX", NULL, "RX INT9_1 INTERP"},
{"RX INT9 MIX2", NULL, "RX INT9 SEC MIX"},
{"RX INT9 MIX2", NULL, "RX INT9 MIX2 INP"},
{"RX INT9 DEM MUX", NULL, "RX INT9 MIX2"},
{"RX INT9 DAC", NULL, "RX INT9 DEM MUX"},
{"RX INT9 DAC", NULL, "LDO_RXTX"},
{"AUX PA", NULL, "RX INT9 DAC"},
{"AUX", NULL, "AUX PA"},
/* ANC Routing */
{"ANC0 FB MUX", "ANC_IN_EAR", "RX INT0 MIX2"},
{"ANC0 FB MUX", "ANC_IN_EAR_SPKR", "RX INT7 MIX2"},
{"ANC OUT EAR Enable", "Switch", "ADC MUX10"},
{"ANC OUT EAR Enable", "Switch", "ADC MUX11"},
{"RX INT0 MIX2", NULL, "ANC OUT EAR Enable"},
{"ANC EAR PA", NULL, "RX INT0 DAC"},
{"ANC EAR", NULL, "ANC EAR PA"},
{"ANC OUT EAR SPKR Enable", "Switch", "ADC MUX10"},
{"ANC OUT EAR SPKR Enable", "Switch", "ADC MUX11"},
{"RX INT7 MIX2", NULL, "ANC OUT EAR SPKR Enable"},
{"ANC SPKR PA Enable", "Switch", "RX INT7 CHAIN"},
{"ANC SPK1 PA", NULL, "ANC SPKR PA Enable"},
{"SPK1 OUT", NULL, "ANC SPK1 PA"},
/*
* SRC0 input to Sidetone RX Mixer
* on RX0, RX1, RX2, RX3, RX4 and RX7 chains
*/
{"IIR0", NULL, "IIR0 INP0 MUX"},
{"IIR0 INP0 MUX", "DEC0", "ADC MUX0"},
{"IIR0 INP0 MUX", "DEC1", "ADC MUX1"},
{"IIR0 INP0 MUX", "DEC2", "ADC MUX2"},
{"IIR0 INP0 MUX", "DEC3", "ADC MUX3"},
{"IIR0 INP0 MUX", "DEC4", "ADC MUX4"},
{"IIR0 INP0 MUX", "DEC5", "ADC MUX5"},
{"IIR0 INP0 MUX", "DEC6", "ADC MUX6"},
{"IIR0 INP0 MUX", "DEC7", "ADC MUX7"},
{"IIR0 INP0 MUX", "DEC8", "ADC MUX8"},
{"IIR0 INP0 MUX", "RX0", "CDC_IF RX0 MUX"},
{"IIR0 INP0 MUX", "RX1", "CDC_IF RX1 MUX"},
{"IIR0 INP0 MUX", "RX2", "CDC_IF RX2 MUX"},
{"IIR0 INP0 MUX", "RX3", "CDC_IF RX3 MUX"},
{"IIR0 INP0 MUX", "RX4", "CDC_IF RX4 MUX"},
{"IIR0 INP0 MUX", "RX5", "CDC_IF RX5 MUX"},
{"IIR0 INP0 MUX", "RX6", "CDC_IF RX6 MUX"},
{"IIR0 INP0 MUX", "RX7", "CDC_IF RX7 MUX"},
{"IIR0", NULL, "IIR0 INP1 MUX"},
{"IIR0 INP1 MUX", "DEC0", "ADC MUX0"},
{"IIR0 INP1 MUX", "DEC1", "ADC MUX1"},
{"IIR0 INP1 MUX", "DEC2", "ADC MUX2"},
{"IIR0 INP1 MUX", "DEC3", "ADC MUX3"},
{"IIR0 INP1 MUX", "DEC4", "ADC MUX4"},
{"IIR0 INP1 MUX", "DEC5", "ADC MUX5"},
{"IIR0 INP1 MUX", "DEC6", "ADC MUX6"},
{"IIR0 INP1 MUX", "DEC7", "ADC MUX7"},
{"IIR0 INP1 MUX", "DEC8", "ADC MUX8"},
{"IIR0 INP1 MUX", "RX0", "CDC_IF RX0 MUX"},
{"IIR0 INP1 MUX", "RX1", "CDC_IF RX1 MUX"},
{"IIR0 INP1 MUX", "RX2", "CDC_IF RX2 MUX"},
{"IIR0 INP1 MUX", "RX3", "CDC_IF RX3 MUX"},
{"IIR0 INP1 MUX", "RX4", "CDC_IF RX4 MUX"},
{"IIR0 INP1 MUX", "RX5", "CDC_IF RX5 MUX"},
{"IIR0 INP1 MUX", "RX6", "CDC_IF RX6 MUX"},
{"IIR0 INP1 MUX", "RX7", "CDC_IF RX7 MUX"},
{"IIR0", NULL, "IIR0 INP2 MUX"},
{"IIR0 INP2 MUX", "DEC0", "ADC MUX0"},
{"IIR0 INP2 MUX", "DEC1", "ADC MUX1"},
{"IIR0 INP2 MUX", "DEC2", "ADC MUX2"},
{"IIR0 INP2 MUX", "DEC3", "ADC MUX3"},
{"IIR0 INP2 MUX", "DEC4", "ADC MUX4"},
{"IIR0 INP2 MUX", "DEC5", "ADC MUX5"},
{"IIR0 INP2 MUX", "DEC6", "ADC MUX6"},
{"IIR0 INP2 MUX", "DEC7", "ADC MUX7"},
{"IIR0 INP2 MUX", "DEC8", "ADC MUX8"},
{"IIR0 INP2 MUX", "RX0", "CDC_IF RX0 MUX"},
{"IIR0 INP2 MUX", "RX1", "CDC_IF RX1 MUX"},
{"IIR0 INP2 MUX", "RX2", "CDC_IF RX2 MUX"},
{"IIR0 INP2 MUX", "RX3", "CDC_IF RX3 MUX"},
{"IIR0 INP2 MUX", "RX4", "CDC_IF RX4 MUX"},
{"IIR0 INP2 MUX", "RX5", "CDC_IF RX5 MUX"},
{"IIR0 INP2 MUX", "RX6", "CDC_IF RX6 MUX"},
{"IIR0 INP2 MUX", "RX7", "CDC_IF RX7 MUX"},
{"IIR0", NULL, "IIR0 INP3 MUX"},
{"IIR0 INP3 MUX", "DEC0", "ADC MUX0"},
{"IIR0 INP3 MUX", "DEC1", "ADC MUX1"},
{"IIR0 INP3 MUX", "DEC2", "ADC MUX2"},
{"IIR0 INP3 MUX", "DEC3", "ADC MUX3"},
{"IIR0 INP3 MUX", "DEC4", "ADC MUX4"},
{"IIR0 INP3 MUX", "DEC5", "ADC MUX5"},
{"IIR0 INP3 MUX", "DEC6", "ADC MUX6"},
{"IIR0 INP3 MUX", "DEC7", "ADC MUX7"},
{"IIR0 INP3 MUX", "DEC8", "ADC MUX8"},
{"IIR0 INP3 MUX", "RX0", "CDC_IF RX0 MUX"},
{"IIR0 INP3 MUX", "RX1", "CDC_IF RX1 MUX"},
{"IIR0 INP3 MUX", "RX2", "CDC_IF RX2 MUX"},
{"IIR0 INP3 MUX", "RX3", "CDC_IF RX3 MUX"},
{"IIR0 INP3 MUX", "RX4", "CDC_IF RX4 MUX"},
{"IIR0 INP3 MUX", "RX5", "CDC_IF RX5 MUX"},
{"IIR0 INP3 MUX", "RX6", "CDC_IF RX6 MUX"},
{"IIR0 INP3 MUX", "RX7", "CDC_IF RX7 MUX"},
{"SRC0", NULL, "IIR0"},
{"RX INT0 MIX2 INP", "SRC0", "SRC0"},
{"RX INT7 MIX2 INP", "SRC0", "SRC0"},
{"RX INT9 MIX2 INP", "SRC0", "SRC0"},
/* Native clk mix path routing */
{"RX INT7_2 NATIVE MUX", "ON", "RX INT7_2 MUX"},
{"RX INT7_2 INTERP", NULL, "RX INT7_2 NATIVE MUX"},
{"RX INT7_2 NATIVE MUX", NULL, "RX INT7 NATIVE SUPPLY"},
{"RX INT8_2 NATIVE MUX", "ON", "RX INT8_2 MUX"},
{"RX INT8_2 INTERP", NULL, "RX INT8_2 NATIVE MUX"},
{"RX INT8_2 NATIVE MUX", NULL, "RX INT8 NATIVE SUPPLY"},
/* ASRC Routing */
{"ASRC2 MUX", "ASRC_IN_SPKR1", "RX INT7_2 INTERP"},
{"RX INT7 SEC MIX", NULL, "ASRC2 MUX"},
{"ASRC3 MUX", "ASRC_IN_SPKR2", "RX INT8_2 INTERP"},
{"RX INT8 SEC MIX", NULL, "ASRC3 MUX"},
/* SLIMBUS-I2S Bridge interface */
{"I2S TX1_0 MUX", "SB_RX2", "SLIM RX2"},
{"I2S TX1_1 MUX", "SB_RX0", "SLIM RX0"},
{"I2S TX1_1 MUX", "SB_RX1", "SLIM RX1"},
{"I2S TX1_1 MUX", "SB_RX2", "SLIM RX2"},
{"I2S TX1_1 MUX", "SB_RX3", "SLIM RX3"},
{"I2S TX1 MIXER", NULL, "I2S TX1_0 MUX"},
{"I2S TX1 MIXER", NULL, "I2S TX1_1 MUX"},
{"I2S1 CAP", NULL, "I2S TX1 MIXER"},
{"CDC_IF TX10 MUX2", "I2SRX1_0_BRDG", "CDC_IF RX2 MUX"},
{"CDC_IF TX11 MUX2", "I2SRX1_1_BRDG", "CDC_IF RX3 MUX"},
{"CDC_IF RX2 MUX", "I2SRX1_0", "I2S1 PB"},
{"CDC_IF RX3 MUX", "I2SRX1_1", "I2S1 PB"},
};
#endif

8101
asoc/codecs/wcd9360/wcd9360.c
View File

File diff suppressed because it is too large Load Diff

180
asoc/codecs/wcd9360/wcd9360.h
View File

@@ -1,180 +0,0 @@
/*
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __WCD9360_H__
#define __WCD9360_H__
#include <dsp/apr_audio-v2.h>
#include "../wcd9xxx-slimslave.h"
#include "../wcd9xxx-common-v2.h"
#define WCD9360_REGISTER_START_OFFSET 0x800
#define WCD9360_SB_PGD_PORT_RX_BASE 0x40
#define WCD9360_SB_PGD_PORT_TX_BASE 0x50
#define WCD9360_RX_PORT_START_NUMBER 16
#define WCD9360_DMIC_CLK_DIV_2 0x0
#define WCD9360_DMIC_CLK_DIV_3 0x1
#define WCD9360_DMIC_CLK_DIV_4 0x2
#define WCD9360_DMIC_CLK_DIV_6 0x3
#define WCD9360_DMIC_CLK_DIV_8 0x4
#define WCD9360_DMIC_CLK_DIV_16 0x5
#define WCD9360_DMIC_CLK_DRIVE_DEFAULT 0x02
#define WCD9360_ANC_DMIC_X2_FULL_RATE 1
#define WCD9360_ANC_DMIC_X2_HALF_RATE 0
#define PAHU_MAX_MICBIAS 4
#define PAHU_NUM_INTERPOLATORS 10
#define MAX_ON_DEMAND_SUPPLY_NAME_LENGTH 64
/* Convert from vout ctl to micbias voltage in mV */
#define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
/* Number of input and output Slimbus port */
enum {
WCD9360_RX0 = 0,
WCD9360_RX1,
WCD9360_RX2,
WCD9360_RX3,
WCD9360_RX4,
WCD9360_RX5,
WCD9360_RX6,
WCD9360_RX7,
WCD9360_RX_MAX,
};
enum {
WCD9360_TX0 = 0,
WCD9360_TX1,
WCD9360_TX2,
WCD9360_TX3,
WCD9360_TX4,
WCD9360_TX5,
WCD9360_TX6,
WCD9360_TX7,
WCD9360_TX8,
WCD9360_TX9,
WCD9360_TX10,
WCD9360_TX11,
WCD9360_TX12,
WCD9360_TX13,
WCD9360_TX14,
WCD9360_TX15,
WCD9360_TX_MAX,
};
/*
* Selects compander and smart boost settings
* for a given speaker mode
*/
enum {
WCD9360_SPKR_MODE_DEFAULT,
WCD9360_SPKR_MODE_1, /* COMP Gain = 12dB, Smartboost Max = 5.5V */
};
/*
* Rx path gain offsets
*/
enum {
WCD9360_RX_GAIN_OFFSET_M1P5_DB,
WCD9360_RX_GAIN_OFFSET_0_DB,
};
enum {
WCD9360_MIC_BIAS_1 = 1,
WCD9360_MIC_BIAS_2,
WCD9360_MIC_BIAS_3,
WCD9360_MIC_BIAS_4
};
enum {
WCD9360_MICB_PULLUP_ENABLE,
WCD9360_MICB_PULLUP_DISABLE,
WCD9360_MICB_ENABLE,
WCD9360_MICB_DISABLE,
};
/*
* Dai data structure holds the
* dai specific info like rate,
* channel number etc.
*/
struct pahu_codec_dai_data {
u32 rate;
u32 *ch_num;
u32 ch_act;
u32 ch_tot;
};
/*
* Structure used to update codec
* register defaults after reset
*/
struct pahu_reg_mask_val {
u16 reg;
u8 mask;
u8 val;
};
#if IS_ENABLED(CONFIG_SND_SOC_WCD9360)
extern void *pahu_get_afe_config(struct snd_soc_codec *codec,
enum afe_config_type config_type);
extern int pahu_cdc_mclk_enable(struct snd_soc_codec *codec, bool enable);
extern int pahu_cdc_mclk_tx_enable(struct snd_soc_codec *codec, bool enable);
extern int pahu_set_spkr_mode(struct snd_soc_codec *codec, int mode);
extern int pahu_set_spkr_gain_offset(struct snd_soc_codec *codec, int offset);
extern void *pahu_get_wcd_dsp_cntl(struct device *dev);
extern int wcd9360_get_micb_vout_ctl_val(u32 micb_mv);
extern int pahu_codec_info_create_codec_entry(
struct snd_info_entry *codec_root,
struct snd_soc_codec *codec);
#else
extern void *pahu_get_afe_config(struct snd_soc_codec *codec,
enum afe_config_type config_type)
{
return NULL;
}
extern int pahu_cdc_mclk_enable(struct snd_soc_codec *codec, bool enable)
{
return 0;
}
extern int pahu_cdc_mclk_tx_enable(struct snd_soc_codec *codec, bool enable)
{
return 0;
}
extern int pahu_set_spkr_mode(struct snd_soc_codec *codec, int mode)
{
return 0;
}
extern int pahu_set_spkr_gain_offset(struct snd_soc_codec *codec, int offset)
{
return 0;
}
extern void *pahu_get_wcd_dsp_cntl(struct device *dev)
{
return NULL;
}
extern int wcd9360_get_micb_vout_ctl_val(u32 micb_mv)
{
return 0;
}
extern int pahu_codec_info_create_codec_entry(
struct snd_info_entry *codec_root,
struct snd_soc_codec *codec)
{
return 0;
}
#endif
#endif

2
asoc/codecs/wcd937x/Android.mk
View File

@@ -9,7 +9,7 @@ endif
AUDIO_CHIPSET := audio AUDIO_CHIPSET := audio
# Build/Package only in case of supported target # Build/Package only in case of supported target
ifeq ($(call is-board-platform-in-list,msm8953 sdm845 sdm670 qcs605 msmnile $(MSMSTEPPE) $(TRINKET)),true) ifeq ($(call is-board-platform-in-list,$(MSMSTEPPE) $(TRINKET)),true)
LOCAL_PATH := $(call my-dir) LOCAL_PATH := $(call my-dir)

8
asoc/codecs/wcd9xxx-core.c
View File

@@ -88,7 +88,6 @@ static const int wcd9xxx_cdc_types[] = {
[WCD9330] = WCD9330, [WCD9330] = WCD9330,
[WCD9335] = WCD9335, [WCD9335] = WCD9335,
[WCD934X] = WCD934X, [WCD934X] = WCD934X,
[WCD9360] = WCD9360,
}; };
static const struct of_device_id wcd9xxx_of_match[] = { static const struct of_device_id wcd9xxx_of_match[] = {
@@ -330,8 +329,7 @@ int wcd9xxx_slim_write_repeat(struct wcd9xxx *wcd9xxx, unsigned short reg,
struct slim_ele_access slim_msg; struct slim_ele_access slim_msg;
mutex_lock(&wcd9xxx->io_lock); mutex_lock(&wcd9xxx->io_lock);
if (wcd9xxx->type == WCD9335 || wcd9xxx->type == WCD934X || if (wcd9xxx->type == WCD9335 || wcd9xxx->type == WCD934X) {
wcd9xxx->type == WCD9360) {
ret = wcd9xxx_page_write(wcd9xxx, &reg); ret = wcd9xxx_page_write(wcd9xxx, &reg);
if (ret) if (ret)
goto done; goto done;
@@ -1353,8 +1351,7 @@ static int wcd9xxx_slim_probe(struct slim_device *slim)
* Vout_D to be ready after BUCK_SIDO is powered up. * Vout_D to be ready after BUCK_SIDO is powered up.
* SYS_RST_N shouldn't be pulled high during this time * SYS_RST_N shouldn't be pulled high during this time
*/ */
if (wcd9xxx->type == WCD9335 || wcd9xxx->type == WCD934X || if (wcd9xxx->type == WCD9335 || wcd9xxx->type == WCD934X)
wcd9xxx->type == WCD9360)
usleep_range(600, 650); usleep_range(600, 650);
else else
usleep_range(5, 10); usleep_range(5, 10);
@@ -1600,7 +1597,6 @@ static const struct slim_device_id wcd_slim_device_id[] = {
{"tomtom-slim-pgd", WCD9330}, {"tomtom-slim-pgd", WCD9330},
{"tasha-slim-pgd", WCD9335}, {"tasha-slim-pgd", WCD9335},
{"tavil-slim-pgd", WCD934X}, {"tavil-slim-pgd", WCD934X},
{"pahu-slim-pgd", WCD9360},
{} {}
}; };

5
asoc/codecs/wcd9xxx-regmap.h
View File

@@ -19,8 +19,6 @@
typedef int (*regmap_patch_fptr)(struct regmap *, int); typedef int (*regmap_patch_fptr)(struct regmap *, int);
extern struct regmap_config wcd9360_regmap_config;
extern struct regmap_config wcd934x_regmap_config; extern struct regmap_config wcd934x_regmap_config;
extern int wcd934x_regmap_register_patch(struct regmap *regmap, extern int wcd934x_regmap_register_patch(struct regmap *regmap,
int version); int version);
@@ -34,9 +32,6 @@ static inline struct regmap_config *wcd9xxx_get_regmap_config(int type)
struct regmap_config *regmap_config; struct regmap_config *regmap_config;
switch (type) { switch (type) {
case WCD9360:
regmap_config = &wcd9360_regmap_config;
break;
case WCD934X: case WCD934X:
regmap_config = &wcd934x_regmap_config; regmap_config = &wcd934x_regmap_config;
break; break;

159
asoc/codecs/wcd9xxx-rst.c
View File

@@ -22,8 +22,6 @@
#include "wcd9335_irq.h" #include "wcd9335_irq.h"
#include <asoc/wcd934x_registers.h> #include <asoc/wcd934x_registers.h>
#include "wcd934x/wcd934x_irq.h" #include "wcd934x/wcd934x_irq.h"
#include <asoc/wcd9360-registers.h>
#include "wcd9360/wcd9360-irq.h"
/* wcd9335 interrupt table */ /* wcd9335 interrupt table */
static const struct intr_data wcd9335_intr_table[] = { static const struct intr_data wcd9335_intr_table[] = {
@@ -88,25 +86,6 @@ static const struct intr_data wcd934x_intr_table[] = {
{WCD934X_IRQ_VBAT_RESTORE, false}, {WCD934X_IRQ_VBAT_RESTORE, false},
}; };
static const struct intr_data wcd9360_intr_table[] = {
{WCD9XXX_IRQ_SLIMBUS, false},
{WCD9360_IRQ_MISC, false},
{WCD9360_IRQ_LDO_RXTX_SCD, false},
{WCD9360_IRQ_EAR_PA_SCD, false},
{WCD9360_IRQ_AUX_PA_SCD, false},
{WCD9360_IRQ_EAR_PA_CNP_COMPLETE, false},
{WCD9360_IRQ_AUX_PA_CNP_COMPLETE, false},
{WCD9360_IRQ_RESERVED_3, false},
{WCD9360_IRQ_SOUNDWIRE, false},
{WCD9360_IRQ_RCO_ERROR, false},
{WCD9360_IRQ_CPE_ERROR, false},
{WCD9360_IRQ_MAD_AUDIO, false},
{WCD9360_IRQ_MAD_BEACON, false},
{WCD9360_IRQ_CPE1_INTR, true},
{WCD9360_IRQ_RESERVED_4, false},
{WCD9360_IRQ_MAD_ULTRASOUND, false},
};
/* /*
* wcd9335_bring_down: Bringdown WCD Codec * wcd9335_bring_down: Bringdown WCD Codec
* *
@@ -405,143 +384,11 @@ version_unknown:
return rc; return rc;
} }
/*
* wcd9360_bring_down: Bringdown WCD Codec
*
* @wcd9xxx: Pointer to wcd9xxx structure
*
* Returns 0 for success or negative error code for failure
*/
static int wcd9360_bring_down(struct wcd9xxx *wcd9xxx)
{
if (!wcd9xxx || !wcd9xxx->regmap)
return -EINVAL;
regmap_write(wcd9xxx->regmap, WCD9360_CODEC_RPM_PWR_CDC_DIG_HM_CTL,
0x04);
return 0;
}
/*
* wcd9360_bring_up: Bringup WCD Codec
*
* @wcd9xxx: Pointer to the wcd9xxx structure
*
* Returns 0 for success or negative error code for failure
*/
static int wcd9360_bring_up(struct wcd9xxx *wcd9xxx)
{
struct regmap *wcd_regmap;
if (!wcd9xxx)
return -EINVAL;
if (!wcd9xxx->regmap) {
dev_err(wcd9xxx->dev, "%s: wcd9xxx regmap is null!\n",
__func__);
return -EINVAL;
}
wcd_regmap = wcd9xxx->regmap;
regmap_write(wcd_regmap, WCD9360_CODEC_RPM_RST_CTL, 0x01);
regmap_write(wcd_regmap, WCD9360_SIDO_NEW_VOUT_A_STARTUP, 0x19);
regmap_write(wcd_regmap, WCD9360_SIDO_NEW_VOUT_D_STARTUP, 0x15);
/* Add 1msec delay for VOUT to settle */
usleep_range(1000, 1100);
regmap_write(wcd_regmap, WCD9360_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
regmap_write(wcd_regmap, WCD9360_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
regmap_write(wcd_regmap, WCD9360_CODEC_RPM_RST_CTL, 0x3);
regmap_write(wcd_regmap, WCD9360_CODEC_RPM_RST_CTL, 0x7);
regmap_write(wcd_regmap, WCD9360_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
return 0;
}
/*
* wcd9360_get_cdc_info: Get codec specific information
*
* @wcd9xxx: pointer to wcd9xxx structure
* @wcd_type: pointer to wcd9xxx_codec_type structure
*
* Returns 0 for success or negative error code for failure
*/
static int wcd9360_get_cdc_info(struct wcd9xxx *wcd9xxx,
struct wcd9xxx_codec_type *wcd_type)
{
u16 id_minor, id_major;
struct regmap *wcd_regmap;
int rc, version = -1;
if (!wcd9xxx || !wcd_type)
return -EINVAL;
if (!wcd9xxx->regmap) {
dev_err(wcd9xxx->dev, "%s: wcd9xxx regmap is null\n", __func__);
return -EINVAL;
}
wcd_regmap = wcd9xxx->regmap;
rc = regmap_bulk_read(wcd_regmap, WCD9360_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
(u8 *)&id_minor, sizeof(u16));
if (rc)
return -EINVAL;
rc = regmap_bulk_read(wcd_regmap, WCD9360_CHIP_TIER_CTRL_CHIP_ID_BYTE2,
(u8 *)&id_major, sizeof(u16));
if (rc)
return -EINVAL;
dev_info(wcd9xxx->dev, "%s: wcd9xxx chip id major 0x%x, minor 0x%x\n",
__func__, id_major, id_minor);
if (id_major != PAHU_MAJOR)
goto version_unknown;
/*
* As fine version info cannot be retrieved before pahu probe.
* Assign coarse versions for possible future use before Pahu probe.
*/
if (id_minor == cpu_to_le16(0))
version = PAHU_VERSION_1_0;
version_unknown:
if (version < 0)
dev_err(wcd9xxx->dev, "%s: wcd934x version unknown\n",
__func__);
/* Fill codec type info */
wcd_type->id_major = id_major;
wcd_type->id_minor = id_minor;
wcd_type->num_irqs = WCD9360_NUM_IRQS;
wcd_type->version = version;
wcd_type->slim_slave_type = WCD9XXX_SLIM_SLAVE_ADDR_TYPE_1;
wcd_type->i2c_chip_status = 0x01;
wcd_type->intr_tbl = wcd9360_intr_table;
wcd_type->intr_tbl_size = ARRAY_SIZE(wcd9360_intr_table);
wcd_type->intr_reg[WCD9XXX_INTR_STATUS_BASE] =
WCD9360_INTR_PIN1_STATUS0;
wcd_type->intr_reg[WCD9XXX_INTR_CLEAR_BASE] =
WCD9360_INTR_PIN1_CLEAR0;
wcd_type->intr_reg[WCD9XXX_INTR_MASK_BASE] =
WCD9360_INTR_PIN1_MASK0;
wcd_type->intr_reg[WCD9XXX_INTR_LEVEL_BASE] =
WCD9360_INTR_LEVEL0;
wcd_type->intr_reg[WCD9XXX_INTR_CLR_COMMIT] =
WCD9360_INTR_CLR_COMMIT;
return rc;
}
codec_bringdown_fn wcd9xxx_bringdown_fn(int type) codec_bringdown_fn wcd9xxx_bringdown_fn(int type)
{ {
codec_bringdown_fn cdc_bdown_fn; codec_bringdown_fn cdc_bdown_fn;
switch (type) { switch (type) {
case WCD9360:
cdc_bdown_fn = wcd9360_bring_down;
break;
case WCD934X: case WCD934X:
cdc_bdown_fn = wcd934x_bring_down; cdc_bdown_fn = wcd934x_bring_down;
break; break;
@@ -561,9 +408,6 @@ codec_bringup_fn wcd9xxx_bringup_fn(int type)
codec_bringup_fn cdc_bup_fn; codec_bringup_fn cdc_bup_fn;
switch (type) { switch (type) {
case WCD9360:
cdc_bup_fn = wcd9360_bring_up;
break;
case WCD934X: case WCD934X:
cdc_bup_fn = wcd934x_bring_up; cdc_bup_fn = wcd934x_bring_up;
break; break;
@@ -583,9 +427,6 @@ codec_type_fn wcd9xxx_get_codec_info_fn(int type)
codec_type_fn cdc_type_fn; codec_type_fn cdc_type_fn;
switch (type) { switch (type) {
case WCD9360:
cdc_type_fn = wcd9360_get_cdc_info;
break;
case WCD934X: case WCD934X:
cdc_type_fn = wcd934x_get_cdc_info; cdc_type_fn = wcd934x_get_cdc_info;
break; break;

17
asoc/codecs/wcd9xxx-utils.c
View File

@@ -38,16 +38,6 @@
static enum wcd9xxx_intf_status wcd9xxx_intf = -1; static enum wcd9xxx_intf_status wcd9xxx_intf = -1;
static struct mfd_cell pahu_devs[] = {
{
.name = "qcom-wcd-pinctrl",
.of_compatible = "qcom,wcd-pinctrl",
},
{
.name = "pahu_codec",
},
};
static struct mfd_cell tavil_devs[] = { static struct mfd_cell tavil_devs[] = {
{ {
.name = "qcom-wcd-pinctrl", .name = "qcom-wcd-pinctrl",
@@ -490,8 +480,7 @@ int wcd9xxx_page_write(struct wcd9xxx *wcd9xxx, unsigned short *reg)
unsigned short c_reg, reg_addr; unsigned short c_reg, reg_addr;
u8 pg_num, prev_pg_num; u8 pg_num, prev_pg_num;
if (wcd9xxx->type != WCD9335 && wcd9xxx->type != WCD934X && if (wcd9xxx->type != WCD9335 && wcd9xxx->type != WCD934X)
wcd9xxx->type != WCD9360)
return ret; return ret;
c_reg = *reg; c_reg = *reg;
@@ -888,10 +877,6 @@ int wcd9xxx_get_codec_info(struct device *dev)
} }
switch (wcd9xxx->type) { switch (wcd9xxx->type) {
case WCD9360:
cinfo->dev = pahu_devs;
cinfo->size = ARRAY_SIZE(pahu_devs);
break;
case WCD934X: case WCD934X:
cinfo->dev = tavil_devs; cinfo->dev = tavil_devs;
cinfo->size = ARRAY_SIZE(tavil_devs); cinfo->size = ARRAY_SIZE(tavil_devs);

7483
asoc/msm8998.c
View File

File diff suppressed because it is too large Load Diff

3551
asoc/sdm660-common.c
View File

File diff suppressed because it is too large Load Diff

133
asoc/sdm660-common.h
View File

@@ -1,133 +0,0 @@
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MSM_COMMON
#define __MSM_COMMON
#include <sound/soc.h>
#include <dsp/q6afe-v2.h>
#include "codecs/wcd-mbhc-v2.h"
#define DEFAULT_MCLK_RATE 9600000
#define NATIVE_MCLK_RATE 11289600
#define SAMPLING_RATE_8KHZ 8000
#define SAMPLING_RATE_11P025KHZ 11025
#define SAMPLING_RATE_16KHZ 16000
#define SAMPLING_RATE_22P05KHZ 22050
#define SAMPLING_RATE_32KHZ 32000
#define SAMPLING_RATE_44P1KHZ 44100
#define SAMPLING_RATE_48KHZ 48000
#define SAMPLING_RATE_88P2KHZ 88200
#define SAMPLING_RATE_96KHZ 96000
#define SAMPLING_RATE_176P4KHZ 176400
#define SAMPLING_RATE_192KHZ 192000
#define SAMPLING_RATE_352P8KHZ 352800
#define SAMPLING_RATE_384KHZ 384000
#define TDM_CHANNEL_MAX 8
#define TDM_SLOT_OFFSET_MAX 8
enum {
TDM_0 = 0,
TDM_1,
TDM_2,
TDM_3,
TDM_4,
TDM_5,
TDM_6,
TDM_7,
TDM_PORT_MAX,
};
enum {
TDM_PRI = 0,
TDM_SEC,
TDM_TERT,
TDM_QUAT,
TDM_QUIN,
TDM_INTERFACE_MAX,
};
struct tdm_port {
u32 mode;
u32 channel;
};
enum {
PRIM_MI2S = 0,
SEC_MI2S,
TERT_MI2S,
QUAT_MI2S,
QUIN_MI2S,
MI2S_MAX,
};
enum {
DIG_CDC,
ANA_CDC,
CODECS_MAX,
};
extern const struct snd_kcontrol_new msm_common_snd_controls[];
extern bool codec_reg_done;
struct sdm660_codec {
void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
enum afe_config_type config_type);
};
enum {
INT_SND_CARD,
EXT_SND_CARD_TASHA,
EXT_SND_CARD_TAVIL,
};
struct msm_asoc_mach_data {
int us_euro_gpio; /* used by gpio driver API */
int usbc_en2_gpio; /* used by gpio driver API */
int hph_en1_gpio;
int hph_en0_gpio;
struct device_node *us_euro_gpio_p; /* used by pinctrl API */
struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
struct device_node *pdm_gpio_p; /* used by pinctrl API */
struct device_node *comp_gpio_p; /* used by pinctrl API */
struct device_node *dmic_gpio_p; /* used by pinctrl API */
struct device_node *ext_spk_gpio_p; /* used by pinctrl API */
struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
struct snd_soc_codec *codec;
struct sdm660_codec sdm660_codec_fn;
struct snd_info_entry *codec_root;
int spk_ext_pa_gpio;
int mclk_freq;
bool native_clk_set;
int lb_mode;
int snd_card_val;
u8 micbias1_cap_mode;
u8 micbias2_cap_mode;
atomic_t int_mclk0_rsc_ref;
atomic_t int_mclk0_enabled;
struct mutex cdc_int_mclk0_mutex;
struct delayed_work disable_int_mclk0_work;
struct afe_clk_set digital_cdc_core_clk;
};
int msm_common_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params);
int msm_aux_pcm_snd_startup(struct snd_pcm_substream *substream);
void msm_aux_pcm_snd_shutdown(struct snd_pcm_substream *substream);
int msm_mi2s_snd_startup(struct snd_pcm_substream *substream);
void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream);
int msm_common_snd_controls_size(void);
void msm_set_codec_reg_done(bool done);
#endif

2162
asoc/sdm660-ext-dai-links.c
View File

File diff suppressed because it is too large Load Diff

1882
asoc/sdm660-external.c
View File

File diff suppressed because it is too large Load Diff

52
asoc/sdm660-external.h
View File

@@ -1,52 +0,0 @@
/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SDM660_EXTERNAL
#define __SDM660_EXTERNAL
int msm_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params);
int msm_ext_slimbus_2_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params);
int msm_btsco_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params);
int msm_proxy_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params);
int msm_proxy_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params);
int msm_audrx_init(struct snd_soc_pcm_runtime *rtd);
int msm_snd_cpe_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params);
struct snd_soc_card *populate_snd_card_dailinks(struct device *dev,
int snd_card_val);
int msm_ext_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
struct snd_pcm_hw_params *params);
int msm_snd_card_tavil_late_probe(struct snd_soc_card *card);
int msm_snd_card_tasha_late_probe(struct snd_soc_card *card);
#if IS_ENABLED(CONFIG_SND_SOC_EXT_CODEC)
int msm_ext_cdc_init(struct platform_device *, struct msm_asoc_mach_data *,
struct snd_soc_card **, struct wcd_mbhc_config *);
void msm_ext_register_audio_notifier(struct platform_device *pdev);
#else
inline int msm_ext_cdc_init(struct platform_device *pdev,
struct msm_asoc_mach_data *pdata,
struct snd_soc_card **card,
struct wcd_mbhc_config *wcd_mbhc_cfg_ptr1)
{
return 0;
}
inline void msm_ext_register_audio_notifier(struct platform_device *pdev)
{
}
#endif
#endif

3354
asoc/sdm660-internal.c
View File

File diff suppressed because it is too large Load Diff

32
asoc/sdm660-internal.h
View File

@@ -1,32 +0,0 @@
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SDM660_INTERNAL
#define __SDM660_INTERNAL
#include <sound/soc.h>
#if IS_ENABLED(CONFIG_SND_SOC_INT_CODEC)
int msm_int_cdc_init(struct platform_device *pdev,
struct msm_asoc_mach_data *pdata,
struct snd_soc_card **card,
struct wcd_mbhc_config *mbhc_cfg);
#else
int msm_int_cdc_init(struct platform_device *pdev,
struct msm_asoc_mach_data *pdata,
struct snd_soc_card **card,
struct wcd_mbhc_config *mbhc_cfg)
{
return 0;
}
#endif
#endif

6963
asoc/sdm845.c
View File

File diff suppressed because it is too large Load Diff

50
config/sdm670auto.conf
View File

@@ -1,50 +0,0 @@
CONFIG_PINCTRL_LPI=m
CONFIG_PINCTRL_WCD=m
CONFIG_AUDIO_EXT_CLK=m
CONFIG_SND_SOC_WCD9XXX_V2=m
CONFIG_SND_SOC_WCD_MBHC=m
CONFIG_SND_SOC_WSA881X=m
CONFIG_SND_SOC_WCD_DSP_MGR=m
CONFIG_SND_SOC_WCD_SPI=m
CONFIG_SND_SOC_WCD_CPE=m
CONFIG_SND_SOC_CPE=m
CONFIG_SND_SOC_WCD9335=m
CONFIG_SND_SOC_WCD934X=m
CONFIG_SND_SOC_WCD934X_MBHC=m
CONFIG_SND_SOC_WCD934X_DSD=m
CONFIG_MSM_QDSP6V2_CODECS=m
CONFIG_MSM_ULTRASOUND=m
CONFIG_MSM_QDSP6_APRV2_GLINK=m
CONFIG_MSM_ADSP_LOADER=m
CONFIG_REGMAP_SWR=m
CONFIG_MSM_QDSP6_SSR=m
CONFIG_MSM_QDSP6_PDR=m
CONFIG_MSM_QDSP6_NOTIFIER=m
CONFIG_SND_SOC_MSM_HOSTLESS_PCM=m
CONFIG_SND_SOC_MSM_QDSP6V2_INTF=m
CONFIG_SND_SOC_SDM670=m
CONFIG_MSM_GLINK_SPI_XPRT=m
CONFIG_SOUNDWIRE=m
CONFIG_SOUNDWIRE_WCD_CTRL=m
CONFIG_SND_SOC_QDSP6V2=m
CONFIG_SND_SOC_MSM_QDSP6V2_INTF=m
CONFIG_WCD9XXX_CODEC_CORE=m
CONFIG_MSM_CDC_PINCTRL=m
CONFIG_SND_SOC_WCD_MBHC_ADC=m
CONFIG_SND_SOC_WCD_MBHC_LEGACY=m
CONFIG_QTI_PP=m
CONFIG_SND_HWDEP_ROUTING=m
CONFIG_DTS_EAGLE=m
CONFIG_DOLBY_DS2=m
CONFIG_DOLBY_LICENSE=m
CONFIG_DTS_SRS_TM=m
CONFIG_SND_SOC_EXT_CODEC=m
CONFIG_SND_SOC_INT_CODEC=m
CONFIG_SND_SOC_MSM_STUB=m
CONFIG_WCD_DSP_GLINK=m
CONFIG_MSM_AVTIMER=m
CONFIG_SND_SOC_SDM660_CDC=m
CONFIG_SND_SOC_ANALOG_CDC=m
CONFIG_SND_SOC_DIGITAL_CDC=m
CONFIG_SND_SOC_MSM_SDW=m
CONFIG_SND_SOC_MSM_HDMI_CODEC_RX=m

50
config/sdm670auto_static.conf
View File

@@ -1,50 +0,0 @@
CONFIG_PINCTRL_LPI=y
CONFIG_PINCTRL_WCD=y
CONFIG_AUDIO_EXT_CLK=y
CONFIG_SND_SOC_WCD9XXX_V2=y
CONFIG_SND_SOC_WCD_MBHC=y
CONFIG_SND_SOC_WSA881X=y
CONFIG_SND_SOC_WCD_DSP_MGR=y
CONFIG_SND_SOC_WCD_SPI=y
CONFIG_SND_SOC_WCD_CPE=y
CONFIG_SND_SOC_CPE=y
CONFIG_SND_SOC_WCD9335=y
CONFIG_SND_SOC_WCD934X=y
CONFIG_SND_SOC_WCD934X_MBHC=y
CONFIG_SND_SOC_WCD934X_DSD=y
CONFIG_MSM_QDSP6V2_CODECS=y
CONFIG_MSM_ULTRASOUND=y
CONFIG_MSM_QDSP6_APRV2_GLINK=y
CONFIG_MSM_ADSP_LOADER=y
CONFIG_REGMAP_SWR=y
CONFIG_MSM_QDSP6_SSR=y
CONFIG_MSM_QDSP6_PDR=y
CONFIG_MSM_QDSP6_NOTIFIER=y
CONFIG_SND_SOC_MSM_HOSTLESS_PCM=y
CONFIG_SND_SOC_MSM_QDSP6V2_INTF=y
CONFIG_SND_SOC_SDM670=y
CONFIG_MSM_GLINK_SPI_XPRT=y
CONFIG_SOUNDWIRE=y
CONFIG_SOUNDWIRE_WCD_CTRL=y
CONFIG_SND_SOC_QDSP6V2=y
CONFIG_SND_SOC_MSM_QDSP6V2_INTF=y
CONFIG_WCD9XXX_CODEC_CORE=y
CONFIG_MSM_CDC_PINCTRL=y
CONFIG_SND_SOC_WCD_MBHC_ADC=y
CONFIG_SND_SOC_WCD_MBHC_LEGACY=y
CONFIG_QTI_PP=y
CONFIG_SND_HWDEP_ROUTING=y
CONFIG_DTS_EAGLE=y
CONFIG_DOLBY_DS2=y
CONFIG_DOLBY_LICENSE=y
CONFIG_DTS_SRS_TM=y
CONFIG_SND_SOC_EXT_CODEC=y
CONFIG_SND_SOC_INT_CODEC=y
CONFIG_SND_SOC_MSM_STUB=y
CONFIG_WCD_DSP_GLINK=y
CONFIG_MSM_AVTIMER=y
CONFIG_SND_SOC_SDM660_CDC=y
CONFIG_SND_SOC_ANALOG_CDC=y
CONFIG_SND_SOC_DIGITAL_CDC=y
CONFIG_SND_SOC_MSM_SDW=y
CONFIG_SND_SOC_MSM_HDMI_CODEC_RX=y

63
config/sdm670autoconf.h
View File

@@ -1,63 +0,0 @@
/*
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define CONFIG_PINCTRL_LPI 1
#define CONFIG_PINCTRL_WCD 1
#define CONFIG_AUDIO_EXT_CLK 1
#define CONFIG_SND_SOC_WCD9XXX_V2 1
#define CONFIG_SND_SOC_WCD_CPE 1
#define CONFIG_SND_SOC_WCD_MBHC 1
#define CONFIG_SND_SOC_WSA881X 1
#define CONFIG_SND_SOC_WCD_DSP_MGR 1
#define CONFIG_SND_SOC_WCD_SPI 1
#define CONFIG_SND_SOC_WCD9335 1
#define CONFIG_SND_SOC_WCD934X 1
#define CONFIG_SND_SOC_WCD934X_MBHC 1
#define CONFIG_SND_SOC_WCD934X_DSD 1
#define CONFIG_MSM_QDSP6V2_CODECS 1
#define CONFIG_MSM_ULTRASOUND 1
#define CONFIG_MSM_QDSP6_APRV2_GLINK 1
#define CONFIG_MSM_ADSP_LOADER 1
#define CONFIG_REGMAP_SWR 1
#define CONFIG_MSM_QDSP6_SSR 1
#define CONFIG_MSM_QDSP6_PDR 1
#define CONFIG_MSM_QDSP6_NOTIFIER 1
#define CONFIG_SND_SOC_MSM_HOSTLESS_PCM 1
#define CONFIG_SND_SOC_MSM_QDSP6V2_INTF 1
#define CONFIG_SND_SOC_SDM670 1
#define CONFIG_MSM_GLINK_SPI_XPRT 1
#define CONFIG_SOUNDWIRE 1
#define CONFIG_SOUNDWIRE_WCD_CTRL 1
#define CONFIG_SND_SOC_WCD_MBHC_ADC 1
#define CONFIG_SND_SOC_WCD_MBHC_LEGACY 1
#define CONFIG_SND_SOC_QDSP6V2 1
#define CONFIG_SND_SOC_MSM_QDSP6V2_INTF 1
#define CONFIG_QTI_PP 1
#define CONFIG_SND_HWDEP_ROUTING 1
#define CONFIG_DTS_EAGLE 1
#define CONFIG_DOLBY_DS2 1
#define CONFIG_DOLBY_LICENSE 1
#define CONFIG_DTS_SRS_TM 1
#define CONFIG_WCD9XXX_CODEC_CORE 1
#define CONFIG_MSM_CDC_PINCTRL 1
#define CONFIG_SND_SOC_MSM_STUB 1
#define CONFIG_WCD_DSP_GLINK 1
#define CONFIG_MSM_AVTIMER 1
#define CONFIG_SND_SOC_EXT_CODEC 1
#define CONFIG_SND_SOC_INT_CODEC 1
#define CONFIG_SND_SOC_CPE 1
#define CONFIG_SND_SOC_SDM660_CDC 1
#define CONFIG_SND_SOC_ANALOG_CDC 1
#define CONFIG_SND_SOC_DIGITAL_CDC 1
#define CONFIG_SND_SOC_MSM_SDW 1
#define CONFIG_SND_SOC_MSM_HDMI_CODEC_RX 1

37
config/sdm845auto.conf
View File

@@ -1,37 +0,0 @@
CONFIG_PINCTRL_WCD=m
CONFIG_SND_SOC_WCD9XXX_V2=m
CONFIG_SND_SOC_WCD_MBHC=m
CONFIG_SND_SOC_WSA881X=m
CONFIG_SND_SOC_WCD_SPI=m
CONFIG_SND_SOC_WCD934X=m
CONFIG_SOUNDWIRE_WCD_CTRL=m
CONFIG_WCD9XXX_CODEC_CORE=m
CONFIG_MSM_CDC_PINCTRL=m
CONFIG_SND_SOC_WCD934X_MBHC=m
CONFIG_SND_SOC_WCD934X_DSD=m
CONFIG_SND_SOC_MACHINE_SDM845=m
CONFIG_WCD_DSP_GLINK=m
CONFIG_MSM_QDSP6V2_CODECS=y
CONFIG_MSM_ULTRASOUND=y
CONFIG_MSM_QDSP6_APRV2_GLINK=y
CONFIG_SND_SOC_MSM_QDSP6V2_INTF=y
CONFIG_MSM_ADSP_LOADER=y
CONFIG_REGMAP_SWR=y
CONFIG_MSM_QDSP6_SSR=y
CONFIG_MSM_QDSP6_PDR=y
CONFIG_MSM_QDSP6_NOTIFIER=y
CONFIG_SND_SOC_MSM_HOSTLESS_PCM=y
CONFIG_SND_SOC_SDM845=y
CONFIG_MSM_GLINK_SPI_XPRT=y
CONFIG_SOUNDWIRE=y
CONFIG_SND_SOC_QDSP6V2=y
CONFIG_SND_SOC_WCD_MBHC_ADC=y
CONFIG_QTI_PP=y
CONFIG_SND_HWDEP_ROUTING=y
CONFIG_DTS_EAGLE=y
CONFIG_DOLBY_DS2=y
CONFIG_DOLBY_LICENSE=y
CONFIG_DTS_SRS_TM=y
CONFIG_SND_SOC_MSM_STUB=y
CONFIG_MSM_AVTIMER=y
CONFIG_SND_SOC_MSM_HDMI_CODEC_RX=y

50
config/sdm845autoconf.h
View File

@@ -1,50 +0,0 @@
/*
* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define CONFIG_PINCTRL_WCD 1
#define CONFIG_SND_SOC_WCD934X 1
#define CONFIG_SND_SOC_WCD9XXX_V2 1
#define CONFIG_SND_SOC_WCD_CPE 1
#define CONFIG_SND_SOC_WCD_MBHC 1
#define CONFIG_SND_SOC_WSA881X 1
#define CONFIG_SND_SOC_WCD_SPI 1
#define CONFIG_SND_SOC_WCD934X_MBHC 1
#define CONFIG_SND_SOC_WCD934X_DSD 1
#define CONFIG_MSM_QDSP6V2_CODECS 1
#define CONFIG_MSM_ULTRASOUND 1
#define CONFIG_MSM_QDSP6_APRV2_GLINK 1
#define CONFIG_SND_SOC_MSM_QDSP6V2_INTF 1
#define CONFIG_MSM_ADSP_LOADER 1
#define CONFIG_REGMAP_SWR 1
#define CONFIG_MSM_QDSP6_SSR 1
#define CONFIG_MSM_QDSP6_PDR 1
#define CONFIG_MSM_QDSP6_NOTIFIER 1
#define CONFIG_SND_SOC_MSM_HOSTLESS_PCM 1
#define CONFIG_SND_SOC_SDM845 1
#define CONFIG_MSM_GLINK_SPI_XPRT 1
#define CONFIG_SOUNDWIRE 1
#define CONFIG_SOUNDWIRE_WCD_CTRL 1
#define CONFIG_SND_SOC_WCD_MBHC_ADC 1
#define CONFIG_SND_SOC_QDSP6V2 1
#define CONFIG_MSM_CDC_PINCTRL 1
#define CONFIG_QTI_PP 1
#define CONFIG_SND_HWDEP_ROUTING 1
#define CONFIG_DTS_EAGLE 1
#define CONFIG_DOLBY_DS2 1
#define CONFIG_DOLBY_LICENSE 1
#define CONFIG_DTS_SRS_TM 1
#define CONFIG_WCD9XXX_CODEC_CORE 1
#define CONFIG_SND_SOC_MSM_STUB 1
#define CONFIG_WCD_DSP_GLINK 1
#define CONFIG_MSM_AVTIMER 1
#define CONFIG_SND_SOC_MSM_HDMI_CODEC_RX 1

10
dsp/Android.mk
View File

@@ -3,14 +3,6 @@
# Assume no targets will be supported # Assume no targets will be supported
# Check if this driver needs be built for current target # Check if this driver needs be built for current target
ifeq ($(call is-board-platform,sdm845),true)
AUDIO_SELECT := CONFIG_SND_SOC_SDM845=m
endif
ifeq ($(call is-board-platform-in-list,msm8953 sdm670 qcs605),true)
AUDIO_SELECT := CONFIG_SND_SOC_SDM670=m
endif
ifeq ($(call is-board-platform,msmnile),true) ifeq ($(call is-board-platform,msmnile),true)
AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m
endif endif
@@ -21,7 +13,7 @@ endif
AUDIO_CHIPSET := audio AUDIO_CHIPSET := audio
# Build/Package only in case of supported target # Build/Package only in case of supported target
ifeq ($(call is-board-platform-in-list,msm8953 sdm845 sdm670 qcs605 msmnile $(MSMSTEPPE) $(TRINKET)),true) ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET)),true)
LOCAL_PATH := $(call my-dir) LOCAL_PATH := $(call my-dir)

15
dsp/Kbuild
View File

@@ -14,21 +14,6 @@ ifeq ($(KERNEL_BUILD), 1)
endif endif
ifeq ($(KERNEL_BUILD), 0) ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SDM845), y)
include $(AUDIO_ROOT)/config/sdm845auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm845autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM670), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM450), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SM6150), y) ifeq ($(CONFIG_ARCH_SM6150), y)
include $(AUDIO_ROOT)/config/sm6150auto.conf include $(AUDIO_ROOT)/config/sm6150auto.conf
export export

10
dsp/codecs/Android.mk
View File

@@ -3,14 +3,6 @@
# Assume no targets will be supported # Assume no targets will be supported
# Check if this driver needs be built for current target # Check if this driver needs be built for current target
ifeq ($(call is-board-platform,sdm845),true)
AUDIO_SELECT := CONFIG_SND_SOC_SDM845=m
endif
ifeq ($(call is-board-platform-in-list,msm8953 sdm670 qcs605),true)
AUDIO_SELECT := CONFIG_SND_SOC_SDM670=m
endif
ifeq ($(call is-board-platform,msmnile),true) ifeq ($(call is-board-platform,msmnile),true)
AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m
endif endif
@@ -21,7 +13,7 @@ endif
AUDIO_CHIPSET := audio AUDIO_CHIPSET := audio
# Build/Package only in case of supported target # Build/Package only in case of supported target
ifeq ($(call is-board-platform-in-list,msm8953 sdm845 sdm670 qcs605 msmnile $(MSMSTEPPE) $(TRINKET)),true) ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET)),true)
LOCAL_PATH := $(call my-dir) LOCAL_PATH := $(call my-dir)

16
dsp/codecs/Kbuild
View File

@@ -14,22 +14,6 @@ ifeq ($(KERNEL_BUILD), 1)
endif endif
ifeq ($(KERNEL_BUILD), 0) ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SDM845), y)
include $(AUDIO_ROOT)/config/sdm845auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm845autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM670), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM450), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SM6150), y) ifeq ($(CONFIG_ARCH_SM6150), y)
include $(AUDIO_ROOT)/config/sm6150auto.conf include $(AUDIO_ROOT)/config/sm6150auto.conf
export export

1158
include/asoc/wcd9360-registers.h
View File

File diff suppressed because it is too large Load Diff

10
ipc/Android.mk
View File

@@ -3,14 +3,6 @@
# Assume no targets will be supported # Assume no targets will be supported
# Check if this driver needs be built for current target # Check if this driver needs be built for current target
ifeq ($(call is-board-platform,sdm845),true)
AUDIO_SELECT := CONFIG_SND_SOC_SDM845=m
endif
ifeq ($(call is-board-platform-in-list,msm8953 sdm670 qcs605),true)
AUDIO_SELECT := CONFIG_SND_SOC_SDM670=m
endif
ifeq ($(call is-board-platform,msmnile),true) ifeq ($(call is-board-platform,msmnile),true)
AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m
endif endif
@@ -21,7 +13,7 @@ endif
AUDIO_CHIPSET := audio AUDIO_CHIPSET := audio
# Build/Package only in case of supported target # Build/Package only in case of supported target
ifeq ($(call is-board-platform-in-list,msm8953 sdm845 sdm670 qcs605 msmnile $(MSMSTEPPE) $(TRINKET)),true) ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET)),true)
LOCAL_PATH := $(call my-dir) LOCAL_PATH := $(call my-dir)

15
ipc/Kbuild
View File

@@ -15,21 +15,6 @@ ifeq ($(KERNEL_BUILD), 1)
endif endif
ifeq ($(KERNEL_BUILD), 0) ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SDM845), y)
include $(AUDIO_ROOT)/config/sdm845auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm845autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM670), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM450), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SM6150), y) ifeq ($(CONFIG_ARCH_SM6150), y)
include $(AUDIO_ROOT)/config/sm6150auto.conf include $(AUDIO_ROOT)/config/sm6150auto.conf
export export

12
soc/Android.mk
View File

@@ -3,14 +3,6 @@
# Assume no targets will be supported # Assume no targets will be supported
# Check if this driver needs be built for current target # Check if this driver needs be built for current target
ifeq ($(call is-board-platform,sdm845),true)
AUDIO_SELECT := CONFIG_SND_SOC_SDM845=m
endif
ifeq ($(call is-board-platform-in-list,msm8953 sdm670 qcs605),true)
AUDIO_SELECT := CONFIG_SND_SOC_SDM670=m
endif
ifeq ($(call is-board-platform,msmnile),true) ifeq ($(call is-board-platform,msmnile),true)
AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m AUDIO_SELECT := CONFIG_SND_SOC_SM8150=m
endif endif
@@ -21,7 +13,7 @@ endif
AUDIO_CHIPSET := audio AUDIO_CHIPSET := audio
# Build/Package only in case of supported target # Build/Package only in case of supported target
ifeq ($(call is-board-platform-in-list,msm8953 sdm845 sdm670 qcs605 msmnile $(MSMSTEPPE) $(TRINKET)),true) ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET)),true)
LOCAL_PATH := $(call my-dir) LOCAL_PATH := $(call my-dir)
@@ -48,7 +40,7 @@ KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM)
KBUILD_OPTIONS += $(AUDIO_SELECT) KBUILD_OPTIONS += $(AUDIO_SELECT)
########################################################### ###########################################################
ifeq ($(call is-board-platform-in-list,msm8953 sdm670 qcs605 $(MSMSTEPPE) $(TRINKET)),true) ifeq ($(call is-board-platform-in-list,$(MSMSTEPPE) $(TRINKET)),true)
include $(CLEAR_VARS) include $(CLEAR_VARS)
LOCAL_MODULE := $(AUDIO_CHIPSET)_pinctrl_lpi.ko LOCAL_MODULE := $(AUDIO_CHIPSET)_pinctrl_lpi.ko
LOCAL_MODULE_KBUILD_NAME := pinctrl_lpi_dlkm.ko LOCAL_MODULE_KBUILD_NAME := pinctrl_lpi_dlkm.ko

15
soc/Kbuild
View File

@@ -14,21 +14,6 @@ ifeq ($(KERNEL_BUILD), 1)
endif endif
ifeq ($(KERNEL_BUILD), 0) ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_SDM845), y)
include $(AUDIO_ROOT)/config/sdm845auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm845autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM670), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SDM450), y)
include $(AUDIO_ROOT)/config/sdm670auto.conf
export
INCS += -include $(AUDIO_ROOT)/config/sdm670autoconf.h
endif
ifeq ($(CONFIG_ARCH_SM8150), y) ifeq ($(CONFIG_ARCH_SM8150), y)
include $(AUDIO_ROOT)/config/sm8150auto.conf include $(AUDIO_ROOT)/config/sm8150auto.conf
export export