disp: msm: sde: update regdma offsets through target dtsi property

REG DMA programming occurs with respect to the sub-block top,
but all registers catalogued are with respect to sspp top.
This change adds support for handling the updated
sspp sub-block top and retains a default value for backward
compatibility.

Change-Id: I5a6364b17e817e38cd5afbcc67ed9df98c024008
Signed-off-by: Nilaan Gunabalachandran <[email protected]>

msm/sde/sde_hw_catalog.c

@@ -156,6 +156,8 @@
 #define SDE_UIDLE_MAX_FPS_60 60
 #define SDE_UIDLE_MAX_FPS_90 90
 
+#define SSPP_GET_REGDMA_BASE(blk_base, top_off) ((blk_base) >= (top_off) ?\
+		(blk_base) - (top_off) : (blk_base))
 
 /*************************************************************
  *  DTSI PROPERTY INDEX
@@ -268,6 +270,7 @@ enum {
 
 enum {
 	VIG_SUBBLOCK_INDEX,
+	VIG_TOP_OFF,
 	VIG_QSEED_OFF,
 	VIG_QSEED_LEN,
 	VIG_CSC_OFF,
@@ -293,6 +296,7 @@ enum {
 
 enum {
 	DMA_SUBBLOCK_INDEX,
+	DMA_TOP_OFF,
 	DMA_IGC_PROP,
 	DMA_GC_PROP,
 	DMA_DGM_INVERSE_PMA,
@@ -675,6 +679,8 @@ static struct sde_prop_type sspp_prop[] = {
 static struct sde_prop_type vig_prop[] = {
 	[VIG_SUBBLOCK_INDEX] = {VIG_SUBBLOCK_INDEX, "cell-index", false,
                         PROP_TYPE_U32},
+	[VIG_TOP_OFF] = {VIG_TOP_OFF, "qcom,sde-vig-top-off", false,
+			PROP_TYPE_U32},
 	[VIG_QSEED_OFF] = {VIG_QSEED_OFF, "qcom,sde-vig-qseed-off", false,
 			PROP_TYPE_U32},
 	[VIG_QSEED_LEN] = {VIG_QSEED_LEN, "qcom,sde-vig-qseed-size", false,
@@ -712,6 +718,8 @@ static struct sde_prop_type rgb_prop[] = {
 static struct sde_prop_type dma_prop[] = {
 	[DMA_SUBBLOCK_INDEX] = {DMA_SUBBLOCK_INDEX, "cell-index", false,
 			PROP_TYPE_U32},
+	[DMA_TOP_OFF] = {DMA_TOP_OFF, "qcom,sde-dma-top-off", false,
+			PROP_TYPE_U32},
 	[DMA_IGC_PROP] = {DMA_IGC_PROP, "qcom,sde-dma-igc", false,
 			PROP_TYPE_U32_ARRAY},
 	[DMA_GC_PROP] = {DMA_GC_PROP, "qcom,sde-dma-gc", false,
@@ -1370,6 +1378,7 @@ static bool _sde_sspp_setup_vcm(struct sde_sspp_cfg *sspp,
 		blk->len = 0;
 		set_bit(type, (unsigned long *) &sspp->features_ext);
 		blk->base = PROP_VALUE_ACCESS(props->values, prop, 0);
+		blk->regdma_base = SSPP_GET_REGDMA_BASE(blk->base, sspp->sblk->top_off);
 		snprintf(blk->name, SDE_HW_BLK_NAME_LEN, "%s%u", name,
 				sspp->id - SSPP_VIG0);
 		if (versioned)
@@ -1495,6 +1504,12 @@ static int _sde_sspp_setup_vigs(struct device_node *np,
 			set_bit(SDE_PERF_SSPP_QOS_8LVL, &sspp->perf_features);
 		vig_count++;
 
+		/* Obtain sub block top, or maintain backwards compatibility */
+		if (props[0] && props[0]->exists[VIG_TOP_OFF])
+			sblk->top_off = PROP_VALUE_ACCESS(props[0]->values, VIG_TOP_OFF, 0);
+		else
+			sblk->top_off = 0x200;
+
 		sblk->format_list = sde_cfg->vig_formats;
 		sblk->virt_format_list = sde_cfg->virt_vig_formats;
 		sblk->num_fp16_igc_blk = 0;
@@ -1545,6 +1560,8 @@ static int _sde_sspp_setup_vigs(struct device_node *np,
 					props[0]->values, VIG_QSEED_OFF, 0);
 			sblk->scaler_blk.len = PROP_VALUE_ACCESS(
 					props[0]->values, VIG_QSEED_LEN, 0);
+			sblk->scaler_blk.regdma_base = SSPP_GET_REGDMA_BASE(sblk->scaler_blk.base,
+					sblk->top_off);
 			snprintf(sblk->scaler_blk.name, SDE_HW_BLK_NAME_LEN,
 					"sspp_scaler%u", sspp->id - SSPP_VIG0);
 		}
@@ -1706,6 +1723,7 @@ static void _sde_sspp_setup_dgm(struct sde_sspp_cfg *sspp,
 	blk->len = 0;
 	set_bit(type, &sspp->features);
 	blk->base = PROP_VALUE_ACCESS(props->values, prop, 0);
+	blk->regdma_base = SSPP_GET_REGDMA_BASE(blk->base, sspp->sblk->top_off);
 	snprintf(blk->name, SDE_HW_BLK_NAME_LEN, "%s%u", name,
 			sspp->id - SSPP_DMA0);
 	if (versioned)
@@ -1784,6 +1802,12 @@ static int _sde_sspp_setup_dmas(struct device_node *np,
 			set_bit(SDE_PERF_SSPP_QOS_8LVL, &sspp->perf_features);
 		dma_count++;
 
+		/* Obtain sub block top, or maintain backwards compatibility */
+		if (props[0] && props[0]->exists[DMA_TOP_OFF])
+			sblk->top_off = PROP_VALUE_ACCESS(props[0]->values, DMA_TOP_OFF, 0);
+		else
+			sblk->top_off = 0x200;
+
 		sblk->num_igc_blk = dgm_count;
 		sblk->num_gc_blk = dgm_count;
 		sblk->num_dgm_csc_blk = dgm_count;

msm/sde/sde_hw_catalog.h

@@ -623,12 +623,14 @@ struct sde_src_blk {
 /**
  * struct sde_scaler_blk: Scaler information
  * @info:   HW register and features supported by this sub-blk
+ * @regdma_base: offset of this sub-block relative regdma top
  * @version: qseed block revision
  * @h_preload: horizontal preload
  * @v_preload: vertical preload
  */
 struct sde_scaler_blk {
 	SDE_HW_SUBBLK_INFO;
+	u32 regdma_base;
 	u32 version;
 	u32 h_preload;
 	u32 v_preload;
@@ -640,11 +642,13 @@ struct sde_csc_blk {
 
 /**
  * struct sde_pp_blk : Pixel processing sub-blk information
+ * @regdma_base: offset of this sub-block relative regdma top
  * @info:   HW register and features supported by this sub-blk
  * @version: HW Algorithm version
  */
 struct sde_pp_blk {
 	SDE_HW_SUBBLK_INFO;
+	u32 regdma_base;
 	u32 version;
 };
 
@@ -702,6 +706,7 @@ enum sde_qos_lut_usage {
  * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps
  * @max_per_pipe_bw_high: maximum allowable bandwidth of this pipe in kBps
  *				in case of no VFE
+ * @top_off: offset of the sub-block top register relative to sspp top
  * @src_blk:
  * @scaler_blk:
  * @csc_blk:
@@ -752,6 +757,7 @@ struct sde_sspp_sub_blks {
 	u32 smart_dma_priority;
 	u32 max_per_pipe_bw;
 	u32 max_per_pipe_bw_high;
+	u32 top_off;
 	struct sde_src_blk src_blk;
 	struct sde_scaler_blk scaler_blk;
 	struct sde_pp_blk csc_blk;

msm/sde/sde_hw_reg_dma_v1_color_proc.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <drm/msm_drm_pp.h>
@@ -15,8 +15,6 @@
 
 /* Reserve space of 128 words for LUT dma payload set-up */
 #define REG_DMA_HEADERS_BUFFER_SZ (sizeof(u32) * 128)
-#define REG_DMA_VIG_SWI_DIFF 0x200
-#define REG_DMA_DMA_SWI_DIFF 0x200
 
 #define VLUT_MEM_SIZE ((128 * sizeof(u32)) + REG_DMA_HEADERS_BUFFER_SZ)
 #define VLUT_LEN (128 * sizeof(u32))
@@ -2184,7 +2182,7 @@ static void vig_gamutv5_off(struct sde_hw_pipe *ctx, void *cfg)
 	struct sde_hw_reg_dma_ops *dma_ops;
 	struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
 	struct sde_reg_dma_kickoff_cfg kick_off;
-	u32 gamut_base = ctx->cap->sblk->gamut_blk.base - REG_DMA_VIG_SWI_DIFF;
+	u32 gamut_base = ctx->cap->sblk->gamut_blk.regdma_base;
 	enum sde_sspp_multirect_index idx = SDE_SSPP_RECT_0;
 
 	dma_ops = sde_reg_dma_get_ops();
@@ -2226,7 +2224,7 @@ void reg_dmav1_setup_vig_gamutv5(struct sde_hw_pipe *ctx, void *cfg)
 	struct sde_hw_reg_dma_ops *dma_ops;
 	struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
 	struct sde_reg_dma_kickoff_cfg kick_off;
-	u32 gamut_base = ctx->cap->sblk->gamut_blk.base - REG_DMA_VIG_SWI_DIFF;
+	u32 gamut_base = ctx->cap->sblk->gamut_blk.regdma_base;
 	bool use_2nd_memory = false;
 	enum sde_sspp_multirect_index idx = SDE_SSPP_RECT_0;
 
@@ -2341,7 +2339,7 @@ static void vig_igcv5_off(struct sde_hw_pipe *ctx, void *cfg)
 	struct sde_hw_reg_dma_ops *dma_ops;
 	struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
 	struct sde_reg_dma_kickoff_cfg kick_off;
-	u32 igc_base = ctx->cap->sblk->igc_blk[0].base - REG_DMA_VIG_SWI_DIFF;
+	u32 igc_base = ctx->cap->sblk->igc_blk[0].regdma_base;
 	enum sde_sspp_multirect_index idx = SDE_SSPP_RECT_0;
 
 	dma_ops = sde_reg_dma_get_ops();
@@ -2384,7 +2382,7 @@ static int reg_dmav1_setup_vig_igc_common(struct sde_hw_reg_dma_ops *dma_ops,
 	u32 offset = 0;
 	u32 lut_sel = 0, lut_enable = 0;
 	u32 *data = NULL, *data_ptr = NULL;
-	u32 igc_base = ctx->cap->sblk->igc_blk[0].base - REG_DMA_VIG_SWI_DIFF;
+	u32 igc_base = ctx->cap->sblk->igc_blk[0].regdma_base;
 	u32 *addr[IGC_TBL_NUM];
 
 	if (hw_cfg->len != sizeof(struct drm_msm_igc_lut)) {
@@ -2513,7 +2511,7 @@ void reg_dmav1_setup_vig_igcv6(struct sde_hw_pipe *ctx, void *cfg)
 	struct sde_hw_reg_dma_ops *dma_ops;
 	struct sde_reg_dma_kickoff_cfg kick_off;
 	struct sde_hw_cp_cfg *hw_cfg = cfg;
-	u32 igc_base = ctx->cap->sblk->igc_blk[0].base - REG_DMA_VIG_SWI_DIFF;
+	u32 igc_base = ctx->cap->sblk->igc_blk[0].regdma_base;
 	enum sde_sspp_multirect_index idx = SDE_SSPP_RECT_0;
 	struct drm_msm_igc_lut *igc_lut;
 	struct sde_reg_dma_setup_ops_cfg dma_write_cfg;
@@ -2668,13 +2666,11 @@ void reg_dmav1_setup_dma_igcv5(struct sde_hw_pipe *ctx, void *cfg,
 			((igc_lut->c2[2 * i + 1] & IGC_DATA_MASK) << 16);
 
 	if (idx == SDE_SSPP_RECT_SOLO || idx == SDE_SSPP_RECT_0) {
-		igc_base = ctx->cap->sblk->igc_blk[0].base -
-				REG_DMA_DMA_SWI_DIFF;
+		igc_base = ctx->cap->sblk->igc_blk[0].regdma_base;
 		igc_dither_off = igc_base + DMA_1D_LUT_IGC_DITHER_OFF;
 		igc_opmode_off = DMA_DGM_0_OP_MODE_OFF;
 	} else {
-		igc_base = ctx->cap->sblk->igc_blk[1].base -
-				REG_DMA_DMA_SWI_DIFF;
+		igc_base = ctx->cap->sblk->igc_blk[1].regdma_base;
 		igc_dither_off = igc_base + DMA_1D_LUT_IGC_DITHER_OFF;
 		igc_opmode_off = DMA_DGM_1_OP_MODE_OFF;
 	}
@@ -2809,10 +2805,10 @@ void reg_dmav1_setup_dma_gcv5(struct sde_hw_pipe *ctx, void *cfg,
 	}
 
 	if (idx == SDE_SSPP_RECT_SOLO || idx == SDE_SSPP_RECT_0) {
-		gc_base = ctx->cap->sblk->gc_blk[0].base - REG_DMA_DMA_SWI_DIFF;
+		gc_base = ctx->cap->sblk->gc_blk[0].regdma_base;
 		gc_opmode_off = DMA_DGM_0_OP_MODE_OFF;
 	} else {
-		gc_base = ctx->cap->sblk->gc_blk[1].base - REG_DMA_DMA_SWI_DIFF;
+		gc_base = ctx->cap->sblk->gc_blk[1].regdma_base;
 		gc_opmode_off = DMA_DGM_1_OP_MODE_OFF;
 	}
 
@@ -3092,7 +3088,7 @@ void reg_dmav1_setup_vig_qseed3(struct sde_hw_pipe *ctx,
 		return;
 	}
 
-	offset = ctx->cap->sblk->scaler_blk.base - REG_DMA_VIG_SWI_DIFF;
+	offset = ctx->cap->sblk->scaler_blk.regdma_base;
 	dma_ops = sde_reg_dma_get_ops();
 	dma_ops->reset_reg_dma_buf(sspp_buf[idx][QSEED][ctx->idx]);
 
@@ -4321,7 +4317,7 @@ void reg_dmav2_setup_vig_gamutv61(struct sde_hw_pipe *ctx, void *cfg)
 	int rc;
 	enum sde_sspp_multirect_index idx = SDE_SSPP_RECT_0;
 
-	u32 gamut_base = ctx->cap->sblk->gamut_blk.base - REG_DMA_VIG_SWI_DIFF;
+	u32 gamut_base = ctx->cap->sblk->gamut_blk.regdma_base;
 	u32 i, j, k = 0, len, table_select = 0;
 	u32 op_mode, scale_offset, scale_tbl_offset, transfer_size_bytes;
 	u16 *data;