msm: camera: isp: Add top irq mask in header files

This commit adds top irq mask in CSID register files. It allows
to change the bitmask as per chip revisions.
Eepoch masks are corrected. need_separate_base flag is removed
as it is no longer used.

CRs-Fixed: 2948116
Change-Id: Id93751818b7abb980d4d42456f6604d9be0ea22a
Signed-off-by: Gaurav Jindal <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid680.h

@@ -79,7 +79,7 @@ static struct cam_irq_controller_reg_info cam_ife_csid_680_irq_reg_info = {
 	.global_clear_bitmask = 0x00000001,
 };
 
-static struct cam_irq_register_set cam_ife_csid_680_buf_done_irq_reg_set[9] = {
+static struct cam_irq_register_set cam_ife_csid_680_buf_done_irq_reg_set[1] = {
 	{
 		.mask_reg_offset   = 0x00000090,
 		.clear_reg_offset  = 0x00000094,
@@ -204,6 +204,9 @@ static struct cam_ife_csid_ver2_pxl_reg_info
 		.non_fatal_err_mask               = 0x10000000,
 		.camif_irq_mask                   = 0x800000,
 		.rup_aup_mask                     = 0x10001,
+		.top_irq_mask                     = 0x10,
+		.epoch0_shift_val                 = 16,
+		.epoch1_shift_val                 = 0,
 };
 
 static struct cam_ife_csid_ver2_pxl_reg_info
@@ -299,6 +302,9 @@ static struct cam_ife_csid_ver2_pxl_reg_info
 		.fatal_err_mask                   = 0x186004,
 		.non_fatal_err_mask               = 0x10000000,
 		.rup_aup_mask                     = 0x40004,
+		.top_irq_mask                     = 0x40,
+		.epoch0_shift_val                 = 16,
+		.epoch1_shift_val                 = 0,
 };
 
 static struct cam_ife_csid_ver2_rdi_reg_info
@@ -392,6 +398,9 @@ static struct cam_ife_csid_ver2_rdi_reg_info
 		.non_fatal_err_mask               = 0x10000000,
 		.camif_irq_mask                   = 0x800000,
 		.rup_aup_mask                     = 0x100010,
+		.top_irq_mask                     = 0x100,
+		.epoch0_shift_val                 = 16,
+		.epoch1_shift_val                 = 0,
 };
 
 static struct cam_ife_csid_ver2_rdi_reg_info
@@ -485,6 +494,9 @@ static struct cam_ife_csid_ver2_rdi_reg_info
 		.non_fatal_err_mask               = 0x10000000,
 		.camif_irq_mask                   = 0x800000,
 		.rup_aup_mask                     = 0x200020,
+		.top_irq_mask                     = 0x200,
+		.epoch0_shift_val                 = 16,
+		.epoch1_shift_val                 = 0,
 };
 
 static struct cam_ife_csid_ver2_rdi_reg_info
@@ -578,6 +590,9 @@ static struct cam_ife_csid_ver2_rdi_reg_info
 		.non_fatal_err_mask               = 0x10000000,
 		.camif_irq_mask                   = 0x800000,
 		.rup_aup_mask                     = 0x400040,
+		.top_irq_mask                     = 0x400,
+		.epoch0_shift_val                 = 16,
+		.epoch1_shift_val                 = 0,
 };
 
 static struct cam_ife_csid_ver2_rdi_reg_info
@@ -671,6 +686,9 @@ static struct cam_ife_csid_ver2_rdi_reg_info
 		.non_fatal_err_mask               = 0x10000000,
 		.camif_irq_mask                   = 0x800000,
 		.rup_aup_mask                     = 0x800080,
+		.top_irq_mask                     = 0x800,
+		.epoch0_shift_val                 = 16,
+		.epoch1_shift_val                 = 0,
 };
 
 static struct cam_ife_csid_ver2_rdi_reg_info
@@ -764,6 +782,9 @@ static struct cam_ife_csid_ver2_rdi_reg_info
 		.non_fatal_err_mask              = 0x10000000,
 		.camif_irq_mask                  = 0x800000,
 		.rup_aup_mask                    = 0x1000100,
+		.top_irq_mask                    = 0x1000,
+		.epoch0_shift_val                = 16,
+		.epoch1_shift_val                = 0,
 };
 
 static struct cam_ife_csid_csi2_rx_reg_info
@@ -833,6 +854,7 @@ static struct cam_ife_csid_csi2_rx_reg_info
 		.fatal_err_mask                  = 0x097A000,
 		.part_fatal_err_mask             = 0x1081800,
 		.non_fatal_err_mask              = 0x0200000,
+		.top_irq_mask                    = 0x4,
 };
 
 static struct cam_ife_csid_ver2_common_reg_info
@@ -902,18 +924,18 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.rst_cmd_sw_reset_complete_val           = 0x2,
 	.rst_cmd_irq_ctrl_only_val               = 0x4,
 	.timestamp_strobe_val                    = 0x2,
-	.top_reset_irq_shift_val                 = 0,
 	.rst_location_shift_val                  = 4,
 	.rst_mode_shift_val                      = 0,
 	.epoch_div_factor                        = 4,
 	.global_reset                            = 1,
 	.rup_supported                           = 1,
 	.only_master_rup                         = 1,
-	.need_separate_base                      = 1,
 	.format_measure_height_mask_val          = 0xFFFF,
 	.format_measure_height_shift_val         = 0x10,
 	.format_measure_width_mask_val           = 0xFFFF,
 	.format_measure_width_shift_val          = 0x0,
+	.top_reset_irq_mask                      = 0x1,
+	.top_buf_done_irq_mask                   = 0x2000,
 };
 
 static struct cam_ife_csid_ver2_top_reg_info

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.h

@@ -205,6 +205,7 @@ struct cam_ife_csid_csi2_rx_reg_info {
 	uint32_t part_fatal_err_mask;
 	uint32_t non_fatal_err_mask;
 	uint32_t debug_irq_mask;
+	uint32_t top_irq_mask;
 };
 
 /*

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c

@@ -1690,7 +1690,6 @@ int cam_ife_csid_ver2_get_hw_caps(void *hw_priv,
 	hw_caps->global_reset_en = csid_reg->cmn_reg->global_reset;
 	hw_caps->rup_en = csid_reg->cmn_reg->rup_supported;
 	hw_caps->only_master_rup = csid_reg->cmn_reg->only_master_rup;
-	hw_caps->need_separate_base = csid_reg->cmn_reg->need_separate_base;
 	hw_caps->is_lite = soc_private->is_ife_csid_lite;
 
 	CAM_DBG(CAM_ISP,
@@ -2774,7 +2773,6 @@ static int cam_ife_csid_ver2_program_rdi_path(
 	void __iomem *mem_base;
 	uint32_t val = 0;
 	uint32_t irq_mask[CAM_IFE_CSID_IRQ_REG_MAX] = {0};
-	uint32_t top_irq_mask = 0;
 	struct cam_ife_csid_ver2_path_cfg *path_cfg;
 
 	rc = cam_ife_csid_ver2_init_config_rdi_path(
@@ -2813,7 +2811,8 @@ static int cam_ife_csid_ver2_program_rdi_path(
 			path_reg->stripe_loc_shift_val);
 
 		cam_io_w_mb(val, mem_base + path_reg->camif_frame_cfg_addr);
-		cam_io_w_mb(path_cfg->camif_data.epoch0,
+		cam_io_w_mb(path_cfg->camif_data.epoch0 <<
+			path_reg->epoch0_shift_val,
 			mem_base + path_reg->epoch_irq_cfg_addr);
 	}
 
@@ -2836,25 +2835,8 @@ static int cam_ife_csid_ver2_program_rdi_path(
 	path_cfg->irq_reg_idx =
 		cam_ife_csid_convert_res_to_irq_reg(res->res_id);
 
-	switch (res->res_id) {
-	case CAM_IFE_PIX_PATH_RES_RDI_0:
-		top_irq_mask = IFE_CSID_VER2_TOP_IRQ_STATUS_RDI0;
-		break;
-	case CAM_IFE_PIX_PATH_RES_RDI_1:
-		top_irq_mask = IFE_CSID_VER2_TOP_IRQ_STATUS_RDI1;
-		break;
-	case CAM_IFE_PIX_PATH_RES_RDI_2:
-		top_irq_mask = IFE_CSID_VER2_TOP_IRQ_STATUS_RDI2;
-		break;
-	case CAM_IFE_PIX_PATH_RES_RDI_3:
-		top_irq_mask = IFE_CSID_VER2_TOP_IRQ_STATUS_RDI3;
-		break;
-	case CAM_IFE_PIX_PATH_RES_RDI_4:
-		top_irq_mask = IFE_CSID_VER2_TOP_IRQ_STATUS_RDI4;
-		break;
-	}
+	irq_mask[CAM_IFE_CSID_IRQ_REG_TOP] = path_reg->top_irq_mask;
 
-	irq_mask[CAM_IFE_CSID_IRQ_REG_TOP] = top_irq_mask;
 	irq_mask[path_cfg->irq_reg_idx] = val;
 	path_cfg->irq_handle = cam_irq_controller_subscribe_irq(
 		csid_hw->csid_irq_controller,
@@ -2928,7 +2910,6 @@ static int cam_ife_csid_ver2_program_ipp_path(
 	void __iomem *mem_base;
 	struct cam_ife_csid_ver2_path_cfg *path_cfg;
 	uint32_t irq_mask[CAM_IFE_CSID_IRQ_REG_MAX] = {0};
-	uint32_t top_irq_mask = 0;
 
 	rc = cam_ife_csid_ver2_init_config_pxl_path(
 		csid_hw, res);
@@ -2961,14 +2942,13 @@ static int cam_ife_csid_ver2_program_ipp_path(
 			 path_reg->stripe_loc_shift_val);
 
 	cam_io_w_mb(val, mem_base + path_reg->camif_frame_cfg_addr);
-	cam_io_w_mb(path_cfg->camif_data.epoch0,
+	cam_io_w_mb(path_cfg->camif_data.epoch0 << path_reg->epoch0_shift_val,
 		mem_base + path_reg->epoch_irq_cfg_addr);
 
 	CAM_DBG(CAM_ISP, "csid[%d] frame_cfg 0x%x epoch_cfg 0x%x",
 			csid_hw->hw_intf->hw_idx,
 			val, path_cfg->camif_data.epoch0);
 
-	top_irq_mask = IFE_CSID_VER2_TOP_IRQ_STATUS_IPP0;
 	path_cfg->irq_reg_idx = cam_ife_csid_get_rt_irq_idx(
 			CAM_IFE_CSID_IRQ_REG_IPP,
 			csid_reg->cmn_reg->num_pix,
@@ -2982,7 +2962,7 @@ static int cam_ife_csid_ver2_program_ipp_path(
 		val |= path_reg->camif_irq_mask;
 	}
 
-	irq_mask[CAM_IFE_CSID_IRQ_REG_TOP] = top_irq_mask;
+	irq_mask[CAM_IFE_CSID_IRQ_REG_TOP] = path_reg->top_irq_mask;
 	irq_mask[path_cfg->irq_reg_idx] = val;
 	path_cfg->irq_handle = cam_irq_controller_subscribe_irq(
 				    csid_hw->csid_irq_controller,
@@ -3145,7 +3125,6 @@ static int cam_ife_csid_ver2_program_ppp_path(
 	uint32_t  val = 0;
 	struct cam_ife_csid_ver2_path_cfg *path_cfg;
 	uint32_t irq_mask[CAM_IFE_CSID_IRQ_REG_MAX] = {0};
-	uint32_t top_irq_mask = 0;
 	void __iomem *mem_base;
 
 	rc = cam_ife_csid_ver2_init_config_pxl_path(
@@ -3179,10 +3158,9 @@ static int cam_ife_csid_ver2_program_ppp_path(
 			 path_reg->stripe_loc_shift_val);
 
 	cam_io_w_mb(val, mem_base + path_reg->camif_frame_cfg_addr);
-	cam_io_w_mb(path_cfg->camif_data.epoch0, mem_base +
-		path_reg->epoch_irq_cfg_addr);
+	cam_io_w_mb(path_cfg->camif_data.epoch0 << path_reg->epoch0_shift_val,
+		mem_base + path_reg->epoch_irq_cfg_addr);
 
-	top_irq_mask = IFE_CSID_VER2_TOP_IRQ_STATUS_PPP0;
 	path_cfg->irq_reg_idx = cam_ife_csid_get_rt_irq_idx(
 				CAM_IFE_CSID_IRQ_REG_PPP,
 				csid_reg->cmn_reg->num_pix,
@@ -3221,8 +3199,8 @@ static int cam_ife_csid_ver2_program_ppp_path(
 	val = csid_hw->debug_info.path_mask;
 
 
-	irq_mask[CAM_IFE_CSID_IRQ_REG_TOP] = top_irq_mask;
 	irq_mask[path_cfg->irq_reg_idx] = val;
+	irq_mask[CAM_IFE_CSID_IRQ_REG_TOP] = path_reg->top_irq_mask;
 	path_cfg->irq_handle = cam_irq_controller_subscribe_irq(
 					csid_hw->csid_irq_controller,
 					CAM_IRQ_PRIORITY_1,
@@ -3398,7 +3376,7 @@ static int cam_ife_csid_ver2_enable_csi2(struct cam_ife_csid_ver2_hw *csid_hw)
 		csid_hw->hw_intf->hw_idx, val);
 	val = 0;
 
-	irq_mask[CAM_IFE_CSID_IRQ_REG_TOP] = IFE_CSID_VER2_TOP_IRQ_STATUS_RX0;
+	irq_mask[CAM_IFE_CSID_IRQ_REG_TOP] = csi2_reg->top_irq_mask;
 
 	if (csid_hw->debug_info.rx_mask) {
 		irq_mask[CAM_IFE_CSID_IRQ_REG_RX] =  csid_hw->debug_info.rx_mask;
@@ -3577,7 +3555,7 @@ static int cam_ife_csid_ver2_enable_core(struct cam_ife_csid_ver2_hw *csid_hw)
 		goto err;
 	}
 
-	irq_mask[CAM_IFE_CSID_IRQ_REG_TOP] = IFE_CSID_VER2_TOP_IRQ_STATUS_RST;
+	irq_mask[CAM_IFE_CSID_IRQ_REG_TOP] = csid_reg->cmn_reg->top_reset_irq_mask;
 
 	csid_hw->reset_irq_handle = cam_irq_controller_subscribe_irq(
 		csid_hw->csid_irq_controller,
@@ -3656,7 +3634,7 @@ static int cam_ife_csid_ver2_enable_hw(
 	val = cam_io_r_mb(mem_base + csid_reg->cmn_reg->hw_version_addr);
 
 	buf_done_irq_mask[CAM_IFE_CSID_IRQ_REG_TOP] =
-			IFE_CSID_VER2_TOP_IRQ_STATUS_BUF_DONE;
+		csid_reg->cmn_reg->top_buf_done_irq_mask;
 	csid_hw->buf_done_irq_handle = cam_irq_controller_subscribe_irq(
 		csid_hw->csid_irq_controller,
 		CAM_IRQ_PRIORITY_4,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h

@@ -74,18 +74,6 @@
 #define IFE_CSID_VER2_CUST_NODE_IDX_1                      0x2
 #define IFE_CSID_VER2_CUST_NODE_IDX_2                      0x4
 
-#define IFE_CSID_VER2_TOP_IRQ_STATUS_RST                  BIT(0)
-#define IFE_CSID_VER2_TOP_IRQ_STATUS_RX0                  BIT(2)
-#define IFE_CSID_VER2_TOP_IRQ_STATUS_RX1                  BIT(3)
-#define IFE_CSID_VER2_TOP_IRQ_STATUS_IPP0                 BIT(4)
-#define IFE_CSID_VER2_TOP_IRQ_STATUS_IPP1                 BIT(5)
-#define IFE_CSID_VER2_TOP_IRQ_STATUS_PPP0                 BIT(6)
-#define IFE_CSID_VER2_TOP_IRQ_STATUS_PPP1                 BIT(7)
-#define IFE_CSID_VER2_TOP_IRQ_STATUS_RDI0                 BIT(8)
-#define IFE_CSID_VER2_TOP_IRQ_STATUS_RDI1                 BIT(9)
-#define IFE_CSID_VER2_TOP_IRQ_STATUS_RDI2                 BIT(10)
-#define IFE_CSID_VER2_TOP_IRQ_STATUS_RDI3                 BIT(11)
-#define IFE_CSID_VER2_TOP_IRQ_STATUS_RDI4                 BIT(12)
 #define IFE_CSID_VER2_TOP_IRQ_STATUS_BUF_DONE             BIT(13)
 
 enum cam_ife_csid_ver2_input_core_sel {
@@ -317,8 +305,11 @@ struct cam_ife_csid_ver2_rdi_reg_info {
 	uint32_t pix_pattern_shift;
 	uint32_t camif_irq_mask;
 	uint32_t rup_aup_mask;
+	uint32_t top_irq_mask;
 	uint32_t epoch0_cfg_val;
 	uint32_t epoch1_cfg_val;
+	uint32_t epoch0_shift_val;
+	uint32_t epoch1_shift_val;
 };
 
 struct cam_ife_csid_ver2_pxl_reg_info {
@@ -423,6 +414,8 @@ struct cam_ife_csid_ver2_pxl_reg_info {
 	uint32_t pix_pattern_shift_val;
 	uint32_t epoch0_cfg_val;
 	uint32_t epoch1_cfg_val;
+	uint32_t epoch0_shift_val;
+	uint32_t epoch1_shift_val;
 	/* config Values */
 	uint32_t resume_frame_boundary;
 	uint32_t overflow_ctrl_mode_val;
@@ -435,6 +428,7 @@ struct cam_ife_csid_ver2_pxl_reg_info {
 	uint32_t non_fatal_err_mask;
 	uint32_t camif_irq_mask;
 	uint32_t rup_aup_mask;
+	uint32_t top_irq_mask;
 };
 
 struct cam_ife_csid_ver2_common_reg_info {
@@ -535,7 +529,6 @@ struct cam_ife_csid_ver2_common_reg_info {
 	uint32_t global_reset;
 	uint32_t rup_supported;
 	uint32_t only_master_rup;
-	uint32_t need_separate_base;
 	/* Masks */
 	uint32_t pxl_cnt_mask;
 	uint32_t line_cnt_mask;
@@ -559,7 +552,9 @@ struct cam_ife_csid_ver2_common_reg_info {
 	uint32_t rdi_irq_mask_all;
 	uint32_t ppp_irq_mask_all;
 	uint32_t udi_irq_mask_all;
-	uint32_t top_reset_irq_shift_val;
+	uint32_t top_err_irq_mask;
+	uint32_t top_reset_irq_mask;
+	uint32_t top_buf_done_irq_mask;
 	uint32_t epoch_div_factor;
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite680.h

@@ -141,11 +141,11 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.rst_cmd_sw_reset_complete_val                = 0x2,
 	.rst_cmd_irq_ctrl_only_val                    = 0x4,
 	.timestamp_strobe_val                         = 0x2,
-	.top_reset_irq_shift_val                      = 0,
+	.top_reset_irq_mask                           = 0x1,
+	.top_buf_done_irq_mask                        = 0x2000,
 	.global_reset                                 = 1,
 	.rup_supported                                = 1,
 	.only_master_rup                              = 1,
-	.need_separate_base                           = 1,
 };
 
 static struct cam_ife_csid_csi2_rx_reg_info
@@ -305,6 +305,7 @@ static struct cam_ife_csid_ver2_pxl_reg_info
 		.non_fatal_err_mask               = 0x10080000,
 		.camif_irq_mask                   = 0x800000,
 		.rup_aup_mask                     = 0x10001,
+		.top_irq_mask                     = 0x10,
 };
 
 static struct cam_ife_csid_ver2_rdi_reg_info
@@ -392,6 +393,9 @@ static struct cam_ife_csid_ver2_rdi_reg_info
 		.non_fatal_err_mask             = 0x10080000,
 		.camif_irq_mask                 = 0x800000,
 		.rup_aup_mask                   = 0x100010,
+		.top_irq_mask                   = 0x100,
+		.epoch0_shift_val               = 16,
+		.epoch1_shift_val               = 0,
 };
 
 static struct cam_ife_csid_ver2_rdi_reg_info
@@ -478,6 +482,9 @@ static struct cam_ife_csid_ver2_rdi_reg_info
 		.non_fatal_err_mask             = 0x10080000,
 		.camif_irq_mask                 = 0x800000,
 		.rup_aup_mask                   = 0x200020,
+		.top_irq_mask                   = 0x200,
+		.epoch0_shift_val               = 16,
+		.epoch1_shift_val               = 0,
 };
 
 static struct cam_ife_csid_ver2_rdi_reg_info
@@ -564,6 +571,9 @@ static struct cam_ife_csid_ver2_rdi_reg_info
 		.non_fatal_err_mask             = 0x10080000,
 		.camif_irq_mask                 = 0x800000,
 		.rup_aup_mask                   = 0x400040,
+		.top_irq_mask                   = 0x400,
+		.epoch0_shift_val               = 16,
+		.epoch1_shift_val               = 0,
 };
 
 static struct cam_ife_csid_ver2_rdi_reg_info
@@ -650,6 +660,9 @@ static struct cam_ife_csid_ver2_rdi_reg_info
 		.non_fatal_err_mask             = 0x10080000,
 		.camif_irq_mask                 = 0x800000,
 		.rup_aup_mask                   = 0x800080,
+		.top_irq_mask                   = 0x800,
+		.epoch0_shift_val               = 16,
+		.epoch1_shift_val               = 0,
 };
 
 static struct cam_ife_csid_ver2_reg_info cam_ife_csid_lite_680_reg_info = {

drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h

@@ -65,7 +65,6 @@ enum cam_ife_cid_res_id {
  * @global_reset_en:      flag to indicate if global reset is enabled
  * @rup_en:               flag to indicate if rup is on csid side
  * @only_master_rup:      flag to indicate if only master RUP
- * @need_separate_base:   flag to indicate is separate base is needed
  */
 struct cam_ife_csid_hw_caps {
 	uint32_t      num_rdis;
@@ -78,7 +77,6 @@ struct cam_ife_csid_hw_caps {
 	bool          global_reset_en;
 	bool          rup_en;
 	bool          only_master_rup;
-	bool          need_separate_base;
 };
 
 struct cam_isp_out_port_generic_info {