qcacmn: Add support for Waikiki HAL Tx
Added HAL Tx specific function to support Waikiki Tx. Change-Id: I7ded253739c91ab19490425b3ddd333a86f237c8
This commit is contained in:
Chaithanya Garrepalli
committed by
Madan Koyyalamudi
Madan Koyyalamudi
parent
7ccb73b31f
commit
d5006a849b
@@ -199,18 +199,34 @@ static inline void hal_tx_desc_sync(void *hal_tx_desc_cached,
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qdf_mem_copy(hw_desc, hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
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}
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/**
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* hal_tx_desc_set_vdev_id - set vdev id to the descriptor to Hardware
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* @hal_tx_des_cached: Cached descriptor that software maintains
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* @vdev_id: vdev id
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*/
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static inline void hal_tx_desc_set_vdev_id(void *desc, uint8_t vdev_id)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, VDEV_ID) |=
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HAL_TX_SM(TCL_DATA_CMD, VDEV_ID, vdev_id);
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}
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/**
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* hal_tx_desc_set_bank_id - set bank id to the descriptor to Hardware
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* @hal_tx_des_cached: Cached descriptor that software maintains
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* @bank_id: bank id
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*/
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static inline void hal_tx_desc_set_bank_id(void *desc, uint8_t bank_id)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, BANK_ID) |=
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HAL_TX_SM(TCL_DATA_CMD, BANK_ID, bank_id);
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}
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/**
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* hal_tx_desc_set_tcl_cmd_type - set tcl command type to the descriptor
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* to Hardware
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* @hal_tx_des_cached: Cached descriptor that software maintains
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* @tcl_cmd_type: tcl command type
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*/
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static inline void
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hal_tx_desc_set_tcl_cmd_type(void *desc, uint8_t tcl_cmd_type)
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{
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@@ -218,6 +234,50 @@ hal_tx_desc_set_tcl_cmd_type(void *desc, uint8_t tcl_cmd_type)
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HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_TYPE, tcl_cmd_type);
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}
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/**
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* hal_tx_desc_set_lmac_id_be - set lmac id to the descriptor to Hardware
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* @hal_soc_hdl: hal soc handle
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* @hal_tx_des_cached: Cached descriptor that software maintains
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* @lmac_id: lmac id
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*/
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static inline void
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hal_tx_desc_set_lmac_id_be(hal_soc_handle_t hal_soc_hdl, void *desc,
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uint8_t lmac_id)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, PMAC_ID) |=
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HAL_TX_SM(TCL_DATA_CMD, PMAC_ID, lmac_id);
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}
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/**
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* hal_tx_desc_set_search_index_be - set search index to the
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* descriptor to Hardware
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* @hal_soc_hdl: hal soc handle
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* @hal_tx_des_cached: Cached descriptor that software maintains
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* @search_index: search index
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*/
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static inline void
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hal_tx_desc_set_search_index_be(hal_soc_handle_t hal_soc_hdl, void *desc,
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uint32_t search_index)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, SEARCH_INDEX) |=
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HAL_TX_SM(TCL_DATA_CMD, SEARCH_INDEX, search_index);
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}
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/**
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* hal_tx_desc_set_cache_set_num - set cache set num to the
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* descriptor to Hardware
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* @hal_soc_hdl: hal soc handle
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* @hal_tx_des_cached: Cached descriptor that software maintains
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* @cache_num: cache number
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*/
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static inline void
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hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl, void *desc,
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uint8_t cache_num)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD, CACHE_SET_NUM) |=
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HAL_TX_SM(TCL_DATA_CMD, CACHE_SET_NUM, cache_num);
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}
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/*---------------------------------------------------------------------------
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* WBM Descriptor accessor APIs for Tx completions
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* ---------------------------------------------------------------------------
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@@ -392,4 +452,101 @@ hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl,
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HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
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}
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#define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK
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#define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT
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#define RBM_PPE2TCL_OFFSET \
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(HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2)
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#define RBM_TCL_CMD_CREDIT_OFFSET \
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(HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2)
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/**
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* hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id
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* @hal_soc: HAL SoC context
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* @hal_ring_hdl: Source ring pointer
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* @rbm_id: return buffer manager ring id
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*
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* Return: void
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*/
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static inline void
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hal_tx_config_rbm_mapping_be(struct hal_soc *hal_soc,
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hal_ring_handle_t hal_ring_hdl,
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uint8_t rbm_id)
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{
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struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
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uint32_t reg_addr = 0;
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uint32_t reg_val = 0;
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uint32_t val = 0;
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uint8_t ring_num;
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enum hal_ring_type ring_type;
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ring_type = srng->ring_type;
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ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id;
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ring_num = ring_num - srng->ring_id;
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reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE);
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if (ring_type == PPE2TCL)
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ring_num = ring_num + RBM_PPE2TCL_OFFSET;
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else if (ring_type == TCL_CMD_CREDIT)
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ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET;
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/* get current value stored in register address */
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val = HAL_REG_READ(hal_soc, reg_addr);
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/* mask out other stored value */
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val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num)));
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reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) <<
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(RBM_MAPPING_SHFT * ring_num));
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/* write rbm mapped value to register address */
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HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
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}
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/**
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* hal_tx_desc_set_buf_addr_be - Fill Buffer Address information in Tx Desc
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* @desc: Handle to Tx Descriptor
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* @paddr: Physical Address
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* @pool_id: Return Buffer Manager ID
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* @desc_id: Descriptor ID
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* @type: 0 - Address points to a MSDU buffer
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* 1 - Address points to MSDU extension descriptor
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*
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* Return: void
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*/
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static inline void
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hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc,
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dma_addr_t paddr, uint8_t rbm_id,
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uint32_t desc_id, uint8_t type)
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{
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/* Set buffer_addr_info.buffer_addr_31_0 */
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HAL_SET_FLD(desc, TCL_DATA_CMD,
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BUF_ADDR_INFO_BUFFER_ADDR_31_0) =
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HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_31_0, paddr);
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/* Set buffer_addr_info.buffer_addr_39_32 */
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HAL_SET_FLD(desc, TCL_DATA_CMD,
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BUF_ADDR_INFO_BUFFER_ADDR_39_32) |=
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HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_39_32,
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(((uint64_t)paddr) >> 32));
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/* Set buffer_addr_info.return_buffer_manager = rbm id */
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HAL_SET_FLD(desc, TCL_DATA_CMD,
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BUF_ADDR_INFO_RETURN_BUFFER_MANAGER) |=
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HAL_TX_SM(TCL_DATA_CMD,
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BUF_ADDR_INFO_RETURN_BUFFER_MANAGER, rbm_id);
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/* Set buffer_addr_info.sw_buffer_cookie = desc_id */
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HAL_SET_FLD(desc, TCL_DATA_CMD,
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BUF_ADDR_INFO_SW_BUFFER_COOKIE) |=
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HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_SW_BUFFER_COOKIE,
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desc_id);
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/* Set Buffer or Ext Descriptor Type */
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HAL_SET_FLD(desc, TCL_DATA_CMD,
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BUF_OR_EXT_DESC_TYPE) |=
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HAL_TX_SM(TCL_DATA_CMD, BUF_OR_EXT_DESC_TYPE, type);
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}
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#endif /* _HAL_BE_TX_H_ */
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