samsung-sm8650/android_kernel_samsung_sm8650-modules
1
0
Bifurcation 0
Code Tickets Demandes d'ajout Actions Paquets Projets Publications Wiki Activité

qcacmn: Add support for Waikiki HAL Tx

Parcourir la source 
Added HAL Tx specific function to support Waikiki Tx.

Change-Id: I7ded253739c91ab19490425b3ddd333a86f237c8
Cette révision appartient à :
Chaithanya Garrepalli
2021-08-12 17:14:34 +05:30
révisé par Madan Koyyalamudi
Parent 7ccb73b31f
révision d5006a849b
12 fichiers modifiés avec 471 ajouts et 282 suppressions
Télécharger le Fichier Patch Télécharger le Fichier des Différences Développer tous les fichiers Réduire tous les fichiers

18
hal/wifi3.0/be/hal_be_api.h
Voir le fichier

@@ -54,24 +54,6 @@ RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET))
void hal_reo_setup_generic_be(struct hal_soc *soc,
void *reoparams);
void hal_tx_desc_set_search_index_generic_be(void *desc, uint32_t search_index);
/**
* hal_tx_desc_set_cache_set_num_generic_be - Set the cache-set-num value
* @desc: Handle to Tx Descriptor
* @cache_num: Cache set number that should be used to cache the index
* based search results, for address and flow search.
* This value should be equal to LSB four bits of the hash value
* of match data, in case of search index points to an entry
* which may be used in content based search also. The value can
* be anything when the entry pointed by search index will not be
* used for content based search.
*
* Return: void
*/
void hal_tx_desc_set_cache_set_num_generic_be(void *desc,
uint8_t cache_num);
/**
* hal_rx_msdu_ext_desc_info_get_ptr_be() - Get the msdu extension
* descriptor pointer.

68
hal/wifi3.0/be/hal_be_generic_api.c
Voir le fichier

@@ -188,30 +188,6 @@ void *hal_rx_msdu_ext_desc_info_get_ptr_be(void *msdu_details_ptr)
return HAL_RX_MSDU_EXT_DESC_INFO_GET(msdu_details_ptr);
}
#ifdef TCL_DATA_CMD_SEARCH_INDEX_OFFSET
void hal_tx_desc_set_search_index_generic_be(void *desc, uint32_t search_index)
{
HAL_SET_FLD(desc, TCL_DATA_CMD, SEARCH_INDEX) |=
HAL_TX_SM(TCL_DATA_CMD, SEARCH_INDEX, search_index);
}
#else
void hal_tx_desc_set_search_index_generic_be(void *desc, uint32_t search_index)
{
}
#endif
#ifdef TCL_DATA_CMD_CACHE_SET_NUM_OFFSET
void hal_tx_desc_set_cache_set_num_generic_be(void *desc, uint8_t cache_num)
{
HAL_SET_FLD(desc, TCL_DATA_CMD, CACHE_SET_NUM) |=
HAL_TX_SM(TCL_DATA_CMD, CACHE_SET_NUM, cache_num);
}
#else
void hal_tx_desc_set_cache_set_num_generic_be(void *desc, uint8_t cache_num)
{
}
#endif
#if defined(QCA_WIFI_WCN7850) || defined(CONFIG_WIFI_EMULATION_WIFI_3_0)
static inline uint32_t
hal_wbm2sw_release_source_get(void *hal_desc, enum hal_be_wbm_release_dir dir)
@@ -262,6 +238,46 @@ uint32_t hal_tx_comp_get_buffer_source_generic_be(void *hal_desc)
HAL_BE_WBM_RELEASE_DIR_TX);
}
/**
* hal_tx_comp_get_release_reason_generic_be() - TQM Release reason
* @hal_desc: completion ring descriptor pointer
*
* This function will return the type of pointer - buffer or descriptor
*
* Return: buffer type
*/
uint8_t hal_tx_comp_get_release_reason_generic_be(void *hal_desc)
{
uint32_t comp_desc = *(uint32_t *)(((uint8_t *)hal_desc) +
WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET);
return (comp_desc &
WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK) >>
WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB;
}
/**
* hal_get_wbm_internal_error_generic_be() - is WBM internal error
* @hal_desc: completion ring descriptor pointer
*
* This function will return 0 or 1 - is it WBM internal error or not
*
* Return: uint8_t
*/
uint8_t hal_get_wbm_internal_error_generic_be(void *hal_desc)
{
/*
* TODO - This func is called by tx comp and wbm error handler
* Check if one needs to use WBM2SW-TX and other WBM2SW-RX
*/
uint32_t comp_desc =
*(uint32_t *)(((uint8_t *)hal_desc) +
HAL_WBM_INTERNAL_ERROR_OFFSET);
return (comp_desc & HAL_WBM_INTERNAL_ERROR_MASK) >>
HAL_WBM_INTERNAL_ERROR_LSB;
}
/**
* hal_setup_link_idle_list_generic_be - Setup scattered idle list using the
* buffer list provided
@@ -886,6 +902,10 @@ void hal_hw_txrx_default_ops_attach_be(struct hal_soc *hal_soc)
hal_gen_reo_remap_val_generic_be;
hal_soc->ops->hal_tx_comp_get_buffer_source =
hal_tx_comp_get_buffer_source_generic_be;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic_be;
hal_soc->ops->hal_get_wbm_internal_error =
hal_get_wbm_internal_error_generic_be;
hal_soc->ops->hal_rx_mpdu_desc_info_get =
hal_rx_mpdu_desc_info_get_be;
hal_soc->ops->hal_rx_err_status_get = hal_rx_err_status_get_be;

84
hal/wifi3.0/be/hal_be_generic_api.h
Voir le fichier

@@ -34,7 +34,6 @@
*
* Return: none
*/
static inline
void hal_tx_comp_get_status_generic_be(void *desc, void *ts1,
struct hal_soc *hal)
{
@@ -99,51 +98,6 @@ void hal_tx_comp_get_status_generic_be(void *desc, void *ts1,
TX_RATE_STATS_INFO_TX_RATE_STATS);
}
/**
* hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor
* @desc: Handle to Tx Descriptor
* @paddr: Physical Address
* @pool_id: Return Buffer Manager ID
* @desc_id: Descriptor ID
* @type: 0 - Address points to a MSDU buffer
* 1 - Address points to MSDU extension descriptor
*
* Return: void
*/
static inline void
hal_tx_desc_set_buf_addr_generic_be(void *desc, dma_addr_t paddr,
uint8_t rbm_id, uint32_t desc_id,
uint8_t type)
{
/* Set buffer_addr_info.buffer_addr_31_0 */
HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0,
BUFFER_ADDR_INFO_BUF_ADDR_INFO) =
HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr);
/* Set buffer_addr_info.buffer_addr_39_32 */
HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
(((uint64_t)paddr) >> 32));
/* Set buffer_addr_info.return_buffer_manager = rbm id */
HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1,
RETURN_BUFFER_MANAGER, rbm_id);
/* Set buffer_addr_info.sw_buffer_cookie = desc_id */
HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1,
BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE,
desc_id);
/* Set Buffer or Ext Descriptor Type */
HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2,
BUF_OR_EXT_DESC_TYPE) |=
HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type);
}
#if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX)
/**
* hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL
@@ -1564,44 +1518,6 @@ hal_rx_status_get_tlv_info_generic_be(void *rx_tlv_hdr, void *ppduinfo,
return HAL_TLV_STATUS_PPDU_NOT_DONE;
}
/**
* hal_tx_comp_get_release_reason_generic_be() - TQM Release reason
* @hal_desc: completion ring descriptor pointer
*
* This function will return the type of pointer - buffer or descriptor
*
* Return: buffer type
*/
static inline uint8_t hal_tx_comp_get_release_reason_generic_be(void *hal_desc)
{
uint32_t comp_desc =
*(uint32_t *)(((uint8_t *)hal_desc) +
WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET);
return (comp_desc & WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK) >>
WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB;
}
/**
* hal_get_wbm_internal_error_generic_be() - is WBM internal error
* @hal_desc: completion ring descriptor pointer
*
* This function will return 0 or 1 - is it WBM internal error or not
*
* Return: uint8_t
*/
static inline uint8_t hal_get_wbm_internal_error_generic_be(void *hal_desc)
{
//TODO - This func is called by tx comp and wbm error handler
//Check if one needs to use WBM2SW-TX and other WBM2SW-RX
uint32_t comp_desc =
*(uint32_t *)(((uint8_t *)hal_desc) +
HAL_WBM_INTERNAL_ERROR_OFFSET);
return (comp_desc & HAL_WBM_INTERNAL_ERROR_MASK) >>
HAL_WBM_INTERNAL_ERROR_LSB;
}
/**
* hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table
* @soc: HAL SoC context

157
hal/wifi3.0/be/hal_be_tx.h
Voir le fichier

@@ -199,18 +199,34 @@ static inline void hal_tx_desc_sync(void *hal_tx_desc_cached,
qdf_mem_copy(hw_desc, hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
}
/**
* hal_tx_desc_set_vdev_id - set vdev id to the descriptor to Hardware
* @hal_tx_des_cached: Cached descriptor that software maintains
* @vdev_id: vdev id
*/
static inline void hal_tx_desc_set_vdev_id(void *desc, uint8_t vdev_id)
{
HAL_SET_FLD(desc, TCL_DATA_CMD, VDEV_ID) |=
HAL_TX_SM(TCL_DATA_CMD, VDEV_ID, vdev_id);
}
/**
* hal_tx_desc_set_bank_id - set bank id to the descriptor to Hardware
* @hal_tx_des_cached: Cached descriptor that software maintains
* @bank_id: bank id
*/
static inline void hal_tx_desc_set_bank_id(void *desc, uint8_t bank_id)
{
HAL_SET_FLD(desc, TCL_DATA_CMD, BANK_ID) |=
HAL_TX_SM(TCL_DATA_CMD, BANK_ID, bank_id);
}
/**
* hal_tx_desc_set_tcl_cmd_type - set tcl command type to the descriptor
* to Hardware
* @hal_tx_des_cached: Cached descriptor that software maintains
* @tcl_cmd_type: tcl command type
*/
static inline void
hal_tx_desc_set_tcl_cmd_type(void *desc, uint8_t tcl_cmd_type)
{
@@ -218,6 +234,50 @@ hal_tx_desc_set_tcl_cmd_type(void *desc, uint8_t tcl_cmd_type)
HAL_TX_SM(TCL_DATA_CMD, TCL_CMD_TYPE, tcl_cmd_type);
}
/**
* hal_tx_desc_set_lmac_id_be - set lmac id to the descriptor to Hardware
* @hal_soc_hdl: hal soc handle
* @hal_tx_des_cached: Cached descriptor that software maintains
* @lmac_id: lmac id
*/
static inline void
hal_tx_desc_set_lmac_id_be(hal_soc_handle_t hal_soc_hdl, void *desc,
uint8_t lmac_id)
{
HAL_SET_FLD(desc, TCL_DATA_CMD, PMAC_ID) |=
HAL_TX_SM(TCL_DATA_CMD, PMAC_ID, lmac_id);
}
/**
* hal_tx_desc_set_search_index_be - set search index to the
* descriptor to Hardware
* @hal_soc_hdl: hal soc handle
* @hal_tx_des_cached: Cached descriptor that software maintains
* @search_index: search index
*/
static inline void
hal_tx_desc_set_search_index_be(hal_soc_handle_t hal_soc_hdl, void *desc,
uint32_t search_index)
{
HAL_SET_FLD(desc, TCL_DATA_CMD, SEARCH_INDEX) |=
HAL_TX_SM(TCL_DATA_CMD, SEARCH_INDEX, search_index);
}
/**
* hal_tx_desc_set_cache_set_num - set cache set num to the
* descriptor to Hardware
* @hal_soc_hdl: hal soc handle
* @hal_tx_des_cached: Cached descriptor that software maintains
* @cache_num: cache number
*/
static inline void
hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl, void *desc,
uint8_t cache_num)
{
HAL_SET_FLD(desc, TCL_DATA_CMD, CACHE_SET_NUM) |=
HAL_TX_SM(TCL_DATA_CMD, CACHE_SET_NUM, cache_num);
}
/*---------------------------------------------------------------------------
* WBM Descriptor accessor APIs for Tx completions
* ---------------------------------------------------------------------------
@@ -392,4 +452,101 @@ hal_tx_populate_bank_register(hal_soc_handle_t hal_soc_hdl,
HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
}
#define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK
#define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT
#define RBM_PPE2TCL_OFFSET \
(HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2)
#define RBM_TCL_CMD_CREDIT_OFFSET \
(HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2)
/**
* hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id
* @hal_soc: HAL SoC context
* @hal_ring_hdl: Source ring pointer
* @rbm_id: return buffer manager ring id
*
* Return: void
*/
static inline void
hal_tx_config_rbm_mapping_be(struct hal_soc *hal_soc,
hal_ring_handle_t hal_ring_hdl,
uint8_t rbm_id)
{
struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
uint32_t reg_addr = 0;
uint32_t reg_val = 0;
uint32_t val = 0;
uint8_t ring_num;
enum hal_ring_type ring_type;
ring_type = srng->ring_type;
ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id;
ring_num = ring_num - srng->ring_id;
reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE);
if (ring_type == PPE2TCL)
ring_num = ring_num + RBM_PPE2TCL_OFFSET;
else if (ring_type == TCL_CMD_CREDIT)
ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET;
/* get current value stored in register address */
val = HAL_REG_READ(hal_soc, reg_addr);
/* mask out other stored value */
val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num)));
reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) <<
(RBM_MAPPING_SHFT * ring_num));
/* write rbm mapped value to register address */
HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
}
/**
* hal_tx_desc_set_buf_addr_be - Fill Buffer Address information in Tx Desc
* @desc: Handle to Tx Descriptor
* @paddr: Physical Address
* @pool_id: Return Buffer Manager ID
* @desc_id: Descriptor ID
* @type: 0 - Address points to a MSDU buffer
* 1 - Address points to MSDU extension descriptor
*
* Return: void
*/
static inline void
hal_tx_desc_set_buf_addr_be(hal_soc_handle_t hal_soc_hdl, void *desc,
dma_addr_t paddr, uint8_t rbm_id,
uint32_t desc_id, uint8_t type)
{
/* Set buffer_addr_info.buffer_addr_31_0 */
HAL_SET_FLD(desc, TCL_DATA_CMD,
BUF_ADDR_INFO_BUFFER_ADDR_31_0) =
HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_31_0, paddr);
/* Set buffer_addr_info.buffer_addr_39_32 */
HAL_SET_FLD(desc, TCL_DATA_CMD,
BUF_ADDR_INFO_BUFFER_ADDR_39_32) |=
HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_BUFFER_ADDR_39_32,
(((uint64_t)paddr) >> 32));
/* Set buffer_addr_info.return_buffer_manager = rbm id */
HAL_SET_FLD(desc, TCL_DATA_CMD,
BUF_ADDR_INFO_RETURN_BUFFER_MANAGER) |=
HAL_TX_SM(TCL_DATA_CMD,
BUF_ADDR_INFO_RETURN_BUFFER_MANAGER, rbm_id);
/* Set buffer_addr_info.sw_buffer_cookie = desc_id */
HAL_SET_FLD(desc, TCL_DATA_CMD,
BUF_ADDR_INFO_SW_BUFFER_COOKIE) |=
HAL_TX_SM(TCL_DATA_CMD, BUF_ADDR_INFO_SW_BUFFER_COOKIE,
desc_id);
/* Set Buffer or Ext Descriptor Type */
HAL_SET_FLD(desc, TCL_DATA_CMD,
BUF_OR_EXT_DESC_TYPE) |=
HAL_TX_SM(TCL_DATA_CMD, BUF_OR_EXT_DESC_TYPE, type);
}
#endif /* _HAL_BE_TX_H_ */