disp: msm: sde: add new interface for RFI feature
Add a new connector range property and a new entry to the panel capability blob to publish the list of supported RFI frequencies. In addition, add the required functions to set, validate and update DSI bit clock rate value to trigger an internal seamless mode switch and reconfigure DSI clock and PLL. Change-Id: I7d19cc369f8c5528709f2f20a51ef02180ebdea4 Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
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@@ -154,6 +154,8 @@ struct dsi_display_ext_bridge {
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* index into the ctrl[MAX_DSI_CTRLS_PER_DISPLAY] array.
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* @cmd_master_idx: The master controller for sending DSI commands to panel.
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* @video_master_idx: The master controller for enabling video engine.
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* @dyn_bit_clk: The DSI bit clock rate dynamically set by user mode client.
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* @dyn_bit_clk_pending: Flag indicating the pending DSI dynamic bit clock rate change.
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* @cached_clk_rate: The cached DSI clock rate set dynamically by sysfs.
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* @clkrate_change_pending: Flag indicating the pending DSI clock re-enabling.
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* @clock_info: Clock sourcing for DSI display.
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@@ -225,7 +227,9 @@ struct dsi_display {
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u32 video_master_idx;
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/* dynamic DSI clock info*/
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u32 cached_clk_rate;
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u32 dyn_bit_clk;
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bool dyn_bit_clk_pending;
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u32 cached_clk_rate;
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atomic_t clkrate_change_pending;
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struct dsi_display_clk_info clock_info;
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@@ -776,4 +780,21 @@ int dsi_display_get_panel_vfp(void *display,
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*/
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int dsi_display_dump_clks_state(struct dsi_display *display);
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/**
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* dsi_display_update_dyn_bit_clk() - update mode timing to compensate for dynamic bit clock
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* @display: Handle to display
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* @mode: Mode to be updated
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* Return: Zero on Success
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*/
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int dsi_display_update_dyn_bit_clk(struct dsi_display *display, struct dsi_display_mode *mode);
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/**
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* dsi_display_restore_bit_clk() - restore mode bit clock rate value from dynamic bit clock
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* @display: Handle to display
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* @mode: Mode to be updated
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* Return: Zero on Success
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*/
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int dsi_display_restore_bit_clk(struct dsi_display *display, struct dsi_display_mode *mode);
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#endif /* _DSI_DISPLAY_H_ */
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