disp: msm: sde: update uidle wd timer load value and fal1 threshold

Update the uidle wd timer load value to 18. This change will allow
a 15us wd timer per hardware recommendation.

Update fal1 threshold value to take the minimum of 15 or the
current setting which takes line time and target idle time into
consideration. The target idle time is also being updated from 10us to
40us.

Change-Id: Ia8d9c2070813beef18fdf342526d82cf8f82989b
Signed-off-by: Samantha Tran <samtran@codeaurora.org>

msm/sde/sde_hw_catalog.c

@@ -149,7 +149,7 @@
 #define SDE_UIDLE_FAL10_EXIT_DANGER 4
 #define SDE_UIDLE_FAL10_DANGER 6
 #define SDE_UIDLE_FAL10_TARGET_IDLE 50
-#define SDE_UIDLE_FAL1_TARGET_IDLE 10
+#define SDE_UIDLE_FAL1_TARGET_IDLE 40
 #define SDE_UIDLE_FAL10_THRESHOLD_60 12
 #define SDE_UIDLE_FAL10_THRESHOLD_90 13
 #define SDE_UIDLE_MAX_DWNSCALE 1500

msm/sde/sde_hw_uidle.h

@@ -23,7 +23,7 @@ struct sde_hw_uidle;
 
 #define SDE_UIDLE_WD_GRANULARITY 1
 #define SDE_UIDLE_WD_HEART_BEAT 0
-#define SDE_UIDLE_WD_LOAD_VAL 12
+#define SDE_UIDLE_WD_LOAD_VAL 18
 
 struct sde_uidle_ctl_cfg {
 	u32 fal10_exit_cnt;

msm/sde/sde_plane.c

@@ -2862,6 +2862,7 @@ static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
 {
 	struct sde_hw_pipe_uidle_cfg cfg;
 	struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
+	u32 fal1_threshold_max = 15;
 
 	u32 line_time = sde_get_linetime(&crtc->mode,
 			sde_crtc->src_bpp, sde_crtc->target_bpp); /* nS */
@@ -2877,8 +2878,9 @@ static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
 		cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
 		cfg.fal10_threshold = fal10_threshold;
 		cfg.fal10_exit_threshold = fal10_threshold + 2;
-		cfg.fal1_threshold = 1 +
-			(fal1_target_idle_time_ns*1000/line_time*2)/1000;
+		cfg.fal1_threshold = min(1 +
+			(fal1_target_idle_time_ns*1000/line_time*2)/1000,
+			fal1_threshold_max);
 		cfg.fal_allowed_threshold = fal10_threshold +
 			(fal10_target_idle_time_ns*1000/line_time*2)/1000;
 	} else {