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disp: msm: sde: add support for DMA 4,5 for Kalama

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Expand various SSPP and CTL related data structures
to support DMA 4,5.

Change-Id: I0ce052b6a2f1599a9b6eb82ce8e4f34f4c68333d
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
This commit is contained in:
Amine Najahi
2021-11-16 13:37:30 -05:00
parent 2d3a255c06
commit d36499ca86
5 changed files with 31 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
msm/sde/sde_hw_ctl.c
View File

@@ -18,6 +18,8 @@
(0x70 + (((lm) - LM_0) * 0x004))
#define CTL_LAYER_EXT3(lm) \
(0xA0 + (((lm) - LM_0) * 0x004))
#define CTL_LAYER_EXT4(lm) \
(0xB8 + (((lm) - LM_0) * 0x004))
#define CTL_TOP 0x014
#define CTL_FLUSH 0x018
#define CTL_START 0x01C
@@ -54,7 +56,7 @@
#define CTL_FLUSH_MASK_ROT BIT(27)
#define CTL_FLUSH_MASK_CTL BIT(17)
#define CTL_NUM_EXT 4
#define CTL_NUM_EXT 5
#define CTL_SSPP_MAX_RECTS 2
#define SDE_REG_RESET_TIMEOUT_US 2000
@@ -73,7 +75,7 @@
* List of SSPP bits in CTL_FLUSH
*/
static const u32 sspp_tbl[SSPP_MAX] = { SDE_NONE, 0, 1, 2, 18, 3, 4, 5,
19, 11, 12, 24, 25, SDE_NONE, SDE_NONE};
19, 11, 12, 24, 25, 13, 14, SDE_NONE, SDE_NONE};
/**
* List of layer mixer bits in CTL_FLUSH
@@ -123,7 +125,7 @@ static const u32 intf_tbl[INTF_MAX] = {SDE_NONE, 31, 30, 29, 28};
*/
static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,
CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0,
1, 2, 3, CTL_INVALID_BIT, CTL_INVALID_BIT};
1, 2, 3, 4, 5, CTL_INVALID_BIT, CTL_INVALID_BIT};
/**
* list of WB bits in CTL_WB_FLUSH
@@ -218,6 +220,8 @@ sspp_reg_cfg_tbl[SSPP_MAX][CTL_SSPP_MAX_RECTS] = {
/* SSPP_DMA1 */{ {0, 21, 3, BIT(18)}, {2, 12, 4, 0} },
/* SSPP_DMA2 */{ {2, 0, 4, 0}, {2, 16, 4, 0} },
/* SSPP_DMA3 */{ {2, 4, 4, 0}, {2, 20, 4, 0} },
/* SSPP_DMA4 */{ {4, 0, 4, 0}, {4, 8, 4, 0} },
/* SSPP_DMA5 */{ {4, 4, 4, 0}, {4, 12, 4, 0} },
/* SSPP_CURSOR0 */{ {1, 20, 4, 0}, {0, 0, 0, 0} },
/* SSPP_CURSOR1 */{ {1, 26, 4, 0}, {0, 0, 0, 0} }
};
@@ -846,6 +850,7 @@ static void sde_hw_ctl_clear_all_blendstages(struct sde_hw_ctl *ctx)
SDE_REG_WRITE(c, CTL_LAYER_EXT(mixer_id), 0);
SDE_REG_WRITE(c, CTL_LAYER_EXT2(mixer_id), 0);
SDE_REG_WRITE(c, CTL_LAYER_EXT3(mixer_id), 0);
SDE_REG_WRITE(c, CTL_LAYER_EXT4(mixer_id), 0);
}
SDE_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0);
}
@@ -894,6 +899,7 @@ static void sde_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx,
struct sde_hw_blk_reg_map *c;
u32 cfg[CTL_NUM_EXT] = { 0 };
int stages;
bool null_commit;
if (!ctx)
return;
@@ -907,15 +913,15 @@ static void sde_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx,
if (stage_cfg)
_sde_hw_ctl_get_mixer_cfg(ctx, stage_cfg, stages, cfg);
if (!disable_border &&
((!cfg[0] && !cfg[1] && !cfg[2] && !cfg[3]) ||
(stage_cfg && !stage_cfg->stage[0][0])))
null_commit = (!cfg[0] && !cfg[1] && !cfg[2] && !cfg[3] && !cfg[4]);
if (!disable_border && (null_commit || (stage_cfg && !stage_cfg->stage[0][0])))
cfg[0] |= CTL_MIXER_BORDER_OUT;
SDE_REG_WRITE(c, CTL_LAYER(lm), cfg[0]);
SDE_REG_WRITE(c, CTL_LAYER_EXT(lm), cfg[1]);
SDE_REG_WRITE(c, CTL_LAYER_EXT2(lm), cfg[2]);
SDE_REG_WRITE(c, CTL_LAYER_EXT3(lm), cfg[3]);
SDE_REG_WRITE(c, CTL_LAYER_EXT4(lm), cfg[4]);
}
static u32 sde_hw_ctl_get_staged_sspp(struct sde_hw_ctl *ctx, enum sde_lm lm,
@@ -937,6 +943,7 @@ static u32 sde_hw_ctl_get_staged_sspp(struct sde_hw_ctl *ctx, enum sde_lm lm,
mixercfg[1] = SDE_REG_READ(c, CTL_LAYER_EXT(lm));
mixercfg[2] = SDE_REG_READ(c, CTL_LAYER_EXT2(lm));
mixercfg[3] = SDE_REG_READ(c, CTL_LAYER_EXT3(lm));
mixercfg[4] = SDE_REG_READ(c, CTL_LAYER_EXT4(lm));
if (mixercfg[0] & CTL_MIXER_BORDER_OUT)
info->bordercolor = true;

12
msm/sde/sde_hw_mdss.h
View File

@@ -140,19 +140,31 @@ enum sde_sspp {
SSPP_VIG1,
SSPP_VIG2,
SSPP_VIG3,
SSPP_VIG_MAX = SSPP_VIG3,
SSPP_RGB0,
SSPP_RGB1,
SSPP_RGB2,
SSPP_RGB3,
SSPP_RGB_MAX = SSPP_RGB3,
SSPP_DMA0,
SSPP_DMA1,
SSPP_DMA2,
SSPP_DMA3,
SSPP_DMA4,
SSPP_DMA5,
SSPP_DMA_MAX = SSPP_DMA5,
SSPP_CURSOR0,
SSPP_CURSOR1,
SSPP_CURSOR_MAX = SSPP_CURSOR1,
SSPP_MAX
};
#define SDE_SSPP_VALID(x) ((x) > SSPP_NONE && (x) < SSPP_MAX)
#define SDE_SSPP_VALID_VIG(x) ((x) >= SSPP_VIG0 && (x) <= SSPP_VIG_MAX)
#define SDE_SSPP_VALID_RGB(x) ((x) >= SSPP_RGB0 && (x) <= SSPP_RGB_MAX)
#define SDE_SSPP_VALID_DMA(x) ((x) >= SSPP_DMA0 && (x) <= SSPP_DMA_MAX)
#define SDE_SSPP_VALID_CURSOR(x) ((x) >= SSPP_CURSOR0 && (x) <= SSPP_CURSOR_MAX)
enum sde_sspp_type {
SSPP_TYPE_VIG,
SSPP_TYPE_RGB,

3
msm/sde/sde_hw_reg_dma_v1_color_proc.c
View File

@@ -2183,8 +2183,7 @@ static int reg_dma_sspp_check(struct sde_hw_pipe *ctx, void *cfg,
if (IS_ERR_OR_NULL(dma_ops))
return -EINVAL;
if (!hw_cfg->ctl || ctx->idx > SSPP_DMA3 || ctx->idx <= SSPP_NONE ||
feature >= REG_DMA_FEATURES_MAX) {
if (!hw_cfg->ctl || !SDE_SSPP_VALID(ctx->idx) || feature >= REG_DMA_FEATURES_MAX) {
DRM_ERROR("invalid ctl %pK sspp idx %d feature %d\n",
hw_cfg->ctl, ctx->idx, feature);
return -EINVAL;

4
msm/sde/sde_hw_top.c
View File

@@ -415,9 +415,9 @@ void sde_hw_set_sspp_sid(struct sde_hw_sid *sid, u32 pipe, u32 vm)
if (!sid)
return;
if ((pipe >= SSPP_VIG0) && (pipe <= SSPP_VIG3))
if (SDE_SSPP_VALID_VIG(pipe))
offset = MDP_SID_VIG0 + ((pipe - SSPP_VIG0) * 4);
else if ((pipe >= SSPP_DMA0) && (pipe <= SSPP_DMA3))
else if (SDE_SSPP_VALID_DMA(pipe))
offset = MDP_SID_DMA0 + ((pipe - SSPP_DMA0) * 4);
else
return;

6
msm/sde/sde_plane.c
View File

@@ -3703,11 +3703,11 @@ static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
if (psde->pipe <= SSPP_VIG3 && psde->pipe >= SSPP_VIG0)
if (SDE_SSPP_VALID_VIG(psde->pipe))
pipe_id = psde->pipe - SSPP_VIG0;
else if (psde->pipe <= SSPP_RGB3 && psde->pipe >= SSPP_RGB0)
else if (SDE_SSPP_VALID_RGB(psde->pipe))
pipe_id = psde->pipe - SSPP_RGB0;
else if (psde->pipe <= SSPP_DMA3 && psde->pipe >= SSPP_DMA0)
else if (SDE_SSPP_VALID_DMA(psde->pipe))
pipe_id = psde->pipe - SSPP_DMA0;
else
pipe_id = -1;