disp: msm: dp: get DSC enable status from mode instead of panel
DSC enable status is updated in DP panel struct as per the DPCD reg read which is done at the start of the HPD ISR. However, there is a chance that DSC is actually disabled later during mode query due to shortage of DSC blocks. This status is stored as part of compression info structure. This change checks for the latter struct to determine the actual DSC status. Change-Id: Id7cd4e65060f2ec939f945e9ac4f4e66260605d3 Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
这个提交包含在:
@@ -436,7 +436,7 @@ static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in,
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tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices;
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if (dsc_num_bytes == 0)
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DP_DEBUG("incorrect no of bytes per slice=%d\n", dsc_num_bytes);
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DP_WARN("incorrect no of bytes per slice=%d\n", dsc_num_bytes);
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dwidth_dsc_bytes = (tot_num_hor_bytes +
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tot_num_eoc_symbols +
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@@ -1113,7 +1113,7 @@ static void dp_panel_calc_tu_parameters(struct dp_panel *dp_panel,
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in.nlanes = panel->link->link_params.lane_count;
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in.bpp = pinfo->bpp;
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in.pixel_enc = 444;
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in.dsc_en = dp_panel->dsc_en;
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in.dsc_en = pinfo->comp_info.enabled;
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in.async_en = 0;
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in.fec_en = dp_panel->fec_en;
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in.num_of_dsc_slices = pinfo->comp_info.dsc_info.slice_per_pkt;
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@@ -1907,7 +1907,7 @@ end:
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}
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static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel,
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u32 mode_edid_bpp, u32 mode_pclk_khz)
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u32 mode_edid_bpp, u32 mode_pclk_khz, bool dsc_en)
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{
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struct dp_link_params *link_params;
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struct dp_panel_private *panel;
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@@ -1918,7 +1918,7 @@ static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel,
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panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
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if (dp_panel->dsc_en)
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if (dsc_en)
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min_supported_bpp = 24;
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bpp = min_t(u32, mode_edid_bpp, max_supported_bpp);
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@@ -1934,7 +1934,7 @@ static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel,
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link_bitrate = drm_fixp2int(rate_fp);
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for (; bpp > min_supported_bpp; bpp -= 6) {
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if (dp_panel->dsc_en) {
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if (dsc_en) {
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if (bpp == 30 && !(dp_panel->sink_dsc_caps.color_depth & DP_DSC_10_BPC))
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continue;
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else if (bpp == 24 && !(dp_panel->sink_dsc_caps.color_depth & DP_DSC_8_BPC))
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@@ -1959,7 +1959,7 @@ static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel,
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}
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static u32 dp_panel_get_mode_bpp(struct dp_panel *dp_panel,
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u32 mode_edid_bpp, u32 mode_pclk_khz)
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u32 mode_edid_bpp, u32 mode_pclk_khz, bool dsc_en)
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{
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struct dp_panel_private *panel;
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u32 bpp = mode_edid_bpp;
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@@ -1976,7 +1976,7 @@ static u32 dp_panel_get_mode_bpp(struct dp_panel *dp_panel,
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panel->link->test_video.test_bit_depth);
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else
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bpp = dp_panel_get_supported_bpp(dp_panel, mode_edid_bpp,
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mode_pclk_khz);
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mode_pclk_khz, dsc_en);
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return bpp;
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}
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@@ -2730,9 +2730,11 @@ static void dp_panel_config_ctrl(struct dp_panel *dp_panel)
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u8 *dpcd = dp_panel->dpcd;
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struct dp_panel_private *panel;
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struct dp_catalog_panel *catalog;
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struct msm_compression_info *comp_info;
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panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
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catalog = panel->catalog;
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comp_info = &dp_panel->pinfo.comp_info;
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config |= (2 << 13); /* Default-> LSCLK DIV: 1/4 LCLK */
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config |= (0 << 11); /* RGB */
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@@ -2740,7 +2742,7 @@ static void dp_panel_config_ctrl(struct dp_panel *dp_panel)
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tbd = panel->link->get_test_bits_depth(panel->link,
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dp_panel->pinfo.bpp);
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if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN || dp_panel->dsc_en)
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if (tbd == DP_TEST_BIT_DEPTH_UNKNOWN || comp_info->enabled)
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tbd = (DP_TEST_BIT_DEPTH_8 >> DP_TEST_BIT_DEPTH_SHIFT);
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config |= tbd << 8;
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@@ -2950,8 +2952,7 @@ static void dp_panel_convert_to_dp_mode(struct dp_panel *dp_panel,
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{
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const u32 num_components = 3, default_bpp = 24;
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struct msm_compression_info *comp_info;
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bool dsc_cap = (dp_mode->capabilities & DP_PANEL_CAPS_DSC) ?
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true : false;
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bool dsc_en = (dp_mode->capabilities & DP_PANEL_CAPS_DSC) ? true : false;
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int rc;
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dp_mode->timing.h_active = drm_mode->hdisplay;
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@@ -3010,9 +3011,9 @@ static void dp_panel_convert_to_dp_mode(struct dp_panel *dp_panel,
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}
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dp_mode->timing.bpp = dp_panel_get_mode_bpp(dp_panel,
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dp_mode->timing.bpp, dp_mode->timing.pixel_clk_khz);
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dp_mode->timing.bpp, dp_mode->timing.pixel_clk_khz, dsc_en);
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if (dp_panel->dsc_en && dsc_cap) {
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if (dp_panel->dsc_en && dsc_en) {
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if (dp_panel_dsc_prepare_basic_params(comp_info,
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dp_mode, dp_panel)) {
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DP_DEBUG("prepare DSC basic params failed\n");
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