disp: msm: sde: remove rgb/cursor pipe related code

The HW support for RGB pipes were removed from MDSS 3.x and cursor pipes
from MDSS 4.x. Remove the support from s/w as well with this change.

Change-Id: Ib5b363234e200ee5c421684cf1904a38a5d90b58
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This commit is contained in:
Veera Sundaram Sankaran
2021-12-14 11:27:41 -08:00
parent e7c09f0092
commit d1dcc8da8e
9 changed files with 21 additions and 230 deletions

View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
@@ -270,7 +270,6 @@ enum {
SSPP_CLK_STATUS,
SSPP_SCALE_SIZE,
SSPP_VIG_BLOCKS,
SSPP_RGB_BLOCKS,
SSPP_DMA_BLOCKS,
SSPP_EXCL_RECT,
SSPP_SMART_DMA,
@@ -298,13 +297,6 @@ enum {
VIG_PROP_MAX,
};
enum {
RGB_SCALER_OFF,
RGB_SCALER_LEN,
RGB_PCC_PROP,
RGB_PROP_MAX,
};
enum {
DMA_SUBBLOCK_INDEX,
DMA_TOP_OFF,
@@ -688,7 +680,6 @@ static struct sde_prop_type sspp_prop[] = {
PROP_TYPE_BIT_OFFSET_ARRAY},
{SSPP_SCALE_SIZE, "qcom,sde-sspp-scale-size", false, PROP_TYPE_U32},
{SSPP_VIG_BLOCKS, "qcom,sde-sspp-vig-blocks", false, PROP_TYPE_NODE},
{SSPP_RGB_BLOCKS, "qcom,sde-sspp-rgb-blocks", false, PROP_TYPE_NODE},
{SSPP_DMA_BLOCKS, "qcom,sde-sspp-dma-blocks", false, PROP_TYPE_NODE},
{SSPP_EXCL_RECT, "qcom,sde-sspp-excl-rect", false, PROP_TYPE_U32_ARRAY},
{SSPP_SMART_DMA, "qcom,sde-sspp-smart-dma-priority", false,
@@ -732,12 +723,6 @@ static struct sde_prop_type vig_prop[] = {
false, PROP_TYPE_U32_ARRAY},
};
static struct sde_prop_type rgb_prop[] = {
{RGB_SCALER_OFF, "qcom,sde-rgb-scaler-off", false, PROP_TYPE_U32},
{RGB_SCALER_LEN, "qcom,sde-rgb-scaler-size", false, PROP_TYPE_U32},
{RGB_PCC_PROP, "qcom,sde-rgb-pcc", false, PROP_TYPE_U32_ARRAY},
};
static struct sde_prop_type dma_prop[] = {
[DMA_SUBBLOCK_INDEX] = {DMA_SUBBLOCK_INDEX, "cell-index", false,
PROP_TYPE_U32},
@@ -1661,103 +1646,6 @@ end:
return rc;
}
static void _sde_sspp_setup_rgbs_pp(struct sde_dt_props *props,
struct sde_mdss_cfg *sde_cfg, struct sde_sspp_cfg *sspp)
{
struct sde_sspp_sub_blks *sblk = sspp->sblk;
sblk->pcc_blk.id = SDE_SSPP_PCC;
if (props->exists[RGB_PCC_PROP]) {
sblk->pcc_blk.base = PROP_VALUE_ACCESS(props->values,
RGB_PCC_PROP, 0);
sblk->pcc_blk.version = PROP_VALUE_ACCESS(props->values,
RGB_PCC_PROP, 1);
sblk->pcc_blk.len = 0;
set_bit(SDE_SSPP_PCC, &sspp->features);
}
}
static int _sde_sspp_setup_rgbs(struct device_node *np,
struct sde_mdss_cfg *sde_cfg)
{
int i;
struct sde_dt_props *props;
struct device_node *snp = NULL;
int rgb_count = 0;
const char *type;
snp = of_get_child_by_name(np, sspp_prop[SSPP_RGB_BLOCKS].prop_name);
if (!snp)
return 0;
props = sde_get_dt_props(snp, RGB_PROP_MAX, rgb_prop,
ARRAY_SIZE(rgb_prop), NULL);
if (IS_ERR(props))
return PTR_ERR(props);
for (i = 0; i < sde_cfg->sspp_count; ++i) {
struct sde_sspp_cfg *sspp = sde_cfg->sspp + i;
struct sde_sspp_sub_blks *sblk = sspp->sblk;
of_property_read_string_index(np,
sspp_prop[SSPP_TYPE].prop_name, i, &type);
if (strcmp(type, "rgb"))
continue;
sblk->maxupscale = MAX_UPSCALE_RATIO;
sblk->maxdwnscale = MAX_DOWNSCALE_RATIO;
sspp->id = SSPP_RGB0 + rgb_count;
snprintf(sspp->name, SDE_HW_BLK_NAME_LEN, "sspp_%u",
sspp->id - SSPP_VIG0);
sspp->clk_ctrl = SDE_CLK_CTRL_RGB0 + rgb_count;
sspp->type = SSPP_TYPE_RGB;
set_bit(SDE_PERF_SSPP_QOS, &sspp->perf_features);
if (sde_cfg->vbif_qos_nlvl == 8)
set_bit(SDE_PERF_SSPP_QOS_8LVL, &sspp->perf_features);
rgb_count++;
if ((sde_cfg->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED2) ||
(sde_cfg->qseed_sw_lib_rev == SDE_SSPP_SCALER_QSEED3)) {
set_bit(SDE_SSPP_SCALER_RGB, &sspp->features);
sblk->scaler_blk.id = sde_cfg->qseed_sw_lib_rev;
sblk->scaler_blk.base = PROP_VALUE_ACCESS(props->values,
RGB_SCALER_OFF, 0);
sblk->scaler_blk.len = PROP_VALUE_ACCESS(props->values,
RGB_SCALER_LEN, 0);
snprintf(sblk->scaler_blk.name, SDE_HW_BLK_NAME_LEN,
"sspp_scaler%u", sspp->id - SSPP_VIG0);
}
_sde_sspp_setup_rgbs_pp(props, sde_cfg, sspp);
sblk->format_list = sde_cfg->dma_formats;
sblk->virt_format_list = NULL;
}
sde_put_dt_props(props);
return 0;
}
static void _sde_sspp_setup_cursor(struct sde_mdss_cfg *sde_cfg,
struct sde_sspp_cfg *sspp, struct sde_sspp_sub_blks *sblk,
struct sde_prop_value *prop_value, u32 *cursor_count)
{
if (!IS_SDE_MAJOR_MINOR_SAME(sde_cfg->hw_rev, SDE_HW_VER_300))
SDE_ERROR("invalid sspp type %d, xin id %d\n",
sspp->type, sspp->xin_id);
set_bit(SDE_SSPP_CURSOR, &sspp->features);
sblk->maxupscale = SSPP_UNITY_SCALE;
sblk->maxdwnscale = SSPP_UNITY_SCALE;
sblk->format_list = sde_cfg->cursor_formats;
sblk->virt_format_list = NULL;
sspp->id = SSPP_CURSOR0 + *cursor_count;
snprintf(sspp->name, SDE_HW_BLK_NAME_LEN, "sspp_%u",
sspp->id - SSPP_VIG0);
sspp->clk_ctrl = SDE_CLK_CTRL_CURSOR0 + *cursor_count;
sspp->type = SSPP_TYPE_CURSOR;
(*cursor_count)++;
}
static void _sde_sspp_setup_dgm(struct sde_sspp_cfg *sspp,
const struct sde_dt_props *props, const char *name,
struct sde_pp_blk *blk, u32 type, u32 prop, bool versioned)
@@ -1996,10 +1884,8 @@ static int _sde_sspp_setup_cmn(struct device_node *np,
{
int rc = 0, off_count, i, j;
struct sde_dt_props *props;
const char *type;
struct sde_sspp_cfg *sspp;
struct sde_sspp_sub_blks *sblk;
u32 cursor_count = 0;
props = sde_get_dt_props(np, SSPP_PROP_MAX, sspp_prop,
ARRAY_SIZE(sspp_prop), &off_count);
@@ -2034,14 +1920,6 @@ static int _sde_sspp_setup_cmn(struct device_node *np,
sspp->base = PROP_VALUE_ACCESS(props->values, SSPP_OFF, i);
sspp->len = PROP_VALUE_ACCESS(props->values, SSPP_SIZE, 0);
of_property_read_string_index(np,
sspp_prop[SSPP_TYPE].prop_name, i, &type);
if (!strcmp(type, "cursor")) {
/* No prop values for cursor pipes */
_sde_sspp_setup_cursor(sde_cfg, sspp, sblk, NULL,
&cursor_count);
}
snprintf(sblk->src_blk.name, SDE_HW_BLK_NAME_LEN, "sspp_src_%u",
sspp->id - SSPP_VIG0);
@@ -2097,10 +1975,6 @@ static int sde_sspp_parse_dt(struct device_node *np,
if (rc)
return rc;
rc = _sde_sspp_setup_rgbs(np, sde_cfg);
if (rc)
return rc;
rc = _sde_sspp_setup_dmas(np, sde_cfg);
return rc;
@@ -4725,26 +4599,11 @@ static int sde_hardware_format_caps(struct sde_mdss_cfg *sde_cfg,
int rc = 0;
uint32_t dma_list_size, vig_list_size, wb2_list_size;
uint32_t virt_vig_list_size, in_rot_list_size = 0;
uint32_t cursor_list_size = 0;
uint32_t index = 0;
uint32_t in_rot_restricted_list_size = 0;
const struct sde_format_extended *inline_fmt_tbl = NULL;
const struct sde_format_extended *inline_restricted_fmt_tbl = NULL;
/* cursor input formats */
if (test_bit(SDE_FEATURE_CURSOR, sde_cfg->features)) {
cursor_list_size = ARRAY_SIZE(cursor_formats);
sde_cfg->cursor_formats = kcalloc(cursor_list_size,
sizeof(struct sde_format_extended), GFP_KERNEL);
if (!sde_cfg->cursor_formats) {
rc = -ENOMEM;
goto out;
}
index = sde_copy_formats(sde_cfg->cursor_formats,
cursor_list_size, 0, cursor_formats,
ARRAY_SIZE(cursor_formats));
}
/* DMA pipe input formats */
dma_list_size = ARRAY_SIZE(plane_formats);
if (test_bit(SDE_FEATURE_FP16, sde_cfg->features))
@@ -4754,7 +4613,7 @@ static int sde_hardware_format_caps(struct sde_mdss_cfg *sde_cfg,
sizeof(struct sde_format_extended), GFP_KERNEL);
if (!sde_cfg->dma_formats) {
rc = -ENOMEM;
goto free_cursor;
goto out;
}
index = sde_copy_formats(sde_cfg->dma_formats, dma_list_size,
@@ -4871,9 +4730,6 @@ free_vig:
kfree(sde_cfg->vig_formats);
free_dma:
kfree(sde_cfg->dma_formats);
free_cursor:
if (test_bit(SDE_FEATURE_CURSOR, sde_cfg->features))
kfree(sde_cfg->cursor_formats);
out:
return rc;
}
@@ -4959,7 +4815,6 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
sde_cfg->vbif_qos_nlvl = 4;
sde_cfg->ts_prefill_rev = 1;
set_bit(SDE_FEATURE_DECIMATION, sde_cfg->features);
set_bit(SDE_FEATURE_CURSOR, sde_cfg->features);
clear_bit(SDE_FEATURE_COMBINED_ALPHA, sde_cfg->features);
clear_bit(SDE_FEATURE_DELAY_PRG_FETCH, sde_cfg->features);
clear_bit(SDE_FEATURE_SUI_MISR, sde_cfg->features);
@@ -5423,7 +5278,6 @@ void sde_hw_catalog_deinit(struct sde_mdss_cfg *sde_cfg)
kfree(sde_cfg->perf.creq_lut);
kfree(sde_cfg->dma_formats);
kfree(sde_cfg->cursor_formats);
kfree(sde_cfg->vig_formats);
kfree(sde_cfg->wb_formats);
kfree(sde_cfg->virt_vig_formats);

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@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
@@ -264,13 +264,11 @@ enum {
* @SDE_SSPP_SRC Src and fetch part of the pipes,
* @SDE_SSPP_SCALER_QSEED2, QSEED2 algorithm support
* @SDE_SSPP_SCALER_QSEED3, QSEED3 alogorithm support
* @SDE_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes
* @SDE_SSPP_CSC, Support of Color space converion
* @SDE_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
* @SDE_SSPP_HSIC, Global HSIC control
* @SDE_SSPP_MEMCOLOR Memory Color Support
* @SDE_SSPP_PCC, Color correction support
* @SDE_SSPP_CURSOR, SSPP can be used as a cursor layer
* @SDE_SSPP_EXCL_RECT, SSPP supports exclusion rect
* @SDE_SSPP_SMART_DMA_V1, SmartDMA 1.0 support
* @SDE_SSPP_SMART_DMA_V2, SmartDMA 2.0 support
@@ -301,13 +299,11 @@ enum {
SDE_SSPP_SRC = 0x1,
SDE_SSPP_SCALER_QSEED2,
SDE_SSPP_SCALER_QSEED3,
SDE_SSPP_SCALER_RGB,
SDE_SSPP_CSC,
SDE_SSPP_CSC_10BIT,
SDE_SSPP_HSIC,
SDE_SSPP_MEMCOLOR,
SDE_SSPP_PCC,
SDE_SSPP_CURSOR,
SDE_SSPP_EXCL_RECT,
SDE_SSPP_SMART_DMA_V1,
SDE_SSPP_SMART_DMA_V2,
@@ -662,7 +658,6 @@ enum {
* @SDE_FEATURE_BASE_LAYER Base Layer supported
* @SDE_FEATURE_TOUCH_WAKEUP Early wakeup with touch supported
* @SDE_FEATURE_SRC_SPLIT Source split supported
* @SDE_FEATURE_CURSOR Cursor supported
* @SDE_FEATURE_VIG_P010 P010 ViG pipe format supported
* @SDE_FEATURE_FP16 FP16 pipe format supported
* @SDE_FEATURE_HDR High Dynamic Range supported
@@ -703,7 +698,6 @@ enum sde_mdss_features {
SDE_FEATURE_BASE_LAYER,
SDE_FEATURE_TOUCH_WAKEUP,
SDE_FEATURE_SRC_SPLIT,
SDE_FEATURE_CURSOR,
SDE_FEATURE_VIG_P010,
SDE_FEATURE_FP16,
SDE_FEATURE_HDR,
@@ -1068,18 +1062,12 @@ enum sde_clk_ctrl_type {
SDE_CLK_CTRL_VIG2,
SDE_CLK_CTRL_VIG3,
SDE_CLK_CTRL_VIG4,
SDE_CLK_CTRL_RGB0,
SDE_CLK_CTRL_RGB1,
SDE_CLK_CTRL_RGB2,
SDE_CLK_CTRL_RGB3,
SDE_CLK_CTRL_DMA0,
SDE_CLK_CTRL_DMA1,
SDE_CLK_CTRL_DMA2,
SDE_CLK_CTRL_DMA3,
SDE_CLK_CTRL_DMA4,
SDE_CLK_CTRL_DMA5,
SDE_CLK_CTRL_CURSOR0,
SDE_CLK_CTRL_CURSOR1,
SDE_CLK_CTRL_WB0,
SDE_CLK_CTRL_WB1,
SDE_CLK_CTRL_WB2,
@@ -1089,8 +1077,8 @@ enum sde_clk_ctrl_type {
};
#define SDE_CLK_CTRL_VALID(x) (x > SDE_CLK_CTRL_NONE && x < SDE_CLK_CTRL_MAX)
#define SDE_CLK_CTRL_SSPP_VALID(x) (x >= SDE_CLK_CTRL_VIG0 && x <= SDE_CLK_CTRL_CURSOR1)
#define SDE_CLK_CTRL_WB_VALID(x) (x >= SDE_CLK_CTRL_WB0 && x <= SDE_CLK_CTRL_WB2)
#define SDE_CLK_CTRL_SSPP_VALID(x) (x >= SDE_CLK_CTRL_VIG0 && x < SDE_CLK_CTRL_WB0)
#define SDE_CLK_CTRL_WB_VALID(x) (x >= SDE_CLK_CTRL_WB0 && x < SDE_CLK_CTRL_LUTDMA)
#define SDE_CLK_CTRL_LUTDMA_VALID(x) (x == SDE_CLK_CTRL_LUTDMA)
#define SDE_CLK_CTRL_IPCC_MSI_VALID(x) (x == SDE_CLK_CTRL_IPCC_MSI)
@@ -1104,18 +1092,12 @@ static const char *sde_clk_ctrl_type_s[SDE_CLK_CTRL_MAX] = {
[SDE_CLK_CTRL_VIG2] = "VIG2",
[SDE_CLK_CTRL_VIG3] = "VIG3",
[SDE_CLK_CTRL_VIG4] = "VIG4",
[SDE_CLK_CTRL_RGB0] = "RGB0",
[SDE_CLK_CTRL_RGB1] = "RGB1",
[SDE_CLK_CTRL_RGB2] = "RGB2",
[SDE_CLK_CTRL_RGB3] = "RGB3",
[SDE_CLK_CTRL_DMA0] = "DMA0",
[SDE_CLK_CTRL_DMA1] = "DMA1",
[SDE_CLK_CTRL_DMA2] = "DMA2",
[SDE_CLK_CTRL_DMA3] = "DMA3",
[SDE_CLK_CTRL_DMA4] = "DMA4",
[SDE_CLK_CTRL_DMA5] = "DMA5",
[SDE_CLK_CTRL_CURSOR0] = "CURSOR0",
[SDE_CLK_CTRL_CURSOR1] = "CURSOR1",
[SDE_CLK_CTRL_WB0] = "WB0",
[SDE_CLK_CTRL_WB1] = "WB1",
[SDE_CLK_CTRL_WB2] = "WB2",
@@ -1791,7 +1773,6 @@ struct sde_perf_cfg {
* @irq_offset_list list of sde_intr_irq_offsets to initialize irq table
* @features bitmap of supported SDE_FEATUREs
* @dma_formats supported formats for dma pipe
* @cursor_formats supported formats for cursor pipe
* @vig_formats supported formats for vig pipe
* @wb_formats supported formats for wb
* @virt_vig_formats supported formats for virtual vig pipe
@@ -1902,7 +1883,6 @@ struct sde_mdss_cfg {
/* Supported Pixel Format Lists */
struct sde_format_extended *dma_formats;
struct sde_format_extended *cursor_formats;
struct sde_format_extended *vig_formats;
struct sde_format_extended *wb_formats;
struct sde_format_extended *virt_vig_formats;
@@ -1924,9 +1904,7 @@ struct sde_mdss_hw_cfg_handler {
#define BLK_MDP(s) ((s)->mdp)
#define BLK_CTL(s) ((s)->ctl)
#define BLK_VIG(s) ((s)->vig)
#define BLK_RGB(s) ((s)->rgb)
#define BLK_DMA(s) ((s)->dma)
#define BLK_CURSOR(s) ((s)->cursor)
#define BLK_MIXER(s) ((s)->mixer)
#define BLK_DSPP(s) ((s)->dspp)
#define BLK_DS(s) ((s)->ds)

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@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2019, 2021 The Linux Foundation. All rights reserved.
*/
@@ -88,23 +89,6 @@ static const struct sde_format_extended plane_formats_vig[] = {
{0, 0},
};
static const struct sde_format_extended cursor_formats[] = {
{DRM_FORMAT_ARGB8888, 0},
{DRM_FORMAT_ABGR8888, 0},
{DRM_FORMAT_RGBA8888, 0},
{DRM_FORMAT_BGRA8888, 0},
{DRM_FORMAT_XRGB8888, 0},
{DRM_FORMAT_ARGB1555, 0},
{DRM_FORMAT_ABGR1555, 0},
{DRM_FORMAT_RGBA5551, 0},
{DRM_FORMAT_BGRA5551, 0},
{DRM_FORMAT_ARGB4444, 0},
{DRM_FORMAT_ABGR4444, 0},
{DRM_FORMAT_RGBA4444, 0},
{DRM_FORMAT_BGRA4444, 0},
{0, 0},
};
static const struct sde_format_extended wb2_formats[] = {
{DRM_FORMAT_RGB565, 0},
{DRM_FORMAT_BGR565, DRM_FORMAT_MOD_QCOM_COMPRESSED},

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@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
@@ -76,8 +77,7 @@
/**
* List of SSPP bits in CTL_FLUSH
*/
static const u32 sspp_tbl[SSPP_MAX] = { SDE_NONE, 0, 1, 2, 18, 3, 4, 5,
19, 11, 12, 24, 25, 13, 14, SDE_NONE, SDE_NONE};
static const u32 sspp_tbl[SSPP_MAX] = { SDE_NONE, 0, 1, 2, 18, 11, 12, 24, 25, 13, 14};
/**
* List of layer mixer bits in CTL_FLUSH
@@ -125,9 +125,7 @@ static const u32 intf_tbl[INTF_MAX] = {SDE_NONE, 31, 30, 29, 28};
/**
* List of SSPP bits in CTL_FETCH_PIPE_ACTIVE
*/
static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19,
CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0,
1, 2, 3, 4, 5, CTL_INVALID_BIT, CTL_INVALID_BIT};
static const u32 fetch_tbl[SSPP_MAX] = {CTL_INVALID_BIT, 16, 17, 18, 19, 0, 1, 2, 3, 4, 5};
/**
* list of WB bits in CTL_WB_FLUSH
@@ -214,18 +212,12 @@ sspp_reg_cfg_tbl[SSPP_MAX][CTL_SSPP_MAX_RECTS] = {
/* SSPP_VIG1 */{ {0, 3, 3, BIT(2)}, {3, 4, 4, 0} },
/* SSPP_VIG2 */{ {0, 6, 3, BIT(4)}, {3, 8, 4, 0} },
/* SSPP_VIG3 */{ {0, 26, 3, BIT(6)}, {3, 12, 4, 0} },
/* SSPP_RGB0 */{ {0, 9, 3, BIT(8)}, {0, 0, 0, 0} },
/* SSPP_RGB1 */{ {0, 12, 3, BIT(10)}, {0, 0, 0, 0} },
/* SSPP_RGB2 */{ {0, 15, 3, BIT(12)}, {0, 0, 0, 0} },
/* SSPP_RGB3 */{ {0, 29, 3, BIT(14)}, {0, 0, 0, 0} },
/* SSPP_DMA0 */{ {0, 18, 3, BIT(16)}, {2, 8, 4, 0} },
/* SSPP_DMA1 */{ {0, 21, 3, BIT(18)}, {2, 12, 4, 0} },
/* SSPP_DMA2 */{ {2, 0, 4, 0}, {2, 16, 4, 0} },
/* SSPP_DMA3 */{ {2, 4, 4, 0}, {2, 20, 4, 0} },
/* SSPP_DMA4 */{ {4, 0, 4, 0}, {4, 8, 4, 0} },
/* SSPP_DMA5 */{ {4, 4, 4, 0}, {4, 12, 4, 0} },
/* SSPP_CURSOR0 */{ {1, 20, 4, 0}, {0, 0, 0, 0} },
/* SSPP_CURSOR1 */{ {1, 26, 4, 0}, {0, 0, 0, 0} }
};
/**

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@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
@@ -146,11 +146,6 @@ enum sde_sspp {
SSPP_VIG2,
SSPP_VIG3,
SSPP_VIG_MAX = SSPP_VIG3,
SSPP_RGB0,
SSPP_RGB1,
SSPP_RGB2,
SSPP_RGB3,
SSPP_RGB_MAX = SSPP_RGB3,
SSPP_DMA0,
SSPP_DMA1,
SSPP_DMA2,
@@ -158,23 +153,16 @@ enum sde_sspp {
SSPP_DMA4,
SSPP_DMA5,
SSPP_DMA_MAX = SSPP_DMA5,
SSPP_CURSOR0,
SSPP_CURSOR1,
SSPP_CURSOR_MAX = SSPP_CURSOR1,
SSPP_MAX
};
#define SDE_SSPP_VALID(x) ((x) > SSPP_NONE && (x) < SSPP_MAX)
#define SDE_SSPP_VALID_VIG(x) ((x) >= SSPP_VIG0 && (x) <= SSPP_VIG_MAX)
#define SDE_SSPP_VALID_RGB(x) ((x) >= SSPP_RGB0 && (x) <= SSPP_RGB_MAX)
#define SDE_SSPP_VALID_DMA(x) ((x) >= SSPP_DMA0 && (x) <= SSPP_DMA_MAX)
#define SDE_SSPP_VALID_CURSOR(x) ((x) >= SSPP_CURSOR0 && (x) <= SSPP_CURSOR_MAX)
enum sde_sspp_type {
SSPP_TYPE_VIG,
SSPP_TYPE_RGB,
SSPP_TYPE_DMA,
SSPP_TYPE_CURSOR,
SSPP_TYPE_MAX
};

View File

@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
@@ -185,7 +186,6 @@ static inline int _sspp_subblk_offset(struct sde_hw_pipe *ctx,
break;
case SDE_SSPP_SCALER_QSEED2:
case SDE_SSPP_SCALER_QSEED3:
case SDE_SSPP_SCALER_RGB:
*idx = sblk->scaler_blk.base;
break;
case SDE_SSPP_CSC:

View File

@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
@@ -30,8 +31,7 @@ struct sde_hw_pipe;
/**
* Define all scaler feature bits in catalog
*/
#define SDE_SSPP_SCALER ((1UL << SDE_SSPP_SCALER_RGB) | \
(1UL << SDE_SSPP_SCALER_QSEED2) | \
#define SDE_SSPP_SCALER ((1UL << SDE_SSPP_SCALER_QSEED2) | \
(1UL << SDE_SSPP_SCALER_QSEED3) | \
(1UL << SDE_SSPP_SCALER_QSEED3LITE))

View File

@@ -1,4 +1,5 @@
/*
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
@@ -2101,8 +2102,7 @@ static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
for (i = 0; i < catalog->sspp_count; i++) {
bool primary = true;
if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
|| primary_planes_idx >= max_crtc_count)
if (primary_planes_idx >= max_crtc_count)
primary = false;
plane = sde_plane_init(dev, catalog->sspp[i].id, primary,

View File

@@ -1,4 +1,5 @@
/*
* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (C) 2014-2021 The Linux Foundation. All rights reserved.
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
@@ -3226,12 +3227,10 @@ static void _sde_plane_update_properties(struct drm_plane *plane,
SDE_PLANE_DIRTY_FORMAT))
_sde_plane_set_qos_lut(plane, crtc, fb);
if (plane->type != DRM_PLANE_TYPE_CURSOR) {
_sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
_sde_plane_set_ot_limit(plane, crtc);
if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
_sde_plane_set_ts_prefill(plane, pstate);
}
if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
_sde_plane_set_qos_remap(plane);
@@ -3720,8 +3719,6 @@ static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
if (SDE_SSPP_VALID_VIG(psde->pipe))
pipe_id = psde->pipe - SSPP_VIG0;
else if (SDE_SSPP_VALID_RGB(psde->pipe))
pipe_id = psde->pipe - SSPP_RGB0;
else if (SDE_SSPP_VALID_DMA(psde->pipe))
pipe_id = psde->pipe - SSPP_DMA0;
else
@@ -4843,9 +4840,7 @@ struct drm_plane *sde_plane_init(struct drm_device *dev,
goto clean_sspp;
}
if (psde->features & BIT(SDE_SSPP_CURSOR))
type = DRM_PLANE_TYPE_CURSOR;
else if (primary_plane)
if (primary_plane)
type = DRM_PLANE_TYPE_PRIMARY;
else
type = DRM_PLANE_TYPE_OVERLAY;