qcacmn: WBM ring changes to fix stability issues
1. Increased the sizes of following SRNGs used by WBM and also added max size check in SRNG setup: -idle link descriptor ring -Tx completion ring -Rx release ing 2. As per HW team, TP_ADDR and HP_ADDR for Idle link ring should remain 0 to avoid some WBM stability issues. Remote head/tail pointers are not required since this ring is completly managed by WBM HW Change-Id: I93d70a287329dfeb08fcfb6b04306d65776b4834
此提交包含在:
@@ -42,8 +42,9 @@ static int dp_srng_setup(struct dp_soc *soc, struct dp_srng *srng,
|
||||
/* TODO: See if we should get align size from hal */
|
||||
uint32_t ring_base_align = 8;
|
||||
struct hal_srng_params ring_params;
|
||||
uint32_t max_entries = hal_srng_max_entries(hal_soc, ring_type);
|
||||
|
||||
|
||||
num_entries = (num_entries > max_entries) ? max_entries : num_entries;
|
||||
srng->hal_srng = NULL;
|
||||
srng->alloc_size = (num_entries * entry_size) + ring_base_align - 1;
|
||||
srng->base_vaddr_unaligned = qdf_mem_alloc_consistent(
|
||||
@@ -688,11 +689,12 @@ static void dp_hw_link_desc_pool_cleanup(struct dp_soc *soc)
|
||||
/* TODO: Following should be configurable */
|
||||
#define WBM_RELEASE_RING_SIZE 64
|
||||
#define TCL_DATA_RING_SIZE 512
|
||||
#define TX_COMP_RING_SIZE 1024
|
||||
#define TCL_CMD_RING_SIZE 32
|
||||
#define TCL_STATUS_RING_SIZE 32
|
||||
#define REO_DST_RING_SIZE 2048
|
||||
#define REO_REINJECT_RING_SIZE 32
|
||||
#define RX_RELEASE_RING_SIZE 256
|
||||
#define RX_RELEASE_RING_SIZE 1024
|
||||
#define REO_EXCEPTION_RING_SIZE 128
|
||||
#define REO_CMD_RING_SIZE 32
|
||||
#define REO_STATUS_RING_SIZE 32
|
||||
@@ -746,7 +748,7 @@ static int dp_soc_cmn_setup(struct dp_soc *soc)
|
||||
goto fail1;
|
||||
}
|
||||
if (dp_srng_setup(soc, &soc->tx_comp_ring[i],
|
||||
WBM2SW_RELEASE, i, 0, TCL_DATA_RING_SIZE)) {
|
||||
WBM2SW_RELEASE, i, 0, TX_COMP_RING_SIZE)) {
|
||||
QDF_TRACE(QDF_MODULE_ID_DP,
|
||||
QDF_TRACE_LEVEL_ERROR,
|
||||
FL("dp_srng_setup failed for tx_comp_ring[%d]"), i);
|
||||
|
@@ -101,6 +101,15 @@ enum hal_ring_type {
|
||||
*/
|
||||
extern uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type);
|
||||
|
||||
/**
|
||||
* hal_srng_max_entries - Returns maximum possible number of ring entries
|
||||
* @hal_soc: Opaque HAL SOC handle
|
||||
* @ring_type: one of the types from hal_ring_type
|
||||
*
|
||||
* Return: Maximum number of entries for the given ring_type
|
||||
*/
|
||||
uint32_t hal_srng_max_entries(void *hal_soc, int ring_type);
|
||||
|
||||
/* SRNG parameters to be passed to hal_srng_setup */
|
||||
struct hal_srng_params {
|
||||
/* Physical base address of the ring */
|
||||
|
@@ -156,6 +156,9 @@
|
||||
#define SRNG_MS(_reg_fld, _val) \
|
||||
(((_val) & _SRNG_FM(_reg_fld)) >> _SRNG_FS(_reg_fld))
|
||||
|
||||
#define SRNG_MAX_SIZE_DWORDS \
|
||||
(SRNG_MS(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 0xffffffff))
|
||||
|
||||
/**
|
||||
* HW ring configuration table to identify hardware ring attributes like
|
||||
* register addresses, number of rings, ring entry size etc., for each type
|
||||
@@ -833,11 +836,17 @@ static inline void hal_srng_src_hw_init(struct hal_soc *hal,
|
||||
|
||||
SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val);
|
||||
|
||||
/* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should
|
||||
* remain 0 to avoid some WBM stability issues. Remote head/tail
|
||||
* pointers are not required since this ring is completly managed
|
||||
* by WBM HW */
|
||||
if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) {
|
||||
tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr +
|
||||
((unsigned long)(srng->u.src_ring.tp_addr) -
|
||||
(unsigned long)(hal->shadow_rdptr_mem_vaddr)));
|
||||
SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff);
|
||||
SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32);
|
||||
}
|
||||
|
||||
/* Initilaize head and tail pointers to indicate ring is empty */
|
||||
SRNG_SRC_REG_WRITE(srng, HP, 0);
|
||||
@@ -1155,6 +1164,19 @@ uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type)
|
||||
return ring_config->entry_size << 2;
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_srng_max_entries - Returns maximum possible number of ring entries
|
||||
* @hal_soc: Opaque HAL SOC handle
|
||||
* @ring_type: one of the types from hal_ring_type
|
||||
*
|
||||
* Return: Maximum number of entries for the given ring_type
|
||||
*/
|
||||
uint32_t hal_srng_max_entries(void *hal_soc, int ring_type)
|
||||
{
|
||||
struct hal_hw_srng_config *ring_config = HAL_SRNG_CONFIG(hal, ring_type);
|
||||
return SRNG_MAX_SIZE_DWORDS / ring_config->entry_size;
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_get_srng_params - Retreive SRNG parameters for a given ring from HAL
|
||||
*
|
||||
|
@@ -62,7 +62,7 @@
|
||||
/* Change this to a lower value to enforce scattered idle list mode */
|
||||
#define WLAN_CFG_MAX_ALLOC_SIZE (32 << 20)
|
||||
|
||||
# define WLAN_CFG_MAX_CLIENTS 32
|
||||
#define WLAN_CFG_MAX_CLIENTS 64
|
||||
|
||||
#define WLAN_CFG_PER_PDEV_TX_RING 1
|
||||
#define WLAN_CFG_NUM_TCL_DATA_RINGS 3
|
||||
|
新增問題並參考
封鎖使用者