qcacmn: Optimize DP Rx Error Handling (Part-2)
In WBM2SW Rx Error path for BE specific functionality 1) HAL API's/Function pointers are replaced with specific function calls. 2) Efficient read/write of WBM Error Info from HAL Rx desc. 3) Minimize reading data from Nbuf TLV. Change-Id: Ic8793ffcbeb2411c9b81fb32acae062e8a1f40cc CRs-Fixed: 3362828
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committed by
Madan Koyyalamudi

parent
df5ce68791
commit
d0d9a987fc
@@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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@@ -86,26 +86,62 @@ enum {
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/**
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* struct hal_wbm_err_desc_info - structure to hold wbm error codes and reasons
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*
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* @reo_psh_rsn: REO push reason
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* @reo_err_code: REO Error code
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* @rxdma_psh_rsn: RXDMA push reason
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* @rxdma_err_code: RXDMA Error code
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* @reserved_1: Reserved bits
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* @wbm_err_src: WBM error source
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* @pool_id: pool ID, indicates which rxdma pool
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* @msdu_continued: Is the MSDU continued
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* @reserved_2: Reserved bits
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* The fields of this structure is aligned to HAL Rx WBM2SW Ring desc,
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* inorder to efficiently copy the data from desc to struct.
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* Do not change the sequence of the fields.
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*
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* @wbm_err_src: Module which initiated the buffer release
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* @bm_action: BM action
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* @buffer_or_desc_type: Type of Buffer or Desc released
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* @return_buffer_manager: Buffer address Info for debug
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* @pool_id: pool ID, indicates which rxdma pool
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* @cache_id: cache Id
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* @cookie_conversion_status: cookie conversion status
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* @rxdma_psh_rsn: RXDMA push reason
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* @rxdma_err_code: RXDMA Error code
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* @reo_psh_rsn: REO push reason
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* @reo_err_code: REO Error code
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* @wbm_internal_error: WBM Internal error
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*/
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struct hal_wbm_err_desc_info {
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uint16_t reo_psh_rsn:2,
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reo_err_code:5,
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rxdma_psh_rsn:2,
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rxdma_err_code:5,
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reserved_1:2;
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uint8_t wbm_err_src:3,
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pool_id:2,
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msdu_continued:1,
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reserved_2:2;
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t wbm_err_src : 3,
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bm_action : 3,
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buffer_or_desc_type : 3,
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return_buffer_manager : 4,
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pool_id : 2,
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cache_id : 1,
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cookie_conversion_status : 1,
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rxdma_psh_rsn : 2,
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rxdma_err_code : 5,
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reo_psh_rsn : 2,
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reo_err_code : 5,
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wbm_internal_error : 1;
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#else
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uint32_t wbm_internal_error : 1,
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reo_err_code : 5,
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reo_psh_rsn : 2,
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rxdma_err_code : 5,
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rxdma_psh_rsn : 2,
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cookie_conversion_status : 1,
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cache_id : 1,
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pool_id : 2,
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return_buffer_manager : 4,
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buffer_or_desc_type : 3,
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bm_action : 3,
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wbm_err_src : 3;
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#endif
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};
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/**
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* union hal_wbm_err_info_u - Union to hold wbm error information
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* @info_bit: hal_wbm_err_desc_info: structure to hold wbm error info bit fields
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* @info: variable to hold wbm error info
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*
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*/
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union hal_wbm_err_info_u {
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struct hal_wbm_err_desc_info info_bit;
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uint32_t info;
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};
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/**
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