qcacmn: Separate hal for qca6290 and qca8074
Create separate individual hal_srng_table and hal register offset in target specific source files. Create separate functions for qca6290 and qca8074 for few hal rx tx functions as the macro value differs between the chipsets. Assign target specific hal tx, rx ops as part of hal_attach and call respective hal tx, rx ops through callbacks. Change-Id: Ibbf490c678c39fdd9d54191aad7aaec786db30ec
This commit is contained in:
Balamurugan Mahalingam
committed by
nshrivas
nshrivas
parent
8ae6415cba
commit
d0159640ea
@@ -454,33 +454,6 @@ static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw)
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HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw);
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}
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/**
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* hal_tx_desc_set_dscp_tid_table_id - Sets DSCP to TID conversion table ID
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* @desc: Handle to Tx Descriptor
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* @id: DSCP to tid conversion table to be used for this frame
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*
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* Return: void
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*/
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#if !defined(QCA_WIFI_QCA6290_11AX)
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static inline void hal_tx_desc_set_dscp_tid_table_id(void *desc,
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uint8_t id)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_3,
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DSCP_TO_TID_PRIORITY_TABLE_ID) |=
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HAL_TX_SM(TCL_DATA_CMD_3,
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DSCP_TO_TID_PRIORITY_TABLE_ID, id);
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}
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#else
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static inline void hal_tx_desc_set_dscp_tid_table_id(void *desc,
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uint8_t id)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_5,
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DSCP_TID_TABLE_NUM) |=
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HAL_TX_SM(TCL_DATA_CMD_5,
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DSCP_TID_TABLE_NUM, id);
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}
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#endif
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/**
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* hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor
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* @desc: Handle to Tx Descriptor
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@@ -515,31 +488,6 @@ static inline void hal_tx_desc_set_hlos_tid(void *desc,
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HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |=
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HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1);
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}
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#ifdef QCA_WIFI_QCA6290_11AX
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/**
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* hal_tx_desc_set_lmac_id - Set the lmac_id value
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* @desc: Handle to Tx Descriptor
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* @lmac_id: mac Id to ast matching
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* b00 – mac 0
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* b01 – mac 1
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* b10 – mac 2
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* b11 – all macs (legacy HK way)
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_lmac_id(void *desc,
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uint8_t lmac_id)
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{
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HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |=
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HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id);
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}
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#else
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static inline void hal_tx_desc_set_lmac_id(void *desc,
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uint8_t lmac_id)
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{
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}
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#endif
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/**
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* hal_tx_desc_sync - Commit the descriptor to Hardware
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* @hal_tx_des_cached: Cached descriptor that software maintains
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@@ -1005,199 +953,6 @@ static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc)
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qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN);
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}
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#if !defined(QCA_WIFI_QCA6290_11AX)
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/**
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* hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table
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* @soc: HAL SoC context
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* @map: DSCP-TID mapping table
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* @id: mapping table ID - 0,1
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*
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* DSCP are mapped to 8 TID values using TID values programmed
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* in two set of mapping registers DSCP_TID1_MAP_<0 to 6> (id = 0)
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* and DSCP_TID2_MAP_<0 to 6> (id = 1)
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* Each mapping register has TID mapping for 10 DSCP values
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*
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* Return: none
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*/
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static inline void hal_tx_set_dscp_tid_map(void *hal_soc, uint8_t *map,
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uint8_t id)
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{
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int i;
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uint32_t addr;
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uint32_t value;
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struct hal_soc *soc = (struct hal_soc *)hal_soc;
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if (id == HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT) {
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addr =
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HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
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} else {
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addr =
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HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
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}
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for (i = 0; i < 64; i += 10) {
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value = (map[i] |
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(map[i+1] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_SHFT) |
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(map[i+2] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_SHFT) |
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(map[i+3] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_SHFT) |
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(map[i+4] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_SHFT) |
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(map[i+5] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_SHFT) |
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(map[i+6] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_SHFT) |
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(map[i+7] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_SHFT) |
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(map[i+8] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_SHFT) |
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(map[i+9] << HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_SHFT));
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HAL_REG_WRITE(soc, addr,
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(value & HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK));
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addr += 4;
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}
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}
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/**
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* hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user
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* @soc: HAL SoC context
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* @map: DSCP-TID mapping table
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* @id : MAP ID
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* @dscp: DSCP_TID map index
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*
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* Return: void
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*/
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static inline void hal_tx_update_dscp_tid(void *hal_soc, uint8_t tid,
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uint8_t id, uint8_t dscp)
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{
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int index;
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uint32_t addr;
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uint32_t value;
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uint32_t regval;
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struct hal_soc *soc = (struct hal_soc *)hal_soc;
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if (id == HAL_TX_DSCP_TID_MAP_TABLE_DEFAULT)
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addr =
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HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
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else
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addr =
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HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
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index = dscp % HAL_TX_NUM_DSCP_PER_REGISTER;
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addr += 4 * (dscp/HAL_TX_NUM_DSCP_PER_REGISTER);
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value = tid << (HAL_TX_BITS_PER_TID * index);
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/* Read back previous DSCP TID config and update
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* with new config.
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*/
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regval = HAL_REG_READ(soc, addr);
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regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * index));
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regval |= value;
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HAL_REG_WRITE(soc, addr,
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(regval & HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK));
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}
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#else
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#define DSCP_TID_TABLE_SIZE 24
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#define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE/4)
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/**
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* hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table
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* @soc: HAL SoC context
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* @map: DSCP-TID mapping table
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* @id: mapping table ID - 0-31
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*
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* DSCP are mapped to 8 TID values using TID values programmed
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* in any of the 32 DSCP_TID_MAPS (id = 0-31).
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*
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* Return: none
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*/
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static inline void hal_tx_set_dscp_tid_map(void *hal_soc, uint8_t *map,
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uint8_t id)
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{
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int i;
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uint32_t addr, cmn_reg_addr;
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uint32_t value = 0, regval;
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uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
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struct hal_soc *soc = (struct hal_soc *)hal_soc;
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if (id >= HAL_MAX_HW_DSCP_TID_MAPS_11AX) {
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return;
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}
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cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
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addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
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id * NUM_WORDS_PER_DSCP_TID_TABLE);
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/* Enable read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval |=
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(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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/* Write 8 (24 bits) DSCP-TID mappings in each interation */
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for (i = 0; i < 64; i += 8) {
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value = (map[i] |
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(map[i+1] << 0x3) |
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(map[i+2] << 0x6) |
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(map[i+3] << 0x9) |
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(map[i+4] << 0xc) |
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(map[i+5] << 0xf) |
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(map[i+6] << 0x12) |
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(map[i+7] << 0x15));
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qdf_mem_copy(&val[cnt], (void *)&value, 3);
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cnt += 3;
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}
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for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
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regval = *(uint32_t *)(val + i);
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HAL_REG_WRITE(soc, addr,
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(regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
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addr += 4;
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}
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/* Diasble read/write access */
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regval = HAL_REG_READ(soc, cmn_reg_addr);
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regval &=
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~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
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HAL_REG_WRITE(soc, cmn_reg_addr, regval);
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}
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static inline void hal_tx_update_dscp_tid(void *hal_soc, uint8_t tid,
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uint8_t id, uint8_t dscp)
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{
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int index;
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uint32_t addr;
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uint32_t value;
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uint32_t regval;
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struct hal_soc *soc = (struct hal_soc *)hal_soc;
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addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, id);
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index = dscp % HAL_TX_NUM_DSCP_PER_REGISTER;
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addr += 4 * (dscp/HAL_TX_NUM_DSCP_PER_REGISTER);
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value = tid << (HAL_TX_BITS_PER_TID * index);
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regval = HAL_REG_READ(soc, addr);
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regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * index));
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regval |= value;
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HAL_REG_WRITE(soc, addr,
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(regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
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}
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#endif
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/**
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* hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG
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* @hal_soc: Handle to HAL SoC structure
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@@ -1214,15 +969,77 @@ static inline void hal_tx_init_data_ring(void *hal_soc, void *hal_srng)
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hal_get_srng_params(hal_soc, hal_srng, &srng_params);
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desc_addr = (uint8_t *) srng_params.ring_base_vaddr;
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desc_addr = (uint8_t *)srng_params.ring_base_vaddr;
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desc_size = sizeof(struct tcl_data_cmd);
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num_desc = srng_params.num_entries;
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while (num_desc) {
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HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG,
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desc_size);
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desc_size);
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desc_addr += (desc_size + sizeof(struct tlv_32_hdr));
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num_desc--;
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}
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}
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/**
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* hal_tx_desc_set_dscp_tid_table_id() - Sets DSCP to TID conversion table ID
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* @hal_soc: Handle to HAL SoC structure
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* @desc: Handle to Tx Descriptor
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* @id: DSCP to tid conversion table to be used for this frame
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_dscp_tid_table_id(struct hal_soc *hal_soc,
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void *desc, uint8_t id)
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{
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hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id(desc, id);
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}
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/**
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* hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table
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*
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* @soc: HAL SoC context
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* @map: DSCP-TID mapping table
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* @id: mapping table ID - 0,1
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*
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* Return: void
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*/
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static inline void hal_tx_set_dscp_tid_map(struct hal_soc *hal_soc,
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uint8_t *map, uint8_t id)
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{
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hal_soc->ops->hal_tx_set_dscp_tid_map(hal_soc, map, id);
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}
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/**
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* hal_tx_update_dscp_tid() - Update the dscp tid map table as updated by user
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*
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* @soc: HAL SoC context
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* @map: DSCP-TID mapping table
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* @id : MAP ID
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* @dscp: DSCP_TID map index
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*
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* Return: void
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*/
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static inline void hal_tx_update_dscp_tid(struct hal_soc *hal_soc, uint8_t tid,
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uint8_t id, uint8_t dscp)
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{
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hal_soc->ops->hal_tx_update_dscp_tid(hal_soc, tid, id, dscp);
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}
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/**
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* hal_tx_desc_set_lmac_id - Set the lmac_id value
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* @desc: Handle to Tx Descriptor
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* @lmac_id: mac Id to ast matching
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* b00 – mac 0
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* b01 – mac 1
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* b10 – mac 2
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* b11 – all macs (legacy HK way)
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_lmac_id(struct hal_soc *hal_soc,
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void *desc, uint8_t lmac_id)
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{
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hal_soc->ops->hal_tx_desc_set_lmac_id(desc, lmac_id);
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}
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#endif /* HAL_TX_H */
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