qcacmn: Separate hal for qca6290 and qca8074
Create separate individual hal_srng_table and hal register offset in target specific source files. Create separate functions for qca6290 and qca8074 for few hal rx tx functions as the macro value differs between the chipsets. Assign target specific hal tx, rx ops as part of hal_attach and call respective hal tx, rx ops through callbacks. Change-Id: Ibbf490c678c39fdd9d54191aad7aaec786db30ec
This commit is contained in:
Balamurugan Mahalingam
committed by
nshrivas
nshrivas
parent
8ae6415cba
commit
d0159640ea
@@ -26,547 +26,17 @@
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "hal_hw_headers.h"
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#include "hal_api.h"
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#include "target_type.h"
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#include "wcss_version.h"
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#include "qdf_module.h"
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/**
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* Common SRNG register access macros:
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* The SRNG registers are distributed across various UMAC and LMAC HW blocks,
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* but the register group and format is exactly same for all rings, with some
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* difference between producer rings (these are 'producer rings' with respect
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* to HW and referred as 'destination rings' in SW) and consumer rings (these
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* are 'consumer rings' with respect to HW and referred as 'source rings' in SW).
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* The following macros provide uniform access to all SRNG rings.
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*/
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/* SRNG registers are split among two groups R0 and R2 and following
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* definitions identify the group to which each register belongs to
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*/
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#define R0_INDEX 0
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#define R2_INDEX 1
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#define HWREG_INDEX(_reg_group) _reg_group ## _ ## INDEX
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/* Registers in R0 group */
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#define BASE_LSB_GROUP R0
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#define BASE_MSB_GROUP R0
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#define ID_GROUP R0
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#define STATUS_GROUP R0
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#define MISC_GROUP R0
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#define HP_ADDR_LSB_GROUP R0
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#define HP_ADDR_MSB_GROUP R0
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#define PRODUCER_INT_SETUP_GROUP R0
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#define PRODUCER_INT_STATUS_GROUP R0
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#define PRODUCER_FULL_COUNTER_GROUP R0
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#define MSI1_BASE_LSB_GROUP R0
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#define MSI1_BASE_MSB_GROUP R0
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#define MSI1_DATA_GROUP R0
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#define HP_TP_SW_OFFSET_GROUP R0
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#define TP_ADDR_LSB_GROUP R0
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#define TP_ADDR_MSB_GROUP R0
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#define CONSUMER_INT_SETUP_IX0_GROUP R0
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#define CONSUMER_INT_SETUP_IX1_GROUP R0
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#define CONSUMER_INT_STATUS_GROUP R0
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#define CONSUMER_EMPTY_COUNTER_GROUP R0
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#define CONSUMER_PREFETCH_TIMER_GROUP R0
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#define CONSUMER_PREFETCH_STATUS_GROUP R0
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/* Registers in R2 group */
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#define HP_GROUP R2
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#define TP_GROUP R2
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/**
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* Register definitions for all SRNG based rings are same, except few
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* differences between source (HW consumer) and destination (HW producer)
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* registers. Following macros definitions provide generic access to all
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* SRNG based rings.
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* For source rings, we will use the register/field definitions of SW2TCL1
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* ring defined in the HW header file mac_tcl_reg_seq_hwioreg.h. To setup
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* individual fields, SRNG_SM macros should be used with fields specified
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* using SRNG_SRC_FLD(<register>, <field>), Register writes should be done
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* using SRNG_SRC_REG_WRITE(<hal_srng>, <register>, <value>).
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* Similarly for destination rings we will use definitions of REO2SW1 ring
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* defined in the register reo_destination_ring.h. To setup individual
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* fields SRNG_SM macros should be used with fields specified using
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* SRNG_DST_FLD(<register>, <field>). Register writes should be done using
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* SRNG_DST_REG_WRITE(<hal_srng>, <register>, <value>).
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*/
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#define SRNG_DST_REG_OFFSET(_reg, _reg_group) \
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HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg##_ADDR(0)
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#define SRNG_SRC_REG_OFFSET(_reg, _reg_group) \
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HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg ## _ADDR(0)
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#define _SRNG_DST_FLD(_reg_group, _reg_fld) \
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HWIO_REO_ ## _reg_group ## _REO2SW1_RING_ ## _reg_fld
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#define _SRNG_SRC_FLD(_reg_group, _reg_fld) \
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HWIO_TCL_ ## _reg_group ## _SW2TCL1_RING_ ## _reg_fld
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#define _SRNG_FLD(_reg_group, _reg_fld, _dir) \
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_SRNG_ ## _dir ## _FLD(_reg_group, _reg_fld)
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#define SRNG_DST_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, DST)
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#define SRNG_SRC_FLD(_reg, _f) _SRNG_FLD(_reg ## _GROUP, _reg ## _ ## _f, SRC)
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#define SRNG_SRC_R0_START_OFFSET SRNG_SRC_REG_OFFSET(BASE_LSB, R0)
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#define SRNG_DST_R0_START_OFFSET SRNG_DST_REG_OFFSET(BASE_LSB, R0)
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#define SRNG_SRC_R2_START_OFFSET SRNG_SRC_REG_OFFSET(HP, R2)
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#define SRNG_DST_R2_START_OFFSET SRNG_DST_REG_OFFSET(HP, R2)
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#define SRNG_SRC_START_OFFSET(_reg_group) \
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SRNG_SRC_ ## _reg_group ## _START_OFFSET
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#define SRNG_DST_START_OFFSET(_reg_group) \
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SRNG_DST_ ## _reg_group ## _START_OFFSET
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#define SRNG_REG_ADDR(_srng, _reg, _reg_group, _dir) \
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((_srng)->hwreg_base[HWREG_INDEX(_reg_group)] + \
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SRNG_ ## _dir ## _REG_OFFSET(_reg, _reg_group) - \
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SRNG_ ## _dir ## _START_OFFSET(_reg_group))
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#define SRNG_DST_ADDR(_srng, _reg) \
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SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, DST)
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#define SRNG_SRC_ADDR(_srng, _reg) \
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SRNG_REG_ADDR(_srng, _reg, _reg ## _GROUP, SRC)
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#define SRNG_REG_WRITE(_srng, _reg, _value, _dir) \
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hal_write_address_32_mb(_srng->hal_soc, SRNG_ ## _dir ## _ADDR(_srng, _reg), (_value))
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#define SRNG_REG_READ(_srng, _reg, _dir) \
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hal_read_address_32_mb(_srng->hal_soc, SRNG_ ## _dir ## _ADDR(_srng, _reg))
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#define SRNG_SRC_REG_WRITE(_srng, _reg, _value) \
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SRNG_REG_WRITE(_srng, _reg, _value, SRC)
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#define SRNG_DST_REG_WRITE(_srng, _reg, _value) \
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SRNG_REG_WRITE(_srng, _reg, _value, DST)
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#define SRNG_SRC_REG_READ(_srng, _reg) \
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SRNG_REG_READ(_srng, _reg, SRC)
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#define _SRNG_FM(_reg_fld) _reg_fld ## _BMSK
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#define _SRNG_FS(_reg_fld) _reg_fld ## _SHFT
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#define SRNG_SM(_reg_fld, _val) \
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(((_val) << _SRNG_FS(_reg_fld)) & _SRNG_FM(_reg_fld))
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#define SRNG_MS(_reg_fld, _val) \
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(((_val) & _SRNG_FM(_reg_fld)) >> _SRNG_FS(_reg_fld))
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#define SRNG_MAX_SIZE_DWORDS \
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(SRNG_MS(SRNG_SRC_FLD(BASE_MSB, RING_SIZE), 0xffffffff))
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#define HAL_RXDMA_MAX_RING_SIZE 0xFFFF
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/**
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* HW ring configuration table to identify hardware ring attributes like
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* register addresses, number of rings, ring entry size etc., for each type
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* of SRNG ring.
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*
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* Currently there is just one HW ring table, but there could be multiple
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* configurations in future based on HW variants from the same wifi3.0 family
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* and hence need to be attached with hal_soc based on HW type
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*/
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#define HAL_SRNG_CONFIG(_hal_soc, _ring_type) (&hw_srng_table[_ring_type])
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static struct hal_hw_srng_config hw_srng_table[] = {
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/* TODO: max_rings can populated by querying HW capabilities */
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{ /* REO_DST */
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.start_ring_id = HAL_SRNG_REO2SW1,
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.max_rings = 4,
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.entry_size = sizeof(struct reo_destination_ring) >> 2,
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.lmac_ring = FALSE,
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.ring_dir = HAL_SRNG_DST_RING,
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.reg_start = {
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HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET)
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},
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.reg_size = {
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HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
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HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
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HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
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HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
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},
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.max_size = HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
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HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
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},
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{ /* REO_EXCEPTION */
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/* Designating REO2TCL ring as exception ring. This ring is
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* similar to other REO2SW rings though it is named as REO2TCL.
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* Any of theREO2SW rings can be used as exception ring.
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*/
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.start_ring_id = HAL_SRNG_REO2TCL,
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.max_rings = 1,
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.entry_size = sizeof(struct reo_destination_ring) >> 2,
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.lmac_ring = FALSE,
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.ring_dir = HAL_SRNG_DST_RING,
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.reg_start = {
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HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET)
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},
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/* Single ring - provide ring size if multiple rings of this
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* type are supported */
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.reg_size = {},
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.max_size = HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
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HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
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},
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{ /* REO_REINJECT */
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.start_ring_id = HAL_SRNG_SW2REO,
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.max_rings = 1,
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.entry_size = sizeof(struct reo_entrance_ring) >> 2,
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.lmac_ring = FALSE,
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.ring_dir = HAL_SRNG_SRC_RING,
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.reg_start = {
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HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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HWIO_REO_R2_SW2REO_RING_HP_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET)
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},
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/* Single ring - provide ring size if multiple rings of this
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* type are supported */
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.reg_size = {},
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.max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
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HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
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},
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{ /* REO_CMD */
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.start_ring_id = HAL_SRNG_REO_CMD,
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.max_rings = 1,
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.entry_size = (sizeof(struct tlv_32_hdr) +
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sizeof(struct reo_get_queue_stats)) >> 2,
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.lmac_ring = FALSE,
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.ring_dir = HAL_SRNG_SRC_RING,
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.reg_start = {
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HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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},
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/* Single ring - provide ring size if multiple rings of this
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* type are supported */
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.reg_size = {},
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.max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
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HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
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},
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{ /* REO_STATUS */
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.start_ring_id = HAL_SRNG_REO_STATUS,
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.max_rings = 1,
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.entry_size = (sizeof(struct tlv_32_hdr) +
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sizeof(struct reo_get_queue_stats_status)) >> 2,
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.lmac_ring = FALSE,
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.ring_dir = HAL_SRNG_DST_RING,
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.reg_start = {
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HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
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SEQ_WCSS_UMAC_REO_REG_OFFSET),
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},
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/* Single ring - provide ring size if multiple rings of this
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* type are supported */
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.reg_size = {},
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.max_size = HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
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HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
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},
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{ /* TCL_DATA */
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.start_ring_id = HAL_SRNG_SW2TCL1,
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.max_rings = 3,
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.entry_size = (sizeof(struct tlv_32_hdr) +
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sizeof(struct tcl_data_cmd)) >> 2,
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.lmac_ring = FALSE,
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.ring_dir = HAL_SRNG_SRC_RING,
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.reg_start = {
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HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
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HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
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},
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.reg_size = {
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HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
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HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
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HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
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HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
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},
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.max_size = HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
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HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
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},
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{ /* TCL_CMD */
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.start_ring_id = HAL_SRNG_SW2TCL_CMD,
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.max_rings = 1,
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.entry_size = (sizeof(struct tlv_32_hdr) +
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sizeof(struct tcl_gse_cmd)) >> 2,
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.lmac_ring = FALSE,
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.ring_dir = HAL_SRNG_SRC_RING,
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.reg_start = {
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HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
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HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
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},
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/* Single ring - provide ring size if multiple rings of this
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* type are supported */
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.reg_size = {},
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.max_size = HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
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HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
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},
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{ /* TCL_STATUS */
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.start_ring_id = HAL_SRNG_TCL_STATUS,
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.max_rings = 1,
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.entry_size = (sizeof(struct tlv_32_hdr) +
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sizeof(struct tcl_status_ring)) >> 2,
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.lmac_ring = FALSE,
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.ring_dir = HAL_SRNG_DST_RING,
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.reg_start = {
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HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
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HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
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SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
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},
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/* Single ring - provide ring size if multiple rings of this
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* type are supported */
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.reg_size = {},
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.max_size = HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
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HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
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},
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{ /* CE_SRC */
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.start_ring_id = HAL_SRNG_CE_0_SRC,
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.max_rings = 12,
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.entry_size = sizeof(struct ce_src_desc) >> 2,
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.lmac_ring = FALSE,
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.ring_dir = HAL_SRNG_SRC_RING,
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.reg_start = {
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HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
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SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
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HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
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SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
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},
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.reg_size = {
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SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
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SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
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SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
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SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
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},
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.max_size = HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
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HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
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},
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{ /* CE_DST */
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.start_ring_id = HAL_SRNG_CE_0_DST,
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.max_rings = 12,
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.entry_size = 8 >> 2,
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/*TODO: entry_size above should actually be
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* sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
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* of struct ce_dst_desc in HW header files
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*/
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.lmac_ring = FALSE,
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.ring_dir = HAL_SRNG_SRC_RING,
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.reg_start = {
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HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
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SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
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HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
|
||||
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
|
||||
},
|
||||
.reg_size = {
|
||||
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
|
||||
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
|
||||
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
|
||||
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
|
||||
},
|
||||
.max_size = HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||
HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||
},
|
||||
{ /* CE_DST_STATUS */
|
||||
.start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
|
||||
.max_rings = 12,
|
||||
.entry_size = sizeof(struct ce_stat_desc) >> 2,
|
||||
.lmac_ring = FALSE,
|
||||
.ring_dir = HAL_SRNG_DST_RING,
|
||||
.reg_start = {
|
||||
HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
|
||||
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
|
||||
HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
|
||||
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
|
||||
},
|
||||
/* TODO: check destination status ring registers */
|
||||
.reg_size = {
|
||||
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
|
||||
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
|
||||
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
|
||||
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
|
||||
},
|
||||
.max_size =
|
||||
HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||
HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||
},
|
||||
{ /* WBM_IDLE_LINK */
|
||||
.start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
|
||||
.max_rings = 1,
|
||||
.entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
|
||||
.lmac_ring = FALSE,
|
||||
.ring_dir = HAL_SRNG_SRC_RING,
|
||||
.reg_start = {
|
||||
HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||
HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||
},
|
||||
/* Single ring - provide ring size if multiple rings of this
|
||||
* type are supported */
|
||||
.reg_size = {},
|
||||
.max_size =
|
||||
HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||
HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||
},
|
||||
{ /* SW2WBM_RELEASE */
|
||||
.start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
|
||||
.max_rings = 1,
|
||||
.entry_size = sizeof(struct wbm_release_ring) >> 2,
|
||||
.lmac_ring = FALSE,
|
||||
.ring_dir = HAL_SRNG_SRC_RING,
|
||||
.reg_start = {
|
||||
HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||
HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||
},
|
||||
/* Single ring - provide ring size if multiple rings of this
|
||||
* type are supported */
|
||||
.reg_size = {},
|
||||
.max_size =
|
||||
HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||
HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||
},
|
||||
{ /* WBM2SW_RELEASE */
|
||||
.start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
|
||||
.max_rings = 4,
|
||||
.entry_size = sizeof(struct wbm_release_ring) >> 2,
|
||||
.lmac_ring = FALSE,
|
||||
.ring_dir = HAL_SRNG_DST_RING,
|
||||
.reg_start = {
|
||||
HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||
HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||
},
|
||||
.reg_size = {
|
||||
HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
|
||||
HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||
HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
|
||||
HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||
},
|
||||
.max_size =
|
||||
HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||
HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||
},
|
||||
{ /* RXDMA_BUF */
|
||||
.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
|
||||
#ifdef IPA_OFFLOAD
|
||||
.max_rings = 3,
|
||||
#else
|
||||
.max_rings = 2,
|
||||
#ifdef QCA_WIFI_QCA8074
|
||||
void hal_qca6290_attach(struct hal_soc *hal);
|
||||
#endif
|
||||
.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
|
||||
.lmac_ring = TRUE,
|
||||
.ring_dir = HAL_SRNG_SRC_RING,
|
||||
/* reg_start is not set because LMAC rings are not accessed
|
||||
* from host
|
||||
*/
|
||||
.reg_start = {},
|
||||
.reg_size = {},
|
||||
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||
},
|
||||
{ /* RXDMA_DST */
|
||||
.start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
|
||||
.max_rings = 1,
|
||||
.entry_size = sizeof(struct reo_entrance_ring) >> 2,
|
||||
.lmac_ring = TRUE,
|
||||
.ring_dir = HAL_SRNG_DST_RING,
|
||||
/* reg_start is not set because LMAC rings are not accessed
|
||||
* from host
|
||||
*/
|
||||
.reg_start = {},
|
||||
.reg_size = {},
|
||||
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||
},
|
||||
{ /* RXDMA_MONITOR_BUF */
|
||||
.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
|
||||
.max_rings = 1,
|
||||
.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
|
||||
.lmac_ring = TRUE,
|
||||
.ring_dir = HAL_SRNG_SRC_RING,
|
||||
/* reg_start is not set because LMAC rings are not accessed
|
||||
* from host
|
||||
*/
|
||||
.reg_start = {},
|
||||
.reg_size = {},
|
||||
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||
},
|
||||
{ /* RXDMA_MONITOR_STATUS */
|
||||
.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
|
||||
.max_rings = 1,
|
||||
.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
|
||||
.lmac_ring = TRUE,
|
||||
.ring_dir = HAL_SRNG_SRC_RING,
|
||||
/* reg_start is not set because LMAC rings are not accessed
|
||||
* from host
|
||||
*/
|
||||
.reg_start = {},
|
||||
.reg_size = {},
|
||||
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||
},
|
||||
{ /* RXDMA_MONITOR_DST */
|
||||
.start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
|
||||
.max_rings = 1,
|
||||
.entry_size = sizeof(struct reo_entrance_ring) >> 2,
|
||||
.lmac_ring = TRUE,
|
||||
.ring_dir = HAL_SRNG_DST_RING,
|
||||
/* reg_start is not set because LMAC rings are not accessed
|
||||
* from host
|
||||
*/
|
||||
.reg_start = {},
|
||||
.reg_size = {},
|
||||
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||
},
|
||||
{ /* RXDMA_MONITOR_DESC */
|
||||
.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
|
||||
.max_rings = 1,
|
||||
.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
|
||||
.lmac_ring = TRUE,
|
||||
.ring_dir = HAL_SRNG_SRC_RING,
|
||||
/* reg_start is not set because LMAC rings are not accessed
|
||||
* from host
|
||||
*/
|
||||
.reg_start = {},
|
||||
.reg_size = {},
|
||||
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||
},
|
||||
{ /* DIR_BUF_RX_DMA_SRC */
|
||||
.start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
|
||||
.max_rings = 1,
|
||||
.entry_size = 2,
|
||||
.lmac_ring = TRUE,
|
||||
.ring_dir = HAL_SRNG_SRC_RING,
|
||||
/* reg_start is not set because LMAC rings are not accessed
|
||||
* from host
|
||||
*/
|
||||
.reg_start = {},
|
||||
.reg_size = {},
|
||||
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||
},
|
||||
#ifdef WLAN_FEATURE_CIF_CFR
|
||||
{ /* WIFI_POS_SRC */
|
||||
.start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
|
||||
.max_rings = 1,
|
||||
.entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
|
||||
.lmac_ring = TRUE,
|
||||
.ring_dir = HAL_SRNG_SRC_RING,
|
||||
/* reg_start is not set because LMAC rings are not accessed
|
||||
* from host
|
||||
*/
|
||||
.reg_start = {},
|
||||
.reg_size = {},
|
||||
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||
},
|
||||
#ifdef QCA_WIFI_QCA8074
|
||||
void hal_qca8074_attach(struct hal_soc *hal);
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* hal_get_srng_ring_id() - get the ring id of a descriped ring
|
||||
@@ -639,7 +109,7 @@ QDF_STATUS hal_set_one_shadow_config(void *hal_soc,
|
||||
{
|
||||
uint32_t target_register;
|
||||
struct hal_soc *hal = (struct hal_soc *)hal_soc;
|
||||
struct hal_hw_srng_config *srng_config = &hw_srng_table[ring_type];
|
||||
struct hal_hw_srng_config *srng_config = &hal->hw_srng_table[ring_type];
|
||||
int shadow_config_index = hal->num_shadow_registers_configured;
|
||||
|
||||
if (shadow_config_index >= MAX_SHADOW_REGISTERS) {
|
||||
@@ -674,10 +144,11 @@ QDF_STATUS hal_set_one_shadow_config(void *hal_soc,
|
||||
QDF_STATUS hal_construct_shadow_config(void *hal_soc)
|
||||
{
|
||||
int ring_type, ring_num;
|
||||
struct hal_soc *hal = (struct hal_soc *)hal_soc;
|
||||
|
||||
for (ring_type = 0; ring_type < MAX_RING_TYPES; ring_type++) {
|
||||
struct hal_hw_srng_config *srng_config =
|
||||
&hw_srng_table[ring_type];
|
||||
&hal->hw_srng_table[ring_type];
|
||||
|
||||
if (ring_type == CE_SRC ||
|
||||
ring_type == CE_DST ||
|
||||
@@ -743,18 +214,33 @@ error:
|
||||
|
||||
static void hal_target_based_configure(struct hal_soc *hal)
|
||||
{
|
||||
struct hif_target_info *tgt_info =
|
||||
hif_get_target_info_handle(hal->hif_handle);
|
||||
|
||||
switch (tgt_info->target_type) {
|
||||
switch (hal->target_type) {
|
||||
#ifdef QCA_WIFI_QCA6290
|
||||
case TARGET_TYPE_QCA6290:
|
||||
hal->use_register_windowing = true;
|
||||
hal_qca6290_attach(hal);
|
||||
break;
|
||||
#endif
|
||||
#ifdef QCA_WIFI_QCA8074
|
||||
case TARGET_TYPE_QCA8074:
|
||||
hal_qca8074_attach(hal);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t hal_get_target_type(struct hal_soc *hal)
|
||||
{
|
||||
struct hif_target_info *tgt_info =
|
||||
hif_get_target_info_handle(hal->hif_handle);
|
||||
|
||||
return tgt_info->target_type;
|
||||
}
|
||||
|
||||
qdf_export_symbol(hal_get_target_type);
|
||||
|
||||
/**
|
||||
* hal_attach - Initialize HAL layer
|
||||
* @hif_handle: Opaque HIF handle
|
||||
@@ -810,6 +296,7 @@ void *hal_attach(void *hif_handle, qdf_device_t qdf_dev)
|
||||
|
||||
qdf_spinlock_create(&hal->register_access_lock);
|
||||
hal->register_window = 0;
|
||||
hal->target_type = hal_get_target_type(hal);
|
||||
|
||||
hal_target_based_configure(hal);
|
||||
|
||||
@@ -1351,6 +838,7 @@ qdf_export_symbol(hal_srng_cleanup);
|
||||
*/
|
||||
uint32_t hal_srng_get_entrysize(void *hal_soc, int ring_type)
|
||||
{
|
||||
struct hal_soc *hal = (struct hal_soc *)hal_soc;
|
||||
struct hal_hw_srng_config *ring_config =
|
||||
HAL_SRNG_CONFIG(hal, ring_type);
|
||||
return ring_config->entry_size << 2;
|
||||
@@ -1366,6 +854,7 @@ qdf_export_symbol(hal_srng_get_entrysize);
|
||||
*/
|
||||
uint32_t hal_srng_max_entries(void *hal_soc, int ring_type)
|
||||
{
|
||||
struct hal_soc *hal = (struct hal_soc *)hal_soc;
|
||||
struct hal_hw_srng_config *ring_config =
|
||||
HAL_SRNG_CONFIG(hal, ring_type);
|
||||
|
||||
@@ -1375,6 +864,7 @@ qdf_export_symbol(hal_srng_max_entries);
|
||||
|
||||
enum hal_srng_dir hal_srng_get_dir(void *hal_soc, int ring_type)
|
||||
{
|
||||
struct hal_soc *hal = (struct hal_soc *)hal_soc;
|
||||
struct hal_hw_srng_config *ring_config =
|
||||
HAL_SRNG_CONFIG(hal, ring_type);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user